Test mode control circuit suitable for dual power rails and control method thereof

Abstract

The invention discloses a test mode control circuit suitable for dual power rails and a control method thereof.The test mode control circuit comprises a test mode judgment circuit and a logic frequency division output circuit, and the test mode judgment circuit compares an input signal VIN with a bias voltage VBIAS and generates an output signal OUT; and the logic frequency division output circuit generates a test mode control signal TESTMODE from the output signal OUT. The circuit structure is simple, the operation steps are simple, power consumption is almost zero, pins are saved, and node information in the circuit can be conveniently tested.

Description

Technical Field

[0001] The present invention relates to a test mode control circuit and a control method thereof, in particular to a test mode control circuit and a control method thereof suitable for dual power rails, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] At present, as the scale of integrated circuits becomes larger and the design becomes more complex, the difficulty of circuit testing will also increase. How to efficiently and conveniently test the overall performance of the circuit has become a new difficulty and challenge. The test of the chip before delivery generally includes CP (chip proding) and FT (final test), and large-scale circuits generally do not perform CP tests. Therefore, if you want to test its internal nodes after the chip is packaged, you need to add some test control circuits to fully grasp the chip performance. At present, the chip test mode control circuit is relatively complex, the test operation is relatively cumbersome, and some chip tests will reserve additional output pins, resulting in a waste of resources. Therefore, a good testability design solution can not only optimize the test steps to save costs, but also save pins and design complexity. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a test mode control circuit and a control method thereof suitable for dual power rails, optimize the test steps and solve the pin and design complexity.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A test mode control circuit suitable for dual power rails includes a test mode judgment circuit and a logic frequency division output circuit. The test mode judgment circuit compares the magnitudes of an input signal VIN and a bias voltage VBIAS and generates an output signal OUT. The logic frequency division output circuit generates a test mode control signal TEST_MODE from the output signal OUT.

[0005] Further, the test mode judgment circuit comprises a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a resistor R1 and a capacitor C1, the source of the PMOS tube M1 is connected to the input signal VIN, the gate of the PMOS tube M1 is connected to the bias voltage VBIAS, the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and one end of the resistor R1, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M3, and the source of the NMOS tube M3 is connected to the The electrode of the resistor R1 is connected to the drain of the NMOS tube M4, the source of the NMOS tube M4 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5, the gate of the NMOS tube M2, the gate of the NMOS tube M3, the gate of the NMOS tube M4 and the gate of the NMOS tube M5 are grounded, the other end of the resistor R1 is connected to the drain of the NMOS tube M6 and one end of the capacitor C1 to generate an output signal OUT, the gate of the NMOS tube M6 is connected to the enable control signal TST_EN, and the source of the NMOS tube M6 and the other end of the capacitor C1 are grounded.

[0006] Furthermore, the PMOS tube M1 is an enhanced PMOS switch tube, and the NMOS tube M6 is an enhanced NMOS switch tube.

[0007] Furthermore, the NMOS tube M2 , the NMOS tube M3 , the NMOS tube M4 and the NMOS tube M5 are depletion-type NMOS tubes.

[0008] Furthermore, the logic frequency division output circuit comprises a Schmitt trigger SMT1, an inverter INV1, a D flip-flop DFF1, a D flip-flop DFF2, a D flip-flop DFF3, a three-input NAND gate NAND1 and an inverter INV2, the input end of the Schmitt trigger SMT1 is connected to the output signal OUT, the output end of the Schmitt trigger SMT1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the CLK end of the D flip-flop DFF1, and the output end of the D flip-flop DFF1 is connected to the CLK end of the D flip-flop DFF1. The terminal is connected to the CLK terminal of the D flip-flop DFF2 and the D terminal of the D flip-flop DFF1, the Q terminal of the D flip-flop DFF1 is connected to the first input terminal of the three-input NAND gate NAND1, and the The CLK terminal of the D flip-flop DFF3 and the D terminal of the D flip-flop DFF2 are connected, the Q terminal of the D flip-flop DFF2 is connected to the second input terminal of the three-input NAND gate NAND1, and the The end is connected to the D end of the D flip-flop DFF3, the Q end of the D flip-flop DFF3 is connected to the third input end of the three-input NAND gate NAND1, the RST end of the D flip-flop DFF1, the RST end of the D flip-flop DFF2 and the RST end of the D flip-flop DFF3 are connected to the reset signal RSET, the output end of the three-input NAND gate NAND1 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 generates a test mode control signal TEST_MODE.

[0009] Furthermore, the D flip-flop DFF1, the D flip-flop DFF2, and the D flip-flop DFF3 respectively constitute three 2-frequency dividers.

[0010] Furthermore, it also includes a control signal output circuit, which includes n groups of control signal output branch circuits, and the xth group of control signal output branch circuits includes a NAND gate NAND2 and an inverter INV3, wherein 0<x≤n, the first input end of the NAND gate NAND2 is connected to the xth group of selection control signal TESTx, the second input end of the NAND gate NAND2 is connected to the test mode control signal TEST_MODE, the output end of the NAND gate NAND2 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 generates the xth group of control output signal TEST_OUTx.

[0011] A test mode control method for a test mode control circuit for dual power rails comprises the following steps: In the normal working mode, the relationship between the input signal VIN, the bias voltage VBIAS and the output signal OUT is VBIAS>VIN>OUT. At this time, the gate-source voltage VGS1 of the PMOS tube M1 is positive, the PMOS tube M1 is cut off, the threshold voltage VTH2 of the NMOS tubes M2, M3, M4 and M5 is negative, and the gate-source voltage VGS2 of the NMOS tubes M2, M3, M4 and M5 is 0. At this time, the NMOS tubes M2, M3, M4 and M5 are an equivalent pull-down current source. Therefore, when the PMOS tube M1 is cut off, the output signal OUT is always pulled down by the equivalent pull-down current source, and the chip always maintains the normal working mode; When entering the test mode, the input signal VIN is re-injected to make VIN>VBIAS and VIN-VBIAS>VTHp, VTHp is the threshold voltage of the PMOS tube M1, at this time, the gate-source voltage VGS1 of the PMOS tube M1 is negative, the PMOS tube M1 is turned on, and the output signal OUT is pulled high by the input signal VIN, and the chip enters the test mode; The output signal OUT is filtered out of interference signals through the RC filter circuit composed of resistor R1 and capacitor C1. When the test mode ends, the enable control signal TST_EN is pulled high through the fuse or efuse function. At this time, the NMOS tube M6 is turned on, the output signal OUT is pulled low, and the system exits the test mode. After the output signal OUT passes through the Schmitt trigger SMT1 and the inverter INV1, it passes through three 2-dividers composed of D flip-flops DFF1, D flip-flops DFF2 and D flip-flops DFF3. The output signal OUT is divided by 2, 4, 8 and the three-input NAND gate NAND1 in sequence to generate a periodic signal that is high for one cycle after a low level for every seven cycles. The periodic signal outputs the test mode control signal TEST_MODE through the inverter INV2; The test mode control signal TEST_MODE and the xth group selection control signal TESTx are coupled through a NAND gate NAND2 and an inverter INV3 to output an xth group control output signal TEST_OUTx for controlling the test function of the xth internal node.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a test mode control circuit and a control method suitable for dual power rails, the circuit structure is simple, and the function switching of the test mode can be completed by only using 6 transistors; the operation steps of the present invention are simple, and the test mode can be entered only when the input signal VIN is higher than the bias voltage VBIAS by a threshold voltage VTHp of a PMOS tube M1, and when the chip works in the normal working mode, the power consumption of the test mode control circuit is almost zero, and other parameters of the chip are not affected, and the voltage or current information of the internal node of the chip can be output through the output pin of the multiplexing circuit, which can save pins and conveniently test the internal node information of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a test mode control circuit suitable for dual power rails of the present invention.

[0014] Figure 2 It is a schematic diagram of the test mode judgment circuit of the present invention.

[0015] Figure 3 It is a schematic diagram of the logic frequency division output circuit of the present invention.

[0016] Figure 4 It is a schematic diagram of a control signal output circuit of the present invention. DETAILED DESCRIPTION

[0017] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0018] like Figure 1 As shown, a test mode control circuit suitable for dual power rails of the present invention includes a test mode judgment circuit and a logic frequency division output circuit. The test mode judgment circuit compares the magnitude of the input signal VIN and the bias voltage VBIAS and generates an output signal OUT. The logic frequency division output circuit generates a test mode control signal TEST_MODE from the output signal OUT.

[0019] The test mode judgment circuit determines whether the test mode control circuit enters the test mode by judging whether the difference between the input signal VIN and the bias voltage VBIAS is greater than the threshold voltage VTHp of a PMOS tube M1. Both the input signal VIN and the bias voltage VBIAS can be clock signals, but the test mode is entered only when VIN-VBIAS>VTHp, and the test mode is exited at other times. The logic frequency division output circuit is used to divide the output signal OUT of the test mode judgment circuit. One cycle is output as a high level every seven cycles. Each high level period can control the output of the voltage or current information of the internal node to be tested.

[0020] like Figure 2 As shown, the test mode judgment circuit includes a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a resistor R1 and a capacitor C1, the source of the PMOS tube M1 is connected to the input signal VIN, the gate of the PMOS tube M1 is connected to the bias voltage VBIAS, the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and one end of the resistor R1, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the The drain of the NMOS tube M4 is connected, the source of the NMOS tube M4 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5, the gate of the NMOS tube M2, the gate of the NMOS tube M3, the gate of the NMOS tube M4 and the gate of the NMOS tube M5 are grounded, the other end of the resistor R1 is connected to the drain of the NMOS tube M6 and one end of the capacitor C1 to generate an output signal OUT, the gate of the NMOS tube M6 is connected to the enable control signal TST_EN, and the source of the NMOS tube M6 and the other end of the capacitor C1 are grounded.

[0021] Among them, the PMOS tube M1 adopts an enhanced PMOS switch tube, and the NMOS tube M6 adopts an enhanced NMOS switch tube. The NMOS tubes M2, M3, M4 and M5 adopt depletion-type NMOS tubes, and the gates of the NMOS tubes M2, M3, M4 and M5 are grounded, so that the gate-source voltage VGS2 of the NMOS tubes M2, M3, M4 and M5 can be fixed to 0, and used as a fixed current source.

[0022] After the chip completes the test, the enable control signal TST_EN is pulled high through functions such as fuse or efuse. At this time, the NMOS tube M6 will be turned on all the time, and the output signal OUT will be permanently pulled low. After the system exits the test mode, the user cannot enter the test mode again, which prevents the user from accidentally entering the test mode in the normal working mode.

[0023] like Figure 3 As shown, the logic frequency division output circuit includes a Schmitt trigger SMT1, an inverter INV1, a D flip-flop DFF1, a D flip-flop DFF2, a D flip-flop DFF3, a three-input NAND gate NAND1 and an inverter INV2, the input end of the Schmitt trigger SMT1 is connected to the output signal OUT, the output end of the Schmitt trigger SMT1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the CLK end of the D flip-flop DFF1, and the output end of the D flip-flop DFF1 is connected to the CLK end of the D flip-flop DFF1. The terminal is connected to the CLK terminal of the D flip-flop DFF2 and the D terminal of the D flip-flop DFF1, the Q terminal of the D flip-flop DFF1 is connected to the first input terminal of the three-input NAND gate NAND1, and the The CLK terminal of the D flip-flop DFF3 and the D terminal of the D flip-flop DFF2 are connected, the Q terminal of the D flip-flop DFF2 is connected to the second input terminal of the three-input NAND gate NAND1, and the The end is connected to the D end of the D flip-flop DFF3, the Q end of the D flip-flop DFF3 is connected to the third input end of the three-input NAND gate NAND1, the RST end of the D flip-flop DFF1, the RST end of the D flip-flop DFF2 and the RST end of the D flip-flop DFF3 are connected to the reset signal RSET, the output end of the three-input NAND gate NAND1 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 generates a test mode control signal TEST_MODE.

[0024] The D flip-flop DFF1, the D flip-flop DFF2, and the D flip-flop DFF3 respectively constitute three 2-frequency dividers.

[0025] A test mode control circuit suitable for dual power rails of the present invention further comprises a control signal output circuit, such as Figure 4 As shown, the control signal output circuit includes n groups of control signal output branch circuits, and the xth group of control signal output branch circuits includes a NAND gate NAND2 and an inverter INV3, wherein 0<x≤n, a first input end of the NAND gate NAND2 is connected to the xth group of selection control signals TESTx, a second input end of the NAND gate NAND2 is connected to the test mode control signal TEST_MODE, an output end of the NAND gate NAND2 is connected to an input end of the inverter INV3, and an output end of the inverter INV3 generates an xth group of control output signals TEST_OUTx.

[0026] A test mode control method for a test mode control circuit for dual power rails comprises the following steps: In normal working mode, the relationship between the input signal VIN, the bias voltage VBIAS and the output signal OUT is VBIAS>VIN>OUT. At this time, the gate-source voltage VGS1 of the PMOS tube M1 is positive, the PMOS tube M1 is cut off, the threshold voltage VTH2 of the NMOS tubes M2, M3, M4 and M5 is negative, and the gate-source voltage VGS2 of the NMOS tubes M2, M3, M4 and M5 is 0. At this time, the NMOS tubes M2, M3, M4 and M5 are an equivalent pull-down current source. Therefore, when the PMOS tube M1 is cut off, the output signal OUT is always pulled down by the equivalent pull-down current source, and the chip always maintains the normal working mode.

[0027] When entering the test mode, the input signal VIN is re-injected to make VIN>VBIAS and VIN-VBIAS>VTHp, VTHp is the threshold voltage of the PMOS tube M1, at this time, the gate-source voltage VGS1 of the PMOS tube M1 is negative, the PMOS tube M1 is turned on, and the output signal OUT is pulled high by the input signal VIN, and the chip enters the test mode.

[0028] The output signal OUT is filtered out of interference signals through the RC filter circuit composed of resistor R1 and capacitor C1. When the test mode ends, the enable control signal TST_EN is pulled high through the fuse or efuse function. At this time, the NMOS tube M6 is turned on, the output signal OUT is pulled low, and the system exits the test mode.

[0029] After the output signal OUT passes through the Schmitt trigger SMT1 and the inverter INV1, it passes through three 2-dividers composed of D flip-flops DFF1, D flip-flops DFF2 and D flip-flops DFF3. The output signal OUT is divided by 2, 4, 8 and the three-input NAND gate NAND1 in sequence to generate a periodic signal that is high for one cycle after a low level for every seven cycles. The periodic signal outputs the test mode control signal TEST_MODE through the inverter INV2.

[0030] The test mode control signal TEST_MODE and the xth group selection control signal TESTx are coupled through a NAND gate NAND2 and an inverter INV3 to output an xth group control output signal TEST_OUTx for controlling the test function of the xth internal node.

[0031] The present invention provides a test mode control circuit and a control method suitable for dual power rails. The circuit structure is simple, and the function switching of the test mode can be completed by only using 6 transistors. The present invention has simple operation steps, and the test mode can be entered only when the input signal VIN is higher than the bias voltage VBIAS by a threshold voltage VTHp of a PMOS tube M1. When the chip works in the normal working mode, the power consumption of the test mode control circuit is almost zero, and other parameters of the chip are not affected. The voltage or current information of the internal node of the chip can be output through the output pin of the multiplexing circuit, which can save pins and conveniently test the internal node information of the circuit.

[0032] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A test mode control circuit suitable for dual power rails, characterized in that: It includes a test mode judgment circuit and a logic frequency division output circuit. The test mode judgment circuit compares the input signal VIN and the bias voltage VBIAS and generates an output signal OUT. The logic frequency division output circuit generates a test mode control signal TEST_MODE from the output signal OUT.

2. A test mode control circuit suitable for dual power rails according to claim 1, characterized in that: The test mode judgment circuit comprises a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a resistor R1 and a capacitor C1, the source of the PMOS tube M1 is connected to an input signal VIN, the gate of the PMOS tube M1 is connected to a bias voltage VBIAS, the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and one end of the resistor R1, the source of the NMOS tube M2 is connected to the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the NMOS tube M4, and the gate of the NMOS tube M5 is connected to the bias voltage VBIAS. The drain of the MOS tube M4 is connected, the source of the NMOS tube M4 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5, the gate of the NMOS tube M2, the gate of the NMOS tube M3, the gate of the NMOS tube M4 and the gate of the NMOS tube M5 are grounded, the other end of the resistor R1 is connected to the drain of the NMOS tube M6 and one end of the capacitor C1 to generate an output signal OUT, the gate of the NMOS tube M6 is connected to the enable control signal TST_EN, and the source of the NMOS tube M6 and the other end of the capacitor C1 are grounded.

3. A test mode control circuit suitable for dual power rails according to claim 2, characterized in that: The PMOS tube M1 is an enhanced PMOS switch tube, and the NMOS tube M6 is an enhanced NMOS switch tube.

4. The test mode control circuit suitable for dual power rails according to claim 2, characterized in that: The NMOS tube M2 , the NMOS tube M3 , the NMOS tube M4 and the NMOS tube M5 are depletion-type NMOS tubes.

5. The test mode control circuit suitable for dual power rails according to claim 1, characterized in that: The logic frequency division output circuit comprises a Schmitt trigger SMT1, an inverter INV1, a D flip-flop DFF1, a D flip-flop DFF2, a D flip-flop DFF3, a three-input NAND gate NAND1 and an inverter INV2, the input end of the Schmitt trigger SMT1 is connected to the output signal OUT, the output end of the Schmitt trigger SMT1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the CLK end of the D flip-flop DFF1, and the output end of the D flip-flop DFF1 is connected to the CLK end of the D flip-flop DFF1. The terminal is connected to the CLK terminal of the D flip-flop DFF2 and the D terminal of the D flip-flop DFF1, the Q terminal of the D flip-flop DFF1 is connected to the first input terminal of the three-input NAND gate NAND1, and the The CLK terminal of the D flip-flop DFF3 and the D terminal of the D flip-flop DFF2 are connected, the Q terminal of the D flip-flop DFF2 is connected to the second input terminal of the three-input NAND gate NAND1, and the The end is connected to the D end of the D flip-flop DFF3, the Q end of the D flip-flop DFF3 is connected to the third input end of the three-input NAND gate NAND1, the RST end of the D flip-flop DFF1, the RST end of the D flip-flop DFF2 and the RST end of the D flip-flop DFF3 are connected to the reset signal RSET, the output end of the three-input NAND gate NAND1 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 generates a test mode control signal TEST_MODE.

6. The test mode control circuit suitable for dual power rails according to claim 5, characterized in that: The D flip-flop DFF1, the D flip-flop DFF2, and the D flip-flop DFF3 respectively constitute three 2-frequency dividers.

7. The test mode control circuit suitable for dual power rails according to claim 1, characterized in that: It also includes a control signal output circuit, which includes n groups of control signal output branch circuits. The xth group of control signal output branch circuits includes a NAND gate NAND2 and an inverter INV3, wherein 0<x≤n, a first input end of the NAND gate NAND2 is connected to the xth group of selection control signal TESTx, a second input end of the NAND gate NAND2 is connected to the test mode control signal TEST_MODE, an output end of the NAND gate NAND2 is connected to the input end of the inverter INV3, and an output end of the inverter INV3 generates the xth group of control output signal TEST_OUTx.

8. A test mode control method for a test mode control circuit suitable for dual power rails according to any one of claims 1 to 7, characterized in that The following steps are involved: In the normal working mode, the relationship between the input signal VIN, the bias voltage VBIAS and the output signal OUT is VBIAS>VIN>OUT. At this time, the gate-source voltage VGS1 of the PMOS tube M1 is positive, the PMOS tube M1 is cut off, the threshold voltage VTH2 of the NMOS tubes M2, M3, M4 and M5 is negative, and the gate-source voltage VGS2 of the NMOS tubes M2, M3, M4 and M5 is 0. At this time, the NMOS tubes M2, M3, M4 and M5 are an equivalent pull-down current source. Therefore, when the PMOS tube M1 is cut off, the output signal OUT is always pulled down by the equivalent pull-down current source, and the chip always maintains the normal working mode; When entering the test mode, the input signal VIN is re-injected to make VIN>VBIAS and VIN-VBIAS>VTHp, VTHp is the threshold voltage of the PMOS tube M1, at this time, the gate-source voltage VGS1 of the PMOS tube M1 is negative, the PMOS tube M1 is turned on, and the output signal OUT is pulled high by the input signal VIN, and the chip enters the test mode; The output signal OUT is filtered out of interference signals through the RC filter circuit composed of resistor R1 and capacitor C1. When the test mode ends, the enable control signal TST_EN is pulled high through the fuse or efuse function. At this time, the NMOS tube M6 is turned on, the output signal OUT is pulled low, and the system exits the test mode. After the output signal OUT passes through the Schmitt trigger SMT1 and the inverter INV1, it passes through three 2-dividers composed of D flip-flops DFF1, D flip-flops DFF2 and D flip-flops DFF3. The output signal OUT is divided by 2, 4, 8 and the three-input NAND gate NAND1 in sequence to generate a periodic signal that is high for one cycle after a low level for every seven cycles. The periodic signal outputs the test mode control signal TEST_MODE through the inverter INV2; The test mode control signal TEST_MODE and the xth group selection control signal TESTx are coupled through a NAND gate NAND2 and an inverter INV3 to output an xth group control output signal TEST_OUTx for controlling the test function of the xth internal node.

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