Method, device and equipment for testing error correction capability of master control of flash memory
By using cache registers instead of flash Array for data operations in flash memory tests, the problem of bit flip error during data reading in the existing technology is solved, and efficient and accurate flash master error correction ability test is achieved, reducing the test cost .
Patent Information
- Application Number
- CN202411513231.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-18
AI Technical Summary
The existing Flash Master ECC capability testing method has bit flip errors when reading data, resulting in inaccurate test results, and high cost during batch testing and large particle overhead.
By writing and reading out the flash-based cache registers, instead of storing data through the flash-based Array, avoiding the extra bit flip caused by array, the simulated injected bit flips is more accurate.
It realizes accurate and efficient flash memory master error correction capability testing, shortens test time, improves test efficiency, reduces test costs, and does not affect the life of flash memory.
Smart Images
Figure CN119479762A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory testing technology, and in particular to a method, device and equipment for testing the error correction capability of a flash memory master. Background Art
[0002] The existing master control ECC capability test is generally to simulate the injection of bit flip data into the NAND flash memory, and then read it out through LDPC decoding to determine whether the single decoding is successful. The above method has the following problems:
[0003] First, due to the characteristics of NAND flash memory, bit flipping may occur when reading data, resulting in errors in the original data of the simulated bit flip injection;
[0004] Second, reading data from NAND flash memory will cause bit flipping, so when reading the original data that has already been flipped by analog injection, the error will increase further;
[0005] Third, the above two points will gradually increase the number of bit flips as the number of times the particles are erased and written increases, which will lead to more inaccurate data;
[0006] Fourthly, there is also a certain granular overhead cost during batch testing, because this capability test requires a large number of decoding times to support data credibility. Summary of the invention
[0007] The purpose of the embodiments of the present application is to provide a method, device and equipment for testing the error correction capability of a flash memory master, so as to solve the above-mentioned problems existing in the prior art and to accurately and efficiently test the error correction capability of the flash memory master.
[0008] In a first aspect, a method for testing the error correction capability of a flash memory master is provided, which is applied to a flash memory master of a flash memory mobile storage device, wherein the flash memory mobile storage device further comprises: a flash memory; the flash memory is provided with a cache register, and the method may comprise:
[0009] Obtain configured test data and corresponding error correction test data;
[0010] Performing random bit flipping on the error correction test data to obtain flipped test data;
[0011] Writing the flip test data into the cache register to obtain a first write address;
[0012] Reading data corresponding to the first write address from the cache register, and decoding the data to obtain decoded data;
[0013] Based on the comparison result between the test data and the decoded data, an error correction capability test result is generated.
[0014] In an optional implementation, the method for acquiring error correction test data includes:
[0015] Processing the test data using an error correction algorithm to obtain processed data;
[0016] Writing the processed data into the cache register to obtain a second write address;
[0017] The data corresponding to the second write address is read from the cache register to obtain the error correction test data.
[0018] In an optional implementation, performing random bit flipping on the error correction test data to obtain flipped test data includes:
[0019] Randomly select at least one bit from the error correction test data;
[0020] The data of the selected bits are bit-flipped to obtain flipped test data.
[0021] In an optional implementation, performing random bit flipping on the error correction test data to obtain flipped test data further includes:
[0022] The error correction test data is subjected to multiple random bit flips to obtain multiple different flip test data; wherein the flipped bits are different each time the bits are flipped.
[0023] In an optional implementation, generating an error correction capability test result based on a comparison result between the test data and the decoded data includes:
[0024] Based on the comparison result of the test data and the decoded data corresponding to different flip test data, the error correction capability test result is obtained.
[0025] In an optional implementation, after decoding the data, the method further includes:
[0026] If the decoding of the data fails, an error correction capability test result is directly generated.
[0027] In a second aspect, a device for testing the error correction capability of a flash memory master is provided, and the device may include:
[0028] An acquisition unit, used to acquire configured test data and corresponding error correction test data;
[0029] A flip unit, used for performing random bit flipping on the error correction test data to obtain flip test data;
[0030] A writing unit, used for writing the flip test data into a cache register of the flash memory to obtain a first writing address;
[0031] a reading unit, configured to read data corresponding to the first write address from the cache register, and decode the data to obtain decoded data;
[0032] A generating unit is used to generate an error correction capability test result based on a comparison result between the test data and the decoded data.
[0033] In a third aspect, an electronic device is provided, the electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;
[0034] Memory, used to store computer programs;
[0035] The processor is used to implement any method step described in the first aspect when executing the program stored in the memory.
[0036] In a fourth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any method step described in the first aspect is implemented.
[0037] This application writes and reads data into and out of a flash memory-based cache register instead of storing data through a flash memory array, thus avoiding extra bit flips caused by the array, and the number of simulated injected bit flips is more accurate. This application has higher test efficiency and does not require actual reading and writing of flash memory, so there is no need to wait for tR and tProg. Therefore, when testing in large quantities, it can shorten the test time and improve test efficiency. This application saves test costs. The error correction capability of the flash memory master needs to be tested in large quantities. Reading and writing only the cache register does not affect the life of the flash memory, and it can continue to be used in other ways later. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0039] Figure 1 A flowchart of a method for testing the error correction capability of a flash memory master controller provided in an embodiment of the present application;
[0040] Figure 2An architectural diagram of a method for testing the error correction capability of a flash memory master provided in an embodiment of the present application;
[0041] Figure 3 An architecture diagram of a method for testing the error correction capability of a conventional flash memory master controller provided in an embodiment of the present application;
[0042] Figure 4 A schematic diagram of the structure of a flash memory master error correction capability testing device provided in an embodiment of the present application;
[0043] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0045] The existing patent CN113470728 also discloses a method for testing error correction capability, but the method of obtaining data in this scheme still requires erasing and programming the NAND flash. The first read data is still read from the array to the page register. There is still a possibility of bit flipping in this step, and subsequent tests are based on this data, so this error will exist in the entire test. Assuming that this part of the benchmark data has 10 bit flips when read, additional simulation injection is performed on this basis to increase bit flips. If the LPDC error correction capability of the flash memory master is 100 bits, then when the test result of this data is 90 bits, it will be judged that the error correction has failed, and the error correction capability obtained is 90 bits. The amount of bit flip error in the basic data determines the accuracy deviation of the test results in the file.
[0046] At the same time, the test method of the patent is not rigorous. The error correction capability of LPDC is a probability problem. Whether it is successful or not is related to the position combination of the bit flip. For the same 100 bit flips, different position combinations of bit flips will produce different test results. Therefore, the error correction capability cannot be determined by the decoding result of a certain bit flip. The test scheme mentioned in the comparison document is 1bit, 2bit, 3bit... In this way, the number of bit flips is gradually increased. Each piece of data adds a bit flip to the previous piece of data, and, so the final conclusion is the capability under a certain bit flip. Since the original data obtained itself has bit flips, the bit flip position of this part is fixed when testing based on this basic data. Therefore, the error correction capability obtained by testing on this basis is inaccurate, and there is a probability of large deviations.
[0047] In order to avoid the problems existing in the above-mentioned patents and other prior arts, the present application writes and reads data into and out of a flash memory-based cache register instead of storing data through a flash memory array, thereby avoiding additional bit flips caused by the array, making the number of bit flips injected by simulation more accurate; at the same time, when performing a large number of tests, the test time is shortened and the test efficiency is improved.
[0048] The preferred embodiments of the present application are described below in conjunction with the drawings in the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In addition, the embodiments and features in the embodiments of the present application may be combined with each other if there is no conflict.
[0049] Figure 1 A flowchart of a method for testing the error correction capability of a flash memory master controller provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method may include:
[0050] Step S110, obtaining configured test data and corresponding error correction test data; performing random bit flipping on the error correction test data to obtain flipped test data.
[0051] In the embodiment of the present application, the flash memory master error correction capability test method is applied to the flash memory master of the flash memory mobile storage, and is used to test the error correction capability of the flash memory master; the flash memory mobile storage is provided with a flash memory master and a flash memory; the flash memory is provided with a cache register; specifically, the flash memory is a NAND flash memory. Specifically, the flash memory mobile storage may include SSD, UFC, SD and USB flash disk, etc.
[0052] In the embodiment of the present application, the test data can be customized by the user according to the test requirements, and can be various model data such as fixed pattern, random pattern, etc.
[0053] In an embodiment of the present application, a method for obtaining error correction test data includes: processing the test data using an error correction algorithm to obtain processed data; writing the processed data into a cache register to obtain a second write address; reading data corresponding to the second write address from the cache register to obtain error correction test data.
[0054] In the embodiment of the present application, the error correction algorithm may be different types of error correction algorithms (ECC) such as LDPC and BCH.
[0055] In the embodiment of the present application, the write instruction is changed so that the flash memory master only writes into the cache register of the flash memory when writing input into the flash memory, but actually writes into the array.
[0056] In an embodiment of the present application, random bit flipping is performed on error correction test data, including: randomly selecting N bits from the error correction test data; bit flipping the selected N bits of data to obtain flipped test data; wherein N represents the number of bits flipped, and N is a positive integer.
[0057] In an embodiment of the present application, the error correction test data can be randomly bit flipped by randomly injecting N bit flips; the bit flip parameters can also be customized according to actual needs, and the bit flip control can be performed based on the bit flip parameters; for example, random continuous bit flips can be defined, etc.
[0058] In an embodiment of the present application, multiple random bit flips are performed on the error correction test data to obtain multiple different flip test data; specifically, the bits flipped in each bit flip are different; the number of random bit flips can also be customized according to actual needs.
[0059] Step S120, writing the flip test data into the cache register to obtain a first write address; reading data corresponding to the first write address from the cache register, and decoding the data to obtain decoded data.
[0060] In an embodiment of the present application, for any flip test data, the flip test data is written into the cache register without LDPC encoding, and the corresponding first write address is determined; the flash memory master decodes the data of the first write address through LDPC decoding to obtain the decoded data corresponding to the flip test data.
[0061] In the embodiment of the present application, decoding failure may occur during decoding. When the flash memory master fails to decode, it means that the flash memory master has not passed the error correction capability test and the test result is failure.
[0062] Step S130: Generate an error correction capability test result based on the comparison result between the test data and the decoded data.
[0063] In an embodiment of the present application, if the decoding is successful, then for any decoded data, if the decoded data is consistent with the test data, it indicates that the test is successful; if the decoded data is inconsistent with the test data, it indicates that the test has failed, and an error correction capability failure test result is directly generated.
[0064] In an embodiment of the present application, based on the number of decoded data consistent with the test data and the number of flipped test data, the success rate of the test success in the case of N bit flips is obtained, which is the test result of the error correction capability of the flash memory master; specifically, the success rate of the test success is the success rate of LDPC decoding.
[0065] For example, if N is 100, the number of flipped test data is 1000, and the number of decoded data consistent with the test data is 998 times, the test result is that the success rate of the test is 99.8% when 100 bits are flipped.
[0066] In another embodiment of the present application, different error correction algorithms correspond to different strengths. After obtaining the error correction capability test results, the strength of the error correction algorithm can be dynamically adjusted according to the error correction capability test results, and then the error correction test data corresponding to the strength is obtained, and the subsequent test content is completed, thereby obtaining the success rate of the test success under the condition of this strength and N bit flips.
[0067] In another embodiment of the present application, the test data can be processed in sequence using error correction algorithms of different strengths to obtain error correction test data corresponding to error correction algorithms of different strengths, thereby further refining the error correction capability of the flash memory and obtaining a more comprehensive error correction capability test result.
[0068] In another embodiment of the present application, in order to improve the comprehensiveness of the flash memory error correction capability test, the bad block area can be written and read in a targeted manner to determine the degree of damage of the bad block; multiple target write addresses can be obtained based on a random algorithm or by analyzing the flash memory configuration parameters, and the error correction test data can be written to the target write address and read to complete the error correction capability test of each area of the flash memory; targeted testing can also be performed on some areas of the flash memory based on user-defined write addresses.
[0069] In an embodiment of the present application, multiple target write addresses are obtained by analyzing the flash memory configuration parameters, including: based on the flash memory configuration parameters, respectively determining the flash memory capacity, page size and block size; based on the determined page size and block size, determining multiple target write addresses; wherein the multiple target write addresses cover the page addresses of all blocks.
[0070] In one embodiment of the present application, Figure 2As shown, the method for testing the error correction capability of the flash memory master includes the following steps:
[0071] (1) Prepare a basic data pattern (which can be a fixed pattern, random pattern, or other models, defined according to test requirements) as Data A;
[0072] (2) The flash memory master writes the preset Data A into the cache register of the NAND flash memory after LDPC encoding (through specific operations, the NAND flash memory only receives data into the cache register but does not actually write it into the array).
[0073] (3) The flash memory master reads the data in the cache register without LDPC decoding to obtain the preset data and the parity data after LDPC encoding, which is Data B.
[0074] (4) Simulate bit flipping in Data B (generally by randomly injecting N bit flips, or by defining random continuous bit flipping as needed) to obtain Data C;
[0075] (5) The master writes Data C into the cache register of the NAND flash memory again without LDPC encoding;
[0076] (6) The master reads the data of the cache register of the flash memory through LDPC decoding to obtain the data Data D, and determines whether the decoding is successful (the LDPC decoding result is compared with Data A and Data D to see whether they are consistent);
[0077] (7) Repeating steps (4) to (6) multiple times, we can find the probability of successful LDPC decoding when N bits are flipped (assuming that when there are 300 bit flips, the test is repeated 1 million times in total and fails 10 times, then we can find that when there are 300 err bits, the success rate of LDPC decoding is 99.999%).
[0078] like Figure 3 As shown, the current method for testing the master ECC capability is mainly to write data into NAND flash memory after LDPC encoding ( Figure 3 ), and then read out the data without LDPC decoding ( Figure 3 Then, the number of bits flipped is simulated and injected into the read data to obtain the simulated flipped data, and then the data is written into the NAND flash memory again ( Figure 3Path 2), and finally read the data after LDPC decoding ( Figure 3 In path 4), determine whether the decoding is successful.
[0079] By comparing the above-mentioned test method of the flash memory master error correction capability of the present application with the existing method of testing the master ECC capability, it can be found that since the data of the present application is written and read through the cache register of the NAND flash memory, and is not actually written into the NAND Array, no additional bit flips will be generated, and the number of simulated injected bit flips is more accurate; and since there is no need to actually read and write NAND, there is no need to wait for tR and tProg, so when testing in large quantities, the test time can be shortened and the test efficiency can be improved. Furthermore, since a large number of tests are required in this verification, only reading and writing the Cache register does not affect the life of the NAND flash memory, and it can continue to be used in other ways later.
[0080] Corresponding to the above method, the embodiment of the present application also provides a test device for the error correction capability of a flash memory master, such as Figure 4 As shown, the test device for the error correction capability of the flash memory master includes:
[0081] An acquisition unit 410, configured to acquire configured test data and corresponding error correction test data;
[0082] A flip unit 420, used for performing random bit flipping on the error correction test data to obtain flipped test data;
[0083] The writing unit 430 is used to write the flip test data into the cache register of the flash memory to obtain a first writing address;
[0084] The reading unit 440 is used to read the data corresponding to the first write address from the cache register, and decode the data to obtain decoded data;
[0085] The generating unit 450 is used to generate an error correction capability test result based on the comparison result between the test data and the decoded data.
[0086] The functions of each functional unit of the flash memory master error correction capability testing device provided in the above-mentioned embodiments of the present application can be realized through the above-mentioned method steps. Therefore, the specific working process and beneficial effects of each unit in the flash memory master error correction capability testing device provided in the embodiments of the present application will not be repeated here.
[0087] The present application also provides an electronic device, such as Figure 5As shown, it includes a processor 510 , a communication interface 520 , a memory 530 and a communication bus 540 , wherein the processor 510 , the communication interface 520 , and the memory 530 communicate with each other via the communication bus 540 .
[0088] Memory 530, for storing computer programs;
[0089] The processor 510 is used to execute the program stored in the memory 530 to implement the following steps:
[0090] Obtain configured test data and corresponding error correction test data;
[0091] Performing random bit flipping on the error correction test data to obtain flipped test data;
[0092] Writing the flip test data into the cache register of the flash memory to obtain a first write address;
[0093] Reading data corresponding to the first write address from the cache register, and decoding the data to obtain decoded data;
[0094] Based on the comparison results between the test data and the decoded data, an error correction capability test result is generated.
[0095] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.
[0096] The communication interface is used for communication between the above electronic device and other devices.
[0097] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.
[0098] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
[0099] The implementation methods and beneficial effects of the components of the electronic device in the above embodiments to solve the problems can be seen in Figure 1 The various steps in the illustrated embodiment are implemented, therefore, the specific working process and beneficial effects of the electronic device provided by the embodiment of the present application are not repeated here.
[0100] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer executes any of the methods for testing the error correction capability of the flash memory master in the above embodiments.
[0101] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any of the methods for testing the error correction capability of the flash memory master in the above embodiments.
[0102] Those skilled in the art will appreciate that the embodiments in the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt a complete hardware embodiment, a complete software embodiment, or a form of an embodiment combining software and hardware. Moreover, the present application may adopt a form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0103] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0104] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0105] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0106] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.
[0107] Obviously, those skilled in the art can make various changes and modifications to the embodiments in the present application without departing from the spirit and scope of the embodiments in the present application. Thus, if these modifications and variations of the embodiments in the present application fall within the scope of the claims and their equivalents in the embodiments of the present application, the embodiments of the present application are also intended to include these modifications and variations.
Claims
1. A method for testing the error correction capability of a flash memory master, characterized in that: The method is applied to a flash memory master of a flash memory mobile storage, wherein the flash memory mobile storage further comprises: a flash memory; the flash memory is provided with a cache register, and the method comprises: Obtain configured test data and corresponding error correction test data; Performing random bit flipping on the error correction test data to obtain flipped test data; Writing the flip test data into the cache register to obtain a first write address; Reading data corresponding to the first write address from the cache register, and decoding the data to obtain decoded data; Based on the comparison result between the test data and the decoded data, an error correction capability test result is generated.
2. The method according to claim 1, characterized in that The method for acquiring error correction test data comprises: Processing the test data using an error correction algorithm to obtain processed data; Writing the processed data into the cache register to obtain a second write address; The data corresponding to the second write address is read from the cache register to obtain the error correction test data.
3. The method according to claim 1, characterized in that Performing random bit flipping on the error correction test data to obtain flipped test data includes: Randomly select at least one bit from the error correction test data; The data of the selected bits are bit-flipped to obtain flipped test data.
4. The method according to claim 1, characterized in that Performing random bit flipping on the error correction test data to obtain flipped test data also includes: The error correction test data is subjected to multiple random bit flips to obtain multiple different flip test data; wherein the flipped bits are different each time the bits are flipped.
5. The method according to claim 4, characterized in that Generating an error correction capability test result based on a comparison result between the test data and the decoded data, including: Based on the comparison result of the test data and the decoded data corresponding to different flip test data, the error correction capability test result is obtained.
6. The method according to claim 1, characterized in that After decoding the data, the method further comprises: If the decoding of the data fails, an error correction capability test result is directly generated.
7. A flash memory master error correction capability testing device, characterized in that: The device comprises: An acquisition unit, used to acquire configured test data and corresponding error correction test data; A flip unit, used for performing random bit flipping on the error correction test data to obtain flip test data; A writing unit, used for writing the flip test data into a cache register of the flash memory to obtain a first writing address; a reading unit, configured to read data corresponding to the first write address from the cache register, and decode the data to obtain decoded data; A generating unit is used to generate an error correction capability test result based on a comparison result between the test data and the decoded data.
8. An electronic device, characterized in that: The electronic device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, used to implement any method described in claims 1-6 when executing a program stored in a memory.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.