Method for producing semiconductor structural element from wafer by means of selective application of edge insulation

Abstract

The invention relates to a method for producing a plurality of semiconductor structural elements, in particular power semiconductor structural elements, from a wafer (100), comprising the following steps: providing a wafer substrate (108), treating a structured wafer surface (105), applying an edge insulation (103) to the wafer surface (105), and separating the wafer (100) into individual semiconductor structural elements (102a, 102b, 102c).

Description

Technical Field

[0001] The invention relates to a method for producing a semiconductor component from a wafer, wherein an edge insulation of the semiconductor component or of a power electronic device is selectively applied by means of an additive manufacturing process. Background Art

[0002] As is known, power semiconductors can be manufactured on a large scale by means of so-called wafer substrates using known production methods by clean room technology or microsystem technology. To produce power semiconductors or semiconductor chips, generally speaking, wafers made of the material silicon (Si) or silicon carbide (SiC) with a diameter of, for example, 150 mm, 200 mm or 300 mm are processed in a plurality of individual steps.

[0003] The power semiconductors or chips processed on the wafer require insulators or so-called edge insulators at the edges in the region of the sawing edges provided for separation in order to prevent electrical flashovers. ). In addition, the insulator serves as a seal against grinding water when the wafer is thinned from behind. In addition, the insulator passivates the edge region of the chip and protects it from contamination or moisture during the service life of the chip. The material for the edge insulator is usually applied by spin coating and developed by an exposure process using UV light. The photolithographic coating and structuring process is carried out in the so-called BEOL (back end of line) in semiconductor production.

[0004] The disadvantage of the known method is that a number of process steps are required and only a portion of the applied material is ultimately required, which makes the process cost-intensive and resource-intensive. In addition, the edge insulator is applied over the entire wafer and therefore also in the case of semiconductor chips that have been found to be malfunctioning in the back-end process during subsequent wafer testing and that, due to the complex production, have eliminated a not insignificant portion of the chip on the wafer. In addition, depending on the product, different layer thicknesses for the insulator are required, for example 5 μm and 12 μm, for which separate facilities need to be provided in production, respectively, which include a spin coater, an image setter and a cleaning machine for the different layer thicknesses. Due to inaccuracies in orientation at the wafer edge, the process cannot be guided to the edge either, which can result in a loss of wafer area and thus fewer chips per wafer. Summary of the invention

[0005] The invention relates to a method for producing a plurality of semiconductor components, in particular power semiconductor components, from a wafer, the method comprising the following steps:

[0006] providing a wafer substrate,

[0007] Processing of structured wafer surfaces,

[0008] applying edge insulation on the wafer surface, and

[0009] The wafer is singulated into individual semiconductor components, wherein, according to the invention, an edge insulation is applied to the wafer surface as a printed electrical insulator by means of a digital printing technique.

[0010] Advantageous embodiments of the method according to the invention for producing a plurality of semiconductor components from a wafer are listed in the dependent claims.

[0011] Compared to the methods known from the prior art, the edge insulation according to the invention is designed as a printed electrical insulator, which results in not only a significant material and resource saving, but also in particular in minimizing chemical waste, the advantage of a simplified process flow. In this way, different layer shapes and / or layer thicknesses can be produced on one facility and can be selected individually for each incoming wafer. Changing chip sizes and layouts can be introduced and adapted quickly and uncomplicatedly using printing technology. In addition, complex and cost-intensive mask changes and phasing of new masks are omitted. In addition, the edge insulation can be processed or applied with constant precision over the entire wafer surface.

[0012] Preferably, the edge insulation is applied selectively in predefined areas of the wafer surface, in particular in the area of ​​a sawing edge of the wafer provided for separating individual semiconductor components or semiconductor chips. Preferably, the edge insulation is applied to the wafer surface according to a predefined layout. As a result, the edge insulation can be applied selectively and precisely with reduced material consumption compared to the prior art.

[0013] Preferably, the application of the edge insulation comprises the application of an organic or inorganic ink, which is then hardened. Preferably, the ink consists of a photosensitive material component, in particular a polymer mixture, which can be hardened by irradiation with UV light or a suitable energy source and / or heat source.

[0014] In this case, the ink is applied or coated in a manner known per se by means of a corresponding printing head which is arranged in a movable manner relative to the wafer surface or the working surface of the auxiliary wafer. In this case, the ink can be applied layer by layer from one or more nozzles of the printing head provided for this purpose, wherein each of the applied layers can be cured immediately or periodically.

[0015] In a preferred embodiment, the application of the edge insulation comprises the application of at least one layer with a layer thickness of between 5 and 30 μm. In order to achieve or apply an edge insulation layer with a greater layer thickness, repeated material application can be performed. In this case, the application of the edge insulation can in particular comprise the application of a plurality of layers, which are applied one above the other on the wafer surface, preferably with subsequent curing in each case.

[0016] Advantageously, after the edge insulation has been applied, the method comprises a leveling step in which a predefined and preferably uniform layer thickness of the edge insulation on the wafer surface is created or achieved. This can be achieved, for example, by means of a scraper. In particular, in this case, excess ink can also be removed or the surface of the applied layer or layers can be smoothed.

[0017] After the edge insulation has been applied, in an optional additional step, final curing can be carried out under UV light or a corresponding heat treatment, thereby ensuring complete curing and consolidation of the material of the edge insulation.

[0018] Preferably, the step of applying the edge insulation to the wafer surface is carried out before a backside thinning process of the wafer, in which the wafer is reduced from its original lens thickness to a component thickness desired or required for the subsequent use of the semiconductor component or chip. Depending on the specific requirements of the production process and the desired thickness of the wafer, this can be done, for example, by grinding, chemical mechanical polishing (CMP) or by etching.

[0019] Alternatively, the step of applying the edge insulation can be performed together with the application of a wafer carrier, a so-called carrier wafer, in particular a printed wafer carrier or printed carrier wafer. The wafer carrier serves to assist and protect the wafer during handling and further process steps. In this case, the printed wafer carrier can also be applied by means of digital printing technology.

[0020] In this case, the edge insulation is preferably first applied in a first process step and subsequently the printed wafer carrier is applied. Advantageously, the auxiliary layer or auxiliary material can be applied in areas in which the edge insulation is not applied or imprinted. The auxiliary layer or auxiliary material can be applied with a layer thickness that is equal to the layer thickness of the edge insulation and / or can be designed such that the surface of the auxiliary layer or auxiliary material lies in the plane of the surface with the edge insulation. In this case, the auxiliary layer can also be applied by means of digital printing technology.

[0021] Furthermore, the step of applying the edge insulation can alternatively be carried out after the back thinning process and the electrical wafer test, in which the functionality and quality of the wafer are checked before the wafer is further processed and cut or separated into individual semiconductor components or chips. Typically, the wafer test is carried out after the BEOL process, in which circuits and connections are produced on the wafer, and the wafer test consists of a series of electrical and functional tests in order to determine that the wafer is functioning properly and corresponds to predefined specifications. Preferably, the edge insulation is applied only, that is, only to semiconductor components that were tested in the wafer test as functioning properly or corresponding to predefined specifications. This can further significantly reduce the use of material.

[0022] The invention further relates to a semiconductor component, in particular a power semiconductor component, which is produced or can be produced according to the above method, wherein the semiconductor component has an edge insulation, which is formed by a printed electrical insulator. In particular, the edge insulation is applied by means of digital printing technology or an additive production method.

[0023] In order to avoid repetitions, reference is made here to the above-described embodiments with regard to the method according to the invention, which are likewise to be regarded as disclosed and claimable with regard to the device according to the invention.

[0024] Further advantages and details of the invention emerge from the following description of preferred embodiments of the invention and from the drawings, which are shown only schematically. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1a A plan view of the structured top side of a wafer having a plurality of wafer units for subsequent separation into semiconductor components is shown.

[0026] Figure 1b Show Figure 1a A detailed view of a wafer unit having multiple wafer units arranged side by side,

[0027] Figure 1c Show Figure 1bDetailed view of a wafer unit of a wafer or of a semiconductor component according to the invention with applied edge insulation before singulation,

[0028] Figure 2a - c shows a cross-sectional view of a wafer unit or a functional block of a wafer, in order to illustrate individual method steps of a preferred specific embodiment of the method according to the invention. DETAILED DESCRIPTION

[0029] Identical elements or elements having the same function are provided with the same reference symbols in the figures.

[0030] exist Figure 1a 1 shows a wafer 100 in a perspective top view, wherein a plurality of wafer units or functional blocks 102 a, b, c which later form semiconductor components or chips are arranged or structured on a top side 101 shown.

[0031] like Figure 1b and 1c As shown, an edge insulation 103 is applied or printed on the wafer top 101 , which separates the individual chips 102 a , 102 b , 102 c from one another and protects the individual chips from external influences. In particular, undesired electrical interactions or short circuits between the chips 102 a , 102 b , 102 c can be prevented.

[0032] In this case, edge insulation 103 is selectively applied or arranged by means of the method according to the invention in predefined areas of wafer top 101, which areas include in particular areas of sawing edges 106 of wafer 100 provided for separating the individual chips. Edge insulation 103 is formed by an electrical insulator printed by means of digital printing technology.

[0033] In this case, the edge insulation 103 can be applied to the wafer surface 101 before the backside thinning process of the wafer. Alternatively, the edge insulation 103 can be applied after the backside thinning process and in particular after the electronic wafer test. In this case, the selective application of the edge insulation 103 is preferably performed only for the following types of wafer units or chips 102a, 102b, 102c: the wafer units or chips have been tested in the wafer test to be functional or meet the predefined specifications.

[0034] Figure 2a -c shows a method step according to a further preferred specific embodiment of the method according to the invention, in which the edge insulation 107 is applied together with the wafer carrier 107 , in particular a printed wafer carrier.

[0035] like Figure 2aAs shown, first, a wafer substrate 108, for example, a wafer substrate composed of silicon (Si), silicon carbide (SiC) or gallium nitride (GaN), is provided as a basis for processing semiconductor components to be formed on the wafer. Then, in a manner known per se, desired or process-predetermined layers and structures 104 are formed on the wafer substrate surface 108a for the production of semiconductor components, such as transistors, diodes or integrated circuits.

[0036] like Figure 2b As shown, in the next step, edge insulation 103 is applied to surface 105 of processed or structured wafer 100. Preferably, edge insulation 103 is applied as an organic or inorganic ink only in predefined areas of the surface by means of a corresponding print head. In particular, edge insulation 103 is applied in the area of ​​sawing edges 106 of wafer 100 provided for separating individual semiconductor components or semiconductor chips. Edge insulation 103 is applied in particular in layers to the wafer surface, preferably with a layer thickness of between 5 and 30 μm, and is subsequently cured by irradiation with UV light or a suitable energy source and / or heat source. In order to achieve greater layer thicknesses, multiple layers can be applied one above the other and each of the multiple layers can be subsequently cured.

[0037] In order to achieve a uniform surface for the subsequent application of the printed wafer carrier 107, an auxiliary layer 109 is preferably applied to the wafer surface 10 in addition to the edge insulation 103. The auxiliary layer is applied in particular to those regions of the wafer to which the wafer carrier 107 is to be applied and to which the edge insulation 103 has not yet been applied. In this case, the auxiliary layer is preferably applied to the wafer surface 105 and the constructed semiconductor structure 104 in such a way that the surface 109a of the auxiliary layer lies in the plane of the surface 103a of the edge insulation 103. Preferably, the auxiliary layer 107 is also applied by means of digital printing technology.

[0038] like Figure 2c As shown, in a further step, a printed wafer carrier 107 is applied to the regions provided for this purpose of the surface of the edge insulation 103 and of the auxiliary layer 107. The wafer carrier 107 is likewise applied in a manner known per se by means of digital printing technology.

[0039] In a subsequent production step (not shown), wafer 100 is separated or singulated by separating semiconductor components 102 a , 102 b , 102 c at provided sawing edges 106 .

Claims

1. A method for producing a plurality of semiconductor components, in particular power semiconductor components, from a wafer (100), the method comprising the following steps: providing a wafer substrate (108), processing the structured wafer surface (105), applying an edge insulation (103) on the wafer surface (105), and separating the wafer (100) into individual semiconductor components (102a, 102b, 102c), It is characterized in that The edge insulation (103) is applied to the wafer surface (105) as a printed electrical insulator by means of digital printing technology.

2. The method according to claim 1, It is characterized in that The edge insulation (103) is selectively applied to a predefined region of the wafer (100) which is provided for a sawing edge (106) for separation.

3. The method according to claim 1 or 2, It is characterized in that The application of the edge insulation (103) comprises the application of an organic or inorganic ink and subsequent curing.

4. The method according to any one of claims 1 to 3, It is characterized in that The application of the edge insulation (103) comprises the application of at least one layer having a layer thickness of between 5 and 30 μm.

5. The method according to any one of the preceding claims, It is characterized in that The application of the edge insulation (103) comprises the application of a plurality of layers which are applied one above the other on the wafer surface (105), preferably with subsequent curing in each case.

6. The method according to any one of the preceding claims, It is characterized in that The method comprises a planarization step in which a uniform layer thickness of the edge insulation (103) on the wafer surface (105) is created.

7. The method according to any one of the preceding claims, It is characterized in that Prior to a backside thinning process of the wafer, an edge insulation (103) is applied on the wafer surface (105).

8. The method according to any one of claims 1 to 6, It is characterized in that After the backside thinning process and electrical wafer testing, the edge insulation (103) is applied on the wafer surface (105).

9. The method according to any one of claims 1 to 6, It is characterized in that The edge insulation (103) is applied to the wafer surface (105) together with the application of a wafer carrier (107), in particular together with the application of a printed wafer carrier.

10. A semiconductor component, in particular a semiconductor component produced according to the method as claimed in any one of the preceding claims, It is characterized in that The semiconductor component (102a, 102b, 102c) has an edge insulation (103) which is formed by a printed electrical insulator.

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