Carrier synchronization method for shared AC / DC bus parallel converter

Abstract

The invention discloses a carrier synchronization method for a parallel converter sharing an AC / DC bus, and the method comprises the steps: employing a layout of one main device, one standby device and multiple slave devices, enabling the main device to transmit a synchronization signal when the main device is normal, and enabling the standby device and the slave devices to receive the synchronization signal; arranging an optical fiber transmitter and an optical fiber receiver on each device; the carrier synchronization method of the multiple parallel converters comprises the following steps: in a normal mode, when carrier counting of an EPWM1 register in a main equipment DSP reaches 0, a synchronization signal is generated, and carriers in an EPWM2-EPWM6 register in the main equipment DSP receive the synchronization signal internally; the synchronizing signal is led to a GPIO pin through an Output X-BAR register in the DSP of the master device, then an electric signal is converted into an optical signal through an optical fiber transmitter in the master device, and the optical signal is sent to the standby device and the slave device.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and in particular relates to a one-master-one-standby-multiple-slave carrier synchronization method for a multi-parallel converter system sharing an AC / DC bus for an energy storage power station and a photovoltaic power station. Background Art

[0002] With the continuous development of new energy power generation technology, converters are increasingly widely used in the fields of wind power, photovoltaics and energy storage, and the requirements for converter performance, capacity, reliability, scalability, etc. are becoming higher and higher. The parallel connection technology of converters combines low-cost and standardized converter modules in parallel into large-capacity converters, which is easy to achieve the power electronics integrated modular design requirements of power conversion equipment and can be plug-and-play. However, in high-power parallel systems, converters share a bus on the DC side and are connected to the AC bus in parallel through inductors on the AC side. The switching frequency of the converter is low and the system bandwidth is narrow. The inductor has poor suppression effect on high-frequency harmonics, which may cause the high-frequency components of the converter output to be inconsistent, resulting in high-frequency circulating currents in the parallel system.

[0003] In a parallel system, the DC side of the converter shares the same DC bus, and the AC output shares the AC bus to connect to the load. When a voltage difference occurs between converters, the voltage difference will excite the inductance of the parallel branch, thereby generating a circulating current. Current literature generally divides circulating current into low-frequency circulating current and high-frequency circulating current. When the modulation waves between modules are inconsistent, the average voltage in one cycle of the output is inconsistent, resulting in low-frequency circulating current in the system; when the carrier waves between modules are inconsistent, the average voltage in one cycle of the output is consistent, and the asynchronous switching state of the power device will cause high-frequency circulating current. If the circulating current does not pass through the power grid and the load, it will increase the loss, cause output current distortion, and even damage the power device.

[0004] There are two main methods for suppressing circulating current: hardware circuit blocking and software algorithm suppression. The hardware blocking method electrically isolates the DC side or the AC side. Each converter uses an independent DC source on the DC side or adds a multi-winding transformer on the AC side. This method cuts off the circulation path of the circulating current and can completely eliminate the circulating current, but it increases the volume and cost of the system and is not conducive to system modularization and integration. The method of suppressing circulating current by software is low-cost and can be mainly divided into converter control strategy and PWM modulation strategy. Converter control strategy usually uses zero vector feedforward control strategy to suppress zero-sequence circulating current; PWM modulation strategy mainly includes zero-sequence current PI regulation SVPWM zero vector action time reasonable distribution of zero vector, non-zero vector replacement of zero vector strategy to suppress zero-sequence circulating current, low-frequency circulating current control based on PR control, and space vector modulation algorithm based on staggered carrier to suppress circulating current. The algorithm steps of the control strategy mentioned above are relatively complex, the control difficulty is high, and the carrier signal is not synchronized, so the suppression effect of high-frequency circulating current of parallel converters is not ideal. Summary of the invention

[0005] In view of the above problems in the prior art, the present invention provides a carrier synchronization control method for parallel converters. To solve the high-frequency circulating current problem caused by the asynchronous carrier of the converter parallel connection, a carrier synchronization algorithm with one master, one backup and multiple slaves is adopted, and carrier synchronization is achieved by using an optical fiber transmitter and a receiver. The transmission quality is good and the speed is fast, and the high-frequency circulating current caused by the asynchronous instantaneous power device switch is avoided, the system loss is reduced, and the efficiency and stability of the system are improved. The technical solution is as follows:

[0006] A carrier synchronization method for a shared AC / DC bus parallel converter adopts a one-master-one-standby-multiple-slave device layout. When the master device is normal, the master device sends a synchronization signal, and the standby device and the slave device receive the synchronization signal. When the master device fails, the standby device sends a synchronization signal, and the master device and the slave device receive the synchronization signal, thereby realizing carrier synchronization between all parallel converters. An optical fiber transmitter and an optical fiber receiver are arranged on each device. The carrier synchronization method for multiple parallel converters is as follows: in a normal mode, when the carrier count of the EPWM1 ​​register in the DSP of the master device reaches 0, a synchronization signal is generated, and the carrier in the EPWM2-EPWM6 register in the DSP of the master device receives the synchronization signal internally; the synchronization signal is led to a GPIO pin through an Output X-BAR register in the DSP of the master device, and then the electrical signal is converted into an optical signal through the optical fiber transmitter in the master device, and sent to the standby device and the slave device; the optical fiber receivers on the standby device and the slave device convert the optical signal into an electrical signal and input it into the GPIO pin of their own DSP, and then the optical fiber receivers on the standby device and the slave device convert the optical signal into an electrical signal and input it into the GPIO pin of their own DSP, and then the optical fiber receivers on the standby device and the slave device convert the optical signal into an electrical signal and input it into the GPIO pin of their own DSP, and then the optical fiber receivers on the standby device and the slave device transmit the optical signal to the GPIO pin of their own DSP, and then transmit the optical signal to the standby device and the slave device through the Input The X-BAR register is input into the EPWM1-EPWM6 register; after receiving this synchronization signal, the carrier counters of other PWM waves in the master device DSP, the carriers of each PWM wave in the standby device DSP, and the carriers of each PWM wave in the slave device DSP start counting upward from 0 to achieve carrier phase synchronization of each converter.

[0007] Furthermore, when the master device fails, the DSP of the backup device will detect the period value of the master device synchronization signal. If it is detected that the actual period value is not within the set value range, the pulse detection counter in the DSP program of the backup device will count once in each control cycle. If the continuous cumulative count reaches the preset number limit, a synchronization signal is generated when the carrier count of the EPWM1 ​​register in the DSP of the backup device reaches 0, and the carrier in the EPWM2-EPWM6 register of the DSP in the backup device can receive the synchronization signal internally; this synchronization signal is led to the GPIO pin through the Output X-BAR register in the DSP of the backup device, and then the optical fiber transmitter in the backup device converts the electrical signal into an optical signal and sends it to the master device and the slave device; the optical fiber receiver on the master device and the slave device converts the optical signal into an electrical signal and inputs it into the GPIO pin of the DSP, and then inputs it into the EPWM1-EPWM6 register through the InputX-BAR register.

[0008] Furthermore, the DSP used by each device is TMS320F28379D.

[0009] The beneficial effects of the present invention are as follows:

[0010] ① Realize carrier synchronization in multi-converter systems to reduce high-frequency circulating currents and system losses. By combining the optical fiber carrier synchronization circuit and the carrier synchronization algorithm, carrier synchronization can be effectively achieved in multi-parallel converter systems to avoid high-frequency circulating current problems caused by asynchronous switching of instantaneous power devices in each converter. This design not only significantly reduces the high-frequency circulating current in the system and the energy loss caused by it, but also improves the overall efficiency and operational stability of the system.

[0011] ② A carrier synchronization algorithm with a master-slave switching function improves system reliability. The carrier synchronization algorithm with one master, one backup and multiple slaves proposed in the present invention, when the master device is working normally, the master device sends a carrier synchronization signal, and the backup device and the slave device receive the synchronization signal. When the master device fails, the backup device can take over and send the synchronization signal in time to ensure the continuity and reliability of the system synchronization signal. This design improves the system's ability to respond to key equipment failures and enhances the system's operational reliability.

[0012] ③ Use optical fiber synchronization technology to improve signal transmission quality and anti-interference ability. Optical fiber transmission has the advantages of fast propagation speed, strong anti-electromagnetic interference ability, long transmission distance and high transmission quality, making the transmission of carrier synchronization signals more stable and reliable, further improving the system's anti-interference ability and overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Carrier synchronization flow chart

[0014] Figure 2 Carrier synchronization principle diagram

[0015] Figure 3 Synchronous signal detection flow chart

[0016] Figure 4 Synchronous diagram for time base counting

[0017] Figure 5 Simplified model for EPWM registers DETAILED DESCRIPTION

[0018] Carrier synchronization flow chart is as follows Figure 1 As shown, it is divided into three types of devices: master, standby and slave. When the master device is normal, the master device sends a synchronization signal, and the standby device and the slave device receive the synchronization signal. When the master device fails, the standby device sends a synchronization signal, and the master device and the slave device receive the synchronization signal. The carrier synchronization principle diagram is shown in Figure 2 As shown in the figure, the main device fault detection flow chart is as follows Figure 3 The present invention uses DSP as a carrier synchronization signal generator, and is mainly implemented by utilizing the EPWM register in the DSP. Figure 4 This is the internal structure diagram of the EPWM module time base counter of DSP TMS320F28379D. The carrier is generated by the time base counter count. This model DSP has a total of 12 EPWM modules. Each EPWM module can be configured to use or ignore the synchronization input signal. The synchronization input includes external synchronization signals (EXTSYNCIN1, EXTSYNCIN2) and internal synchronization signals. The internal synchronization signal (EPWMxSYNCOUT) can be generated by EPWM1, EPWM4, EPWM7, and EPWM10. EPWM simplified model Figure 5 As shown, Syncln is the synchronization signal input, EN can choose to receive or shield the input synchronization signal, Phase reg is to set the initial phase value, SyncOut is the synchronization signal output, and there are four output modes as follows:

[0019] 1. SyncOut connected to SyncIn---Output received synchronous input signal

[0020] 2. SyncOut connected to CTR = 0 --- Output is generated when the carrier count reaches zero

[0021] 3. SyncOut connected to CTR = CMPB --- Output is generated when the carrier count and CMPB register are equal

[0022] 4. SyncOut connected to X---No synchronous output signal is generated

[0023] The specific scheme for realizing carrier synchronization of multiple parallel converters is as follows: to realize carrier synchronization of multiple parallel converters, it is necessary to synchronize the carriers of the DSPs in each converter control module, thereby converting the problem into carrier synchronization of multiple DSPs. In normal mode, one DSP is used as the master device to generate synchronization signals, one DSP is used as the backup device to receive synchronization signals, and the other DSPs are used as slave devices to receive synchronization signals. The EN of the EPWM1-EPWM6 registers of all device DSPs selects to receive synchronization signals, the initial value of Phase reg is set to 0, the SyncOut synchronization signal output of the EPWM1 ​​register of the master and backup DSPs selects mode 2, and the SyncOut synchronization signal output of the EPWM2-EPWM6 registers of the master and backup DSPs and the EPWM1-EPWM6 registers of the slave DSPs selects mode 1. In this way, in normal mode, the EPWM1 ​​register of the master DSP is used as the source of the synchronization signal, and the EPWM registers of all other DSPs are used as the receiving source of the synchronization signal. After the carrier synchronization starts, a synchronization signal is generated when the carrier count of the EPWM1 ​​register in the master device DSP reaches 0, and the carrier in the EPWM2-EPWM6 register of the master device DSP can receive the synchronization signal internally. This synchronization signal is led to the GPIO pin through the Output X-BAR register in the master device DSP, and then the optical fiber transmitter in the master device converts the electrical signal into an optical signal and sends it to the backup device and the slave device. The optical fiber receiver on the backup device and the slave device converts the optical signal into an electrical signal and inputs it to the GPIO pin of the DSP, and then inputs it to the EPWM1-EPWM6 register of its own DSP through the Input X-BAR register.

[0024] In the fault mode, the EPWM1 ​​register of the standby device DSP is used as the source of the synchronization signal, and the EPWM registers of all other device DSPs are used as the receiving sources of the synchronization signal. When the master device fails, the standby device DSP will detect the period value of the master device synchronization signal. If the actual period value is not within the set value range, the pulse detection counter in the standby device DSP program will count once in each control cycle. In order to prevent signal interference, if the continuous cumulative count reaches five times, a synchronization signal is generated when the carrier count of the EPWM1 ​​register in the standby device DSP reaches 0. The carrier in the EPWM2-EPWM6 register of the DSP in the standby device can receive the synchronization signal internally. This synchronization signal is led to the GPIO pin through the Output X-BAR register in the standby device DSP, and then the optical fiber transmitter in the standby device converts the electrical signal into an optical signal and sends it to the master device and the slave device. The optical fiber receiver on the master device and the slave device converts the optical signal into an electrical signal and inputs it to the GPIO pin of its own DSP, and then inputs it into the EPWM1-EPWM6 register through the Input X-BAR register.

Claims

1. A carrier synchronization method for a shared AC / DC bus parallel converter, which adopts a one-master-one-standby-multiple-slave device layout, wherein when the master device is normal, the master device sends a synchronization signal, and the standby device and the slave device receive the synchronization signal; when the master device fails, the standby device sends a synchronization signal, and the master device and the slave device receive the synchronization signal, thereby realizing carrier synchronization between all parallel converters; an optical fiber transmitter and an optical fiber receiver are arranged on each device; the carrier synchronization method for multiple parallel converters is as follows: in normal mode, when the carrier count of the EPWM1 ​​register in the DSP of the master device reaches 0, a synchronization signal is generated, and the carrier in the EPWM2-EPWM6 register in the DSP of the master device receives the synchronization signal internally; the synchronization signal is led to the GPIO pin through the Output X-BAR register in the DSP of the master device, and then the electrical signal is converted into an optical signal through the optical fiber transmitter in the master device, and sent to the standby device and the slave device; the optical fiber receivers on the standby device and the slave device convert the optical signal into an electrical signal and input it into the GPIO pin of their own DSP, and then through the Input The X-BAR register is input into the EPWM1-EPWM6 register; after receiving this synchronization signal, the carrier counters of other PWM waves in the master device DSP, the carriers of each PWM wave in the standby device DSP, and the carriers of each PWM wave in the slave device DSP start counting upward from 0 to achieve carrier phase synchronization of each converter.

2. The carrier synchronization method for parallel converters with shared AC / DC bus according to claim 1, characterized in that: When the master device fails, the standby device DSP will detect the period value of the master device synchronization signal. If it is detected that the actual period value is not within the set value range, the pulse detection counter in the standby device DSP program will count once in each control cycle. If the continuous cumulative count reaches the preset number limit, a synchronization signal is generated when the carrier count of the EPWM1 ​​register in the standby device DSP reaches 0. The carrier in the EPWM2-EPWM6 register of the DSP in the standby device can receive the synchronization signal internally; this synchronization signal is led to the GPIO pin through the Output X-BAR register in the standby device DSP, and then the optical fiber transmitter in the standby device converts the electrical signal into an optical signal and sends it to the master device and the slave device; the optical fiber receiver on the master device and the slave device converts the optical signal into an electrical signal and inputs it to the GPIO pin of the DSP, and then inputs it into the EPWM1-EPWM6 register through the Input X-BAR register.

3. The carrier synchronization method for parallel converters with shared AC / DC bus according to claim 1, characterized in that: The DSP used in each device is TMS320F28379D.

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