CAN transceiver

Abstract

The invention discloses a CAN (Controller Area Network) transceiver. According to the CAN transceiver, a delay driving circuit is provided with an input end for receiving and sending data signals and providing K high-side control signals and K low-side control signals, and a high-side control circuit receives the K high-side control signals and outputs the high-side signals; the low-side control circuit receives K low-side control signals and outputs low-side signals; the sending data signal is increased to a first proportion threshold value at the first time, the difference between the high-side signal and the low-side signal is reduced to a first threshold value at the second time, and the second time is delayed by N stepping delays compared with the first time; the sending data signal is reduced to a second proportion threshold value at third time, the difference between the high-side signal and the low-side signal is increased to a second threshold value at fourth time, the fourth time is delayed by N stepping delays compared with the third time, N and K are positive integers, and N is larger than or equal to 2 and smaller than K. According to the invention, the bit width change time is reduced through the delay driving circuit, and the reliability and speed of CAN bus data transmission are improved.

Description

Technical Field

[0001] The present application relates to the technical field of CAN transceivers, and in particular to a CAN transceiver. Background Art

[0002] With the development of automotive electronics, the amount of data that the vehicle body needs to process is increasing. Therefore, the CAN bus widely used in automotive communications also needs to have a faster bus transmission speed. However, the faster the bus transmission speed, the higher the timing requirements for the CAN transceiver. In CAN communication, the CAN transceiver usually receives the transmit data signal TX from the transmit data port TXD, and changes the differential signal between the high-side signal port and the low-side signal port of the CAN transceiver according to the logical potential of the transmit data signal, and outputs an output signal in a dominant or recessive position. However, in the process of changing the logical potential of the transmit data signal, when the transmit data signal switches from a logic low potential to a logic high potential, the transmit data signal is confirmed to be in a logic high potential only when the real-time value is higher than a certain proportion threshold. Similarly, when switching from a logic high potential to a logic low potential, the transmit data signal is confirmed to be in a logic low potential only when the real-time value is lower than a certain proportion threshold, such as Figure 1 As shown, the time difference between the logic high potential and the logic low potential of the transmitted data signal is called the bit width time tbit(TXD). When the transmitted data signal is confirmed to be a logic high potential, the differential voltage begins to decrease. When the differential voltage decreases to the first threshold, the CAN transceiver is in a recessive position. When the transmitted data signal is confirmed to be a logic low potential, the differential voltage begins to increase. When the differential voltage increases to the second threshold, the CAN transceiver is in a dominant position. The time difference between the recessive position and the dominant position of the CAN transceiver is called the bus threshold time tbit(BUS). Since the time for the differential voltage to decrease from the highest value to the first threshold is usually longer than the time for the differential voltage to increase from the lowest value to the second threshold, a time difference will occur between the bit width time tbit(TXD) and the bus threshold time tbit(BUS), namely the bit width change time Δtbit(BUS). High-speed CAN bus data transmission needs to match a smaller bit width change time. If the bit width change time is too long, it may cause signal distortion, thereby affecting the correct reception of data. Summary of the invention

[0003] The present application provides a CAN transceiver, which aims to solve the problem in the prior art that the CAN bus bit width time is too large, resulting in signal distortion and affecting the correct reception of data.

[0004] According to the first aspect of the present application, the present application provides a CAN transceiver, including: a sending data port, receiving a sending data signal; a high-side bus port, outputting a high-side signal; a low-side bus port, outputting a low-side signal; a delay drive circuit, having an input end to receive a sending data signal, having K high-side output ends to provide K high-side control signals, and K low-side output ends to provide K low-side control signals, the delay drive circuit generates K high-side control signals and K low-side control signals according to the sending data signal; a high-side control circuit, having K input ends to receive K high-side control signals, having an output end coupled to the high-side bus port and outputting a high-side signal, the high-side control circuit generates according to the K high-side control signals A high-side signal; a low-side control circuit having K input terminals receiving K low-side control signals, having an output terminal coupled to a low-side bus port and outputting a low-side signal, wherein the low-side control circuit generates a low-side signal according to the K low-side control signals; the sending data signal increases to a first proportional threshold at a first time, and the difference between the high-side signal and the low-side signal decreases to a first threshold at a second time, wherein the second time is delayed by N step delays compared to the first time; the sending data signal decreases to a second proportional threshold at a third time, and the difference between the high-side signal and the low-side signal increases to a second threshold at a fourth time, wherein the fourth time is delayed by N step delays compared to the third time, wherein N and K are positive integers, and 2≤N<K.

[0005] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0006] The CAN transceiver provided in the present application sets a delay driving circuit to delay the time of the difference between the high-side signal and the low-side signal at the first threshold by N step delays compared with the time of the first proportional threshold when the data signal is sent, and delays the time of the difference between the high-side signal and the low-side signal at the second threshold by N step delays compared with the time of the second proportional threshold when the data signal is sent, so that the time difference between the bit width time tbit(TXD) and the bus threshold time tbit(BUS) (i.e., the bit width change time) is reduced to 0, thereby improving the reliability and fidelity of CAN bus data transmission and being able to match a higher CAN bus signal transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1A structural schematic diagram of a CAN bus system according to an embodiment of the present invention is given;

[0009] Figure 2 The signal waveform diagram of the existing CAN transceiver when the explicit and implicit bits are switched is given;

[0010] Figure 3 A schematic structural diagram of a CAN transceiver according to an embodiment of the present invention is given;

[0011] Figure 4 Given Figure 3 The waveform diagram of each signal in the CAN transceiver is shown. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0013] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0014] It should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0015] Figure 1A structural schematic diagram of a CAN bus system according to an embodiment of the present invention is given. The CAN bus system includes a CAN controller and a CAN transceiver, and the CAN transceiver includes a transmit data port TXD and a receive data port RXD. The CAN transceiver receives the transmit data signal TX generated by the CAN controller and converts it into a high-side signal VH and a low-side signal VL that conform to the CAN bus signal specification so as to be transmitted on the CAN bus. After receiving the high-side signal VH and the low-side signal VL, the CAN transceiver demodulates, amplifies and converts them into a receive data signal RX, and outputs the receive data signal RX from its receive data port RXD to the CAN controller. In CAN bus communication, different data bits (dominant or recessive) are represented by changing the level difference between the high-side signal VH and the low-side signal VL, thereby realizing data transmission and reception. The switching between the dominant bit and the recessive bit determines the differential voltage on the CAN bus. In the dominant bit, the differential voltage Vdiff between the high-side signal VH and the low-side signal VL is large; in the recessive bit, the differential voltage Vdiff between the high-side signal VH and the low-side signal VL is small or even close to 0.

[0016] Figure 2 The signal waveform diagram of the existing CAN transceiver when switching between dominant and recessive positions is given. In the CAN bus system, the typical dominant position differential voltage Vdiff is 2.2V, which can ensure the noise tolerance and data reliability during the communication process. In the process of the differential voltage Vdiff changing from dominant position to recessive position, when the differential voltage Vdiff is less than the first threshold Vth1, it is determined that the CAN transceiver is in the recessive position, and in the process of changing from recessive position to dominant position, when the differential voltage Vdiff is greater than the second threshold Vth2, it is determined that the CAN transceiver is in the dominant position, such as Figure 2 As shown, the time difference between the first threshold Vth1 and the second threshold Vth2 is the bus threshold time tbit(BUS), that is, the transition period from when the CAN transceiver detects that the voltage is less than the first threshold Vth1 to when the voltage is not greater than the second threshold Vth2. In order to prevent interference from noise and interference, the stable time needs to be maintained within this range. Similarly, for the transmit data signal TX received by the CAN transceiver, when it switches from a logic low level to a logic high level, when the value of TX reaches the first proportional threshold value A1 of the logic high level, the transmit data signal TX is determined to be a logic high level, and when it switches from a logic high level to a logic low level, when the value of TX reaches the second proportional threshold value A2 of the logic high level, the transmit data signal TX is determined to be a logic low level. The time difference between the first proportional threshold A1 and the second proportional threshold A2 is the bit width time tbit(TXD). The bus threshold time tbit(BUS) minus tbit(TXD) is the bit width change time Δtbit(BUS) of the bus BUS, and the calculation formula is:

[0017] Δtbit(BUS)=tbit(BUS)-tbit(TXD)

[0018] The bit width change time is an important parameter of the CAN bus system, which directly affects the reliability and speed of bus data transmission. The lower the bit width change time (i.e., the shorter the bit time), the higher the communication rate and better real-time performance. In the prior art, the delay of the data signal TX from dominant to recessive is consistent with the delay from recessive to dominant, and the first proportional threshold A1+the second proportional threshold A2 is 100%. However, since the delay of the differential voltage Vdiff from dominant to recessive is greater than the delay from recessive to dominant, the first threshold Vth1+the second threshold Vth2 is less than the dominant value of the differential voltage, which results in the bit width change time being too high.

[0019] Figure 3 A schematic diagram of the structure of a CAN transceiver according to an embodiment of the present invention is given. The CAN transceiver comprises a transmit data port TXD, a high-side bus port CANH, a low-side bus port CANL, a delay driving circuit 10 and a low-side control circuit 30.

[0020] The transmission data port TXD receives the transmission data signal TX, the high-side bus port CANH outputs the high-side signal VH, and the low-side bus port CANL outputs the low-side signal VL. The delay driving circuit 10 has an input terminal for receiving the transmission data signal TX, K high-side output terminals for providing K high-side control signals VCH, and K low-side output terminals for providing K low-side control signals VCL. The delay driving circuit 10 generates K high-side control signals VCH and K low-side control signals VCL according to the transmission data signal TX. The high-side control circuit 20 has K input terminals for receiving the K high-side control signals VCH, and an output terminal coupled to the high-side bus port CANH and outputting the high-side signal VH. The high-side control circuit 20 generates the high-side signal VH according to the K high-side control signals VCH. The low-side control circuit 30 has K input terminals for receiving K low-side control signals VCL, and has an output terminal coupled to the low-side bus port CANL and outputting a low-side signal VL. The low-side control circuit 30 generates a low-side signal VL according to the K low-side control signals VCL.

[0021] exist Figure 3In the illustrated embodiment, the delay driving circuit 10 includes a delay circuit 11, a logic circuit 12 and a driving circuit 13. The delay circuit 11 has an input terminal for receiving a transmission data signal TX, and an output terminal for providing a delay signal. The delay circuit 11 generates the delay signal according to the transmission data signal TX. The logic circuit 12 has a first input terminal for receiving the delay signal, a second input terminal for receiving the transmission data signal TX, and an output terminal for providing a logic signal. The logic circuit 12 generates the logic signal by performing a logic operation based on the delay signal and the transmission data signal TX. The driving circuit 13 has an input terminal for receiving a logic signal, K high-side output terminals for providing K high-side control signals VCH, and K low-side output terminals for providing K low-side control signals VCL. The driving circuit 13 generates K high-side control signals VCH and K low-side control signals VCL according to the logic signal.

[0022] exist Figure 3 In the illustrated embodiment, the delay circuit 11 includes NM series-connected step delay circuits 11 , and the output signal of the next-stage step delay circuit 11 is separated from the output signal of the previous-stage step delay circuit 11 by a step delay. The input end of the first-stage step delay circuit B1 receives the transmission data signal TX, and the input end of the second-stage step delay circuit B2 is coupled to the output end of the first-stage step delay circuit B1, and receives the output signal of the first-stage step delay circuit B1. The output signal of the first-stage step delay circuit B1 is separated from the input signal of the first-stage step delay circuit B1 (i.e., the transmission data signal TX) by a step delay. Similarly, the output signal of the second-stage step delay circuit B2 is separated from the input signal of the second-stage step delay circuit B2 (i.e., the output signal of the first-stage step delay circuit B1) by a step delay, and is separated from the input signal of the first-stage step delay circuit B1 by a step delay. By analogy, the output signal (i.e., the delay signal) of the NMth step delay circuit 11 is separated from the transmission data signal TX by NM step delays. Exemplarily, the step delay circuit 11 may include a buffer.

[0023] exist Figure 3 In the illustrated embodiment, the logic circuit 12 includes a logic OR circuit having a first input terminal for receiving the delay signal, a second input terminal for receiving the transmit data signal TX, and an output terminal for providing the logic signal. The logic OR circuit performs an OR operation on the delay signal and the transmit data signal TX to generate the logic signal.

[0024] exist Figure 3In the embodiment shown, the driving circuit 13 includes K serially coupled stepping driving circuits 13, and the K serially coupled stepping driving circuits 13 provide corresponding K high-side control signals VCH and K low-side control signals VCL, including the first high-side control signal VCH1 to the Kth high-side control signal VCHK, and the first low-side control signal VCL1 to the Kth low-side control signal VCLK. The first stepping driving circuit 13 has an input terminal, a high-side output terminal and a low-side output terminal, wherein the input terminal receives the logic signal, the high-side output terminal provides the first high-side control signal VCH1, and the low-side output terminal provides the first low-side control signal VCL1, and the first stepping driving circuit 13 generates the first high-side control signal VCH1 and the first low-side control signal VCL1 according to the logic signal, wherein the first high-side control signal VCH1 is inverted with the first low-side control signal VCL1. The Kth stepper driving circuit 13 has an input end, a high-side output end and a low-side output end, wherein the input end is coupled to the high-side output end of the K-1th stepper driving circuit 13 to receive the K-1th high-side control signal VCHK-1, the high-side output end provides the Kth high-side control signal VCHK, and the low-side output end provides the Kth low-side control signal VCLK. The Kth stepper driving circuit 13 generates the Kth high-side control signal VCHK and the Kth low-side control signal VCLK according to the K-1th high-side control signal VCHK-1, wherein the Kth high-side control signal VCHK is delayed by one step delay compared to the K-1th high-side control signal VCHK-1.

[0025] In some embodiments, the stepper drive circuit 13 includes a first inverter and a second inverter, the first inverter having an input terminal and an output terminal, wherein the input terminal receives a logic signal or a high-side control signal VCH provided by the previous stepper drive circuit 13, and the output terminal provides a low-side control signal VCL, and the first inverter generates a low-side control signal VCL inverted therefrom according to the logic signal or the high-side control signal VCH provided by the previous stepper drive circuit 13. The second inverter has an input terminal and an output terminal, wherein the input terminal receives the low-side control signal VCL, and the output terminal provides the high-side control signal VCH, and the second inverter generates a high-side control signal VCH inverted therefrom according to the low-side control signal VCL.

[0026] exist Figure 3In the illustrated embodiment, the high-side control circuit 20 includes K P-type switch tubes MP1 to MPK. For the switch tubes MP1 to MPK, they all have a first end coupled to the power supply voltage, a third end coupled to the high-side bus port CANH, and a second end receiving a high-side control signal VCH. Each switch tube receives a corresponding high-side control signal VCH. The low-side control circuit 30 includes K N-type switch tubes MN1 to MNK. For the switch tubes MN1 to MNK, they all have a first end coupled to the low-side bus port CANL, a third end coupled to the reference ground, and a second end receiving a low-side control signal VCL. Each switch tube receives a corresponding low-side control signal VCL.

[0027] Figure 4 Given Figure 3 The waveform diagram of each signal in the CAN transceiver is shown in Figure 1. Figure 3 The CAN transceiver structure shown is Figure 4 The waveforms of the signals in the figure are used to illustrate the above. Figure 4 In the illustrated embodiment, the first state is a logic low state, and the second state is a logic high state.

[0028] At the first time t1, the data transmission signal TX increases to the first proportional threshold value A1, the data transmission signal TX is at a logic high level, and the logic signal provided by the logic circuit 12 is switched from the first state to the second state. For example, the first high-side control signal VCH is switched from the first state to the second state. After a step delay, the second high-side control signal VCH is switched from the first state to the second state. Since each high-side control signal VCH is coupled to the second end of a P-type switch tube in the high-side control circuit 20, the P-type switches in the high-side control circuit 20 are turned off one by one, and the high-side control circuit 20 is switched from the power supply voltage to the second state. The high-side step impedance RH between the high-side bus port CANH gradually increases. Similarly, when the logic signal switches from the first state to the second state, the first low-side control signal VCL switches from the second state to the first state. After a step delay, the second low-side control signal VCL switches from the second state to the first state. Since each low-side control signal VCL is coupled to the second end of an N-type switch tube in the low-side control circuit 30, the N-type switches in the low-side control circuit 30 are turned off one by one, and the low-side step impedance RL from the power supply voltage to the high-side bus port CANH in the low-side control circuit 30 gradually increases. Due to the increase of the high-side step impedance RH and the low-side step impedance RL, the differential voltage Vdiff between the high-side bus port CANH and the low-side bus port CANL gradually decreases.

[0029] At the second time t2, after N step delays, the differential voltage Vdiff decreases to the first threshold Vth1 at the second time t2, and the CAN transceiver switches from a dominant bit to a recessive bit.

[0030] Between the second time t2 and the third time t3, after K-1 step delays, the K high-side control signals VCH are all switched to the second state, the K low-side control signals VCL are all switched to the first state, the high-side step impedance RH and the low-side step impedance RL reach the maximum, and the differential voltage Vdiff drops to the minimum. After the differential voltage Vdiff drops to the minimum for a period of time, the transmission data signal TX begins to decrease.

[0031] At the third time t3 , the transmission data signal TX decreases to the second proportional threshold value A2 , and the transmission data signal TX is at a logic low level.

[0032] Between the fifth time t5 and the third time t3, after NM step delays of the delay circuit 11, the logic signal output by the logic circuit 12 switches from the second state to the first state at the fifth time t5, and the first high-side control signal VCH switches from the second state to the first state. After a step delay, the second high-side control signal VCH switches from the second state to the first state. Similarly, the first low-side control signal VCL switches from the first state to the second state. After a step delay, the second low-side control signal VCL switches from the first state to the second state, and so on.

[0033] At the fourth time t4, after M step delays, the differential voltage Vdiff decreases to the second threshold Vth2 at the second time t2, and the CAN transceiver switches from a recessive position to a dominant position. After K-1 step delays, the K high-side control signals VCH are all switched to the first state; when the logic signal switches from the second state to the first state, after K-1 step delays, the K low-side control signals VCL are all switched to the second state.

[0034] exist Figure 3In the illustrated embodiment, the difference between the high-side signal VH and the low-side signal VL decreases to the first threshold Vth1 at the second time t2, wherein the second time t2 is delayed by N step delays compared to the first time t1; the transmit data signal TX decreases to the second proportional threshold A2 at the third time t3, and the difference between the high-side signal VH and the low-side signal VL increases to the second threshold Vth2 at the fourth time t4, wherein the fourth time t4 is delayed by N step delays compared to the third time t3, wherein N and K are positive integers, and 2≤N<K. The logic signal switches from the second state to the first state at the fifth time t5, wherein the fifth time t5 is advanced by M step delays compared to the fourth time t4, and the fifth time t5 is delayed by NM step delays compared to the third time t3, wherein M is a positive integer, and 2≤M<N.

[0035] In some embodiments, the first ratio threshold value A1 is 70%, the second ratio threshold value A2 is 30%, the first threshold Vth1 is 500 mV, and the second threshold Vth2 is 900 mV.

[0036] In some embodiments, when the K high-side control signals VCH are all switched to the second state, the difference between the high-side signal VH and the low-side signal VL is 0V, and when the K high-side control signals VCH are all switched to the first state, the difference between the high-side signal VH and the low-side signal VL is 2.2V.

[0037] The present invention delays the transmission of the time when the sending data signal TXTX changes to a logic low level at the falling edge through the delay driving circuit 10, so that the time from the time when the sending data signal TX changes to a logic high level at the rising edge to the time when the CAN transceiver outputs a recessive state is equal to the time when the sending data signal TX changes to a logic low level at the falling edge to the time when the CAN transceiver outputs a dominant state, both of which are N step delays, thereby making the bus threshold time tbit(BUS) and the bit width time tbit(TXD), and then making the bit width change time Δtbit(BUS)=0, which greatly improves the reliability and speed of CAN bus data transmission.

[0038] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A CAN transceiver, characterized in that: include: Sending data port, receiving sending data signal; High-side bus port, outputs high-side signal; Low-side bus port, outputs low-side signal; A delay driving circuit, having an input end for receiving a transmission data signal, having K high-side output ends for providing K high-side control signals, and K low-side output ends for providing K low-side control signals, wherein the delay driving circuit generates K high-side control signals and K low-side control signals according to the transmission data signal; A high-side control circuit has K input terminals for receiving K high-side control signals, and an output terminal coupled to the high-side bus port and outputting the high-side signal, wherein the high-side control circuit generates a high-side signal according to the K high-side control signals; A low-side control circuit has K input terminals for receiving K low-side control signals, and has an output terminal coupled to the low-side bus port and outputting the low-side signal, wherein the low-side control circuit generates a low-side signal according to the K low-side control signals; The transmitted data signal increases to a first proportional threshold at a first time, and the difference between the high-side signal and the low-side signal decreases to a first threshold at a second time, wherein the second time is delayed by N step delays compared to the first time; the transmitted data signal decreases to a second proportional threshold at a third time, and the difference between the high-side signal and the low-side signal increases to a second threshold at a fourth time, wherein the fourth time is delayed by N step delays compared to the third time, wherein N and K are positive integers, and 2≤N<K.

2. The CAN transceiver according to claim 1, characterized in that: The first ratio threshold is 70%, the second ratio threshold is 30%, the first threshold is 500 mV, and the second threshold is 900 mV.

3. The CAN transceiver according to claim 1, characterized in that: The time-delay driving circuit comprises: A delay circuit, having an input end for receiving a transmission data signal and an output end for providing a delay signal, wherein the delay circuit generates the delay signal according to the transmission data signal; A logic circuit having a first input terminal for receiving the delay signal, a second input terminal for receiving the transmission data signal, and an output terminal for providing a logic signal, wherein the logic circuit generates the logic signal by performing a logic operation based on the delay signal and the transmission data signal; The driving circuit has an input terminal for receiving a logic signal, K high-side output terminals for providing K high-side control signals, and K low-side output terminals for providing K low-side control signals. The driving circuit generates K high-side control signals and K low-side control signals according to the logic signal.

4. The CAN transceiver according to claim 3, characterized in that: When the transmitted data signal increases to a first proportional threshold at a first time, the logic signal switches from the first state to the second state; when the transmitted data signal decreases to a second proportional threshold at a third time, the logic signal maintains the second state; the logic signal switches from the second state to the first state at a fifth time; the fifth time is advanced by M step delays compared to the fourth time; and the fifth time is delayed by NM step delays compared to the third time, where M is a positive integer and 2≤M<N.

5. The CAN transceiver according to claim 3, characterized in that: The delay circuit includes NM series-connected step delay circuits, and the output signal of the next-stage step delay circuit is separated from the output signal of the previous-stage step delay circuit by a step delay.

6. The CAN transceiver according to claim 3, characterized in that: The logic circuit includes a logic OR circuit having a first input terminal for receiving the delay signal, a second input terminal for receiving the transmission data signal, and an output terminal for providing the logic signal. The logic OR circuit performs an OR operation on the delay signal and the transmission data signal to generate the logic signal.

7. The CAN transceiver according to claim 3, characterized in that: The driving circuit comprises K stepping driving circuits coupled in series, The first stepper drive circuit has an input terminal, a high-side output terminal and a low-side output terminal, wherein the input terminal receives the logic signal, the high-side output terminal provides a first high-side control signal, and the low-side output terminal provides a first low-side control signal, and the first stepper drive circuit generates a first high-side control signal and a first low-side control signal according to the logic signal, wherein the first high-side control signal is inverted with the first low-side control signal; The Kth stepper drive circuit has an input end, a high-side output end and a low-side output end, wherein the input end is coupled to the high-side output end of the K-1th stepper drive circuit to receive the K-1th high-side control signal, the high-side output end provides the Kth high-side control signal, and the low-side output end provides the Kth low-side control signal. The Kth stepper drive circuit generates the Kth high-side control signal and the Kth low-side control signal according to the K-1th high-side control signal, wherein the Kth high-side control signal is delayed by a step delay compared to the K-1th control signal.

8. The CAN transceiver according to claim 7, characterized in that: K serially coupled stepper drive circuits provide corresponding K high-side control signals and K low-side control signals, including a first high-side control signal to a K-th high-side control signal, and a first low-side control signal to a K-th low-side control signal; When the logic signal is switched from the first state to the second state, the first high-side control signal is switched from the first state to the second state, after a step delay, the second high-side control signal is switched from the first state to the second state, after K-1 step delays, the K high-side control signals are all switched to the second state; when the logic signal is switched from the first state to the second state, the first low-side control signal is switched from the second state to the first state, after a step delay, the second low-side control signal is switched from the second state to the first state, after K-1 step delays, the K low-side control signals are all switched to the first state; When the logic signal switches from the second state to the first state, the first high-side control signal switches from the second state to the first state, after a step delay, the second high-side control signal switches from the second state to the first state, after K-1 step delays, the K high-side control signals are all switched to the first state; when the logic signal switches from the second state to the first state, the first low-side control signal switches from the first state to the second state, after a step delay, the second low-side control signal switches from the first state to the second state, after K-1 step delays, the K low-side control signals are all switched to the second state.

9. The CAN transceiver according to claim 8, characterized in that: When the K high-side control signals are all switched to the second state, the difference between the high-side signal and the low-side signal is 0V, and when the K high-side control signals are all switched to the first state, the difference between the high-side signal and the low-side signal is 2.2V.

10. The CAN transceiver according to claim 7, characterized in that: The stepping drive circuit comprises: A first inverter having an input end and an output end, wherein the input end receives a logic signal or a high-side control signal provided by a previous stepper drive circuit, and the output end provides a low-side control signal, and the first inverter generates a low-side control signal inverted therefrom according to the logic signal or the high-side control signal provided by the previous stepper drive circuit; The second inverter has an input terminal and an output terminal, wherein the input terminal receives a low-side control signal and the output terminal provides a high-side control signal. The second inverter generates a high-side control signal inverted from the low-side control signal according to the low-side control signal.

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