Field plate structure and preparation method thereof, and semiconductor device and preparation method thereof

Abstract

The invention provides a field plate structure and a preparation method thereof, and a semiconductor device and a preparation method thereof, and the preparation method of the field plate structure comprises the following steps: providing a semiconductor structure, forming a laminated structure covering the upper surface of the semiconductor structure, the laminated structure comprises N dielectric layers which are laminated in sequence, the first dielectric layer covers the upper surface of the semiconductor structure, and the second dielectric layer covers the lower surface of the semiconductor structure; the Nth dielectric layer covers the (N-1) th dielectric layer, N is greater than or equal to 2, and the etching selection ratio between two adjacent dielectric layers in the N dielectric layers is not less than a preset ratio; (N-1) steps located on the same side of the laminated structure are formed, the (N-M) th step exposes the (N-M) th dielectric layer, and M is an integer smaller than N; and forming a field plate covering the N-1 steps. The N dielectric layers with high etching selection ratio are formed between the two adjacent dielectric layers on the upper surface of the semiconductor structure, and the steps and the field plate covering the steps are formed based on the N dielectric layers, so that the controllability of the process is improved, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a field plate structure and a preparation method, a semiconductor device and a preparation method. Background Art

[0002] Radio frequency lateral double diffused metal oxide semiconductor field effect transistor (RF-LDMOS) introduces a multi-layer field plate structure into the device, which not only improves the surface electric field of the device, but also improves the reliability of the device, while increasing the device's conduction capability, reducing the device's on-resistance, and greatly improving the device's RF performance. However, the field plate preparation process of RF-LDMOS with multi-layer field plates is relatively complicated. Figure 1 As shown, it is a schematic diagram of the cross-sectional structure of an RF-LDMOS device, including a substrate 01, a well region 011, a drift region 012, a source region 013, a drain region 014, a gate structure 02, a gate oxide layer 021, a gate polysilicon layer 022, a first metal silicide layer 023, a second metal silicide layer 024, a third metal silicide layer 025, a first dielectric layer 03, a second dielectric layer 031, an interlayer dielectric layer 032, a first field plate 04 and a second field plate 041. The preparation of the field plate requires two dielectric layer (first dielectric layer 03 and second dielectric layer 031) depositions and two field plate (first field plate 04 and second field plate 041) depositions and etchings, so the preparation is relatively complicated, and the controllability of the etching process is relatively poor. The etching thickness of the dielectric layer cannot be accurately controlled, and the thickness of the dielectric layer will affect the electric field distribution and breakdown voltage of the device, resulting in poor uniformity of the electric field distribution in the device and poor reliability of the device.

[0003] Therefore, there is an urgent need to find a method for preparing a field plate structure that can improve the controllability of the field plate structure etching process and the reliability of the device. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a field plate structure and a preparation method, a semiconductor device and a preparation method, so as to solve the problem of poor device reliability caused by poor controllability of the field plate manufacturing process in the prior art.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a field plate structure, comprising the following steps:

[0006] A semiconductor structure is provided, and a stacked structure is formed covering an upper surface of the semiconductor structure, wherein the stacked structure comprises N dielectric layers stacked in sequence, wherein a first dielectric layer covers the upper surface of the semiconductor structure, an Nth dielectric layer covers an N-1th dielectric layer, N is greater than or equal to 2, and an etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers is not less than a preset value;

[0007] Forming N-1 steps located on the same side of the stacked structure, the NMth step exposing the NMth dielectric layer, where M is an integer less than N;

[0008] A field plate is formed covering the N-1 steps and a portion of an upper surface of the Nth dielectric layer.

[0009] Optionally, the N dielectric layers include first dielectric layers and second dielectric layers alternately stacked in sequence, the first dielectric layers are made of silicon nitride or a silicon oxide / silicon nitride composite dielectric layer, and the second dielectric layers include silicon oxide.

[0010] Optionally, the preset ratio is not less than 15:1.

[0011] Optionally, the material of the L+1th dielectric layer is different from that of the L-1th dielectric layer, where L is an integer greater than 1 and less than N.

[0012] Optionally, the size of the Qth dielectric layer exposed by the Qth step is different from the size of the Q+1th dielectric layer exposed by the Q+1th step, where Q is an integer greater than or equal to 1 and less than N-1.

[0013] The present invention provides a field plate structure, and the field plate structure is manufactured by adopting the above-mentioned method for preparing the field plate structure.

[0014] The present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0015] A field plate structure manufactured by the method for manufacturing the field plate structure described above is provided, wherein the semiconductor structure comprises a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, the semiconductor layer comprises a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure, the N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and an end of the field plate close to the drain electrical contact region is spaced a preset distance from the drain electrical contact region;

[0016] A first electrode electrically connected to the source electrical contact region, a second electrode electrically connected to the drain electrical contact region, and a third electrode electrically connected to the gate structure are formed.

[0017] Optionally, the semiconductor layer also includes a first conductive type drift region and a second conductive type well region, the doping type of the source electric contact region and the drain electric contact region are the same as the doping type of the drift region, the source electric contact region is located on the upper surface of the well region, the drain electric contact region is located on the upper surface of the drift region, and the gate structure is located on the upper surface of the semiconductor layer between the source electric contact region and the drift region.

[0018] Optionally, a second contact region of the second conductivity type is further formed in the semiconductor layer and is located on an upper surface layer of the well region. The second contact region is close to a side wall of the drift region and is adjacent to a side wall of the source contact region away from the drift region.

[0019] Optionally, the semiconductor layer also includes a second conductive type substrate and a second conductive type epitaxial layer stacked in sequence, the well region and the drift region are located in the upper surface layer of the epitaxial layer, and a second conductive type first contact region is also formed in the semiconductor layer, the first contact region penetrates the epitaxial layer and extends at least to the top surface of the substrate, wherein the side surface of the first contact region is in contact with the second contact region.

[0020] Optionally, a first contact layer and a second contact layer are further formed in the semiconductor structure, the first contact layer covers the exposed upper surface of the source electrical contact region, and the second contact layer covers the exposed upper surface of the drain electrical contact region.

[0021] Optionally, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, and a projection size of the gate dielectric layer along the stacking direction of the gate dielectric layer and the gate conductive layer is not smaller than a projection size of the gate conductive layer along the stacking direction of the gate dielectric layer and the gate conductive layer.

[0022] Optionally, after forming the field plate and before forming the first electrode, the second electrode and the third electrode, the step also includes forming an interlayer dielectric layer covering the exposed upper surface of the stacked structure and the exposed surface of the field plate, the first electrode penetrates the interlayer dielectric layer and is electrically connected to the source electrical contact region, and the second electrode penetrates the interlayer dielectric layer and the stacked structure and is electrically connected to the drain electrical contact region.

[0023] Optionally, the semiconductor layer also includes a channel layer and a barrier layer stacked in sequence, the gate structure is located on the upper surface of the barrier layer, the source electrical contact region includes at least a stacked region of the barrier layer and the channel layer spaced a preset distance from the gate structure, and the drain electrical contact region includes at least a stacked region of the barrier layer and the channel layer spaced a preset distance from the gate structure.

[0024] The present invention also provides a semiconductor device, comprising:

[0025] A field plate structure manufactured by the method for manufacturing a field plate structure as described above, wherein the semiconductor structure comprises a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, the semiconductor layer comprises a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure, the N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and an end of the field plate close to the drain electrical contact region is spaced a preset distance from the drain electrical contact region;

[0026] A first electrode, a second electrode and a third electrode, wherein the first electrode is electrically connected to the source electrical contact region, the second electrode is electrically connected to the drain electrical contact region, and the third electrode is electrically connected to the gate structure.

[0027] As described above, the field plate structure and preparation method, the semiconductor device and preparation method of the present invention form a stacked structure including N stacked dielectric layers on the upper surface of the semiconductor structure by improving the manufacturing process of the field plate. There is a high etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers, so that in the process of forming the step, the lower dielectric layer of the two adjacent dielectric layers is the etching stop layer of the upper dielectric layer, which improves the controllability of the process, avoids damaging the first dielectric layer covering the semiconductor structure in the process of forming the step, ensures the quality of the first dielectric layer, and improves the uniformity and reliability of the device; utilizing the characteristic of the step increasing step by step, the field plate covering the step formed by etching the field plate material layer once can be equivalent to the electric field suppression effect of multiple field plate layers, reducing the number of etching times of the field plate in the device, reducing the cost, and facilitating large-scale mass production, and having a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of the structure of an RF-LDMOS device.

[0029] Figure 2 Shown is a process flow chart of a method for preparing a field plate structure of the present invention.

[0030] Figure 3 A schematic structural diagram showing a substrate in a method for manufacturing a semiconductor device of the present invention.

[0031] Figure 4 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a first contact region.

[0032] Figure 5 It is a schematic structural diagram showing the method for preparing a semiconductor device of the present invention after forming an isolation structure.

[0033] Figure 6 It is a schematic structural diagram showing the method for preparing a semiconductor device of the present invention after forming a gate dielectric layer.

[0034] Figure 7 It is a schematic structural diagram showing the method for preparing a semiconductor device of the present invention after forming a third contact layer.

[0035] Figure 8 It is a schematic structural diagram of the method for preparing a semiconductor device of the present invention after forming a drift region.

[0036] Fig. 9 It is a schematic structural diagram of the method for preparing a semiconductor device of the present invention after forming a well region.

[0037] Fig.10 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a second contact region.

[0038] Fig.11 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a first contact layer and a second contact layer.

[0039] Fig.12 It is a schematic structural diagram showing the method for preparing a semiconductor device of the present invention after forming a stacked structure.

[0040] Fig.13 It is a schematic diagram showing the structure after forming steps in the method for preparing a semiconductor device of the present invention.

[0041] Fig.14 It is a schematic structural diagram of the method for preparing a semiconductor device of the present invention after forming a field plate material layer.

[0042] Fig.15 It is a schematic structural diagram of the method for preparing a semiconductor device of the present invention after forming a field plate.

[0043] Fig.16 It shows a structural schematic diagram after forming an interlayer dielectric layer in the method for preparing a semiconductor device of the present invention.

[0044] Fig.17 Another structural schematic diagram is shown after forming an interlayer dielectric layer in the method for preparing a semiconductor device of the present invention.

[0045] Fig.18 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a first plug and a second plug.

[0046] Fig.19 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a first interconnection layer and a second interconnection layer.

[0047] Fig. 20 It is a schematic structural diagram showing the method for preparing a semiconductor device of the present invention after forming an insulating layer.

[0048] Fig.21 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a fourth plug and a fifth plug.

[0049] Fig. 22 It is a schematic structural diagram showing the method for manufacturing a semiconductor device of the present invention after forming a first pad and a second pad.

[0050] Fig.23 It is a schematic diagram showing the structure after forming a passivation layer in the method for preparing a semiconductor device of the present invention.

[0051] Fig.24 It is a schematic structural diagram showing the method for preparing a semiconductor device of the present invention after forming a back electrode layer.

[0052] Description of Figure Numbers

[0053] 01 Substrate

[0054] 011 Well region

[0055] 012 Drift Zone

[0056] 013 Source Area

[0057] 014 Leakage Area

[0058] 02 Gate structure

[0059] 021 Gate Oxide Layer

[0060] 022 Gate polysilicon layer

[0061] 023 First metal silicide layer

[0062] 024 Second metal silicide layer

[0063] 025 Third metal silicide layer

[0064] 03 First dielectric layer

[0065] 031 Second dielectric layer

[0066] 032 Interlayer dielectric layer

[0067] 04 First board

[0068] 041 The Second Board

[0069] 1 Semiconductor layer

[0070] 10 Substrate

[0071] 11 Epitaxial layer

[0072] 12 Drift Zone

[0073] 13 Well region

[0074] 14 Source electrical contact area

[0075] 15 Drain electrical contact area

[0076] 16 First contact area

[0077] 17 Second contact area

[0078] 18 Isolation Structure

[0079] 2 Gate structure

[0080] 20 Semiconductor Structure

[0081] 21. Gate dielectric layer

[0082] 22. Gate conductive layer

[0083] 23 First contact layer

[0084] 24 Second contact layer

[0085] 25 Third contact layer

[0086] 3. Laminated structure

[0087] 31 First dielectric layer

[0088] 32 Second dielectric layer

[0089] 4 steps

[0090] 5 Field Board

[0091] 51 Field plate material layer

[0092] 52 Interlayer dielectric layer

[0093] 6. First electrode

[0094] 61 First Plug

[0095] 62 First interconnect layer

[0096] 63 Fourth Plug

[0097] 64 First pad

[0098] 65 back electrode layer

[0099] 7 Second electrode

[0100] 71 Second plug

[0101] 72 Second Interconnection Layer

[0102] 73 Fifth Plug

[0103] 74 Second pad

[0104] 8 Insulation layer

[0105] 9 Passivation layer DETAILED DESCRIPTION

[0106] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0107] See also Figures 2 to 24 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0108] Embodiment 1

[0109] This embodiment provides a method for preparing a field plate structure, such as Figure 2 FIG. 1 is a process flow chart of the method for preparing the field plate structure, comprising the following steps:

[0110] S1-1: providing a semiconductor structure, forming a stacked structure covering the upper surface of the semiconductor structure, the stacked structure comprising N dielectric layers stacked in sequence, the first dielectric layer covering the upper surface of the semiconductor structure, the Nth dielectric layer covering the N-1th dielectric layer, N being greater than or equal to 2, and the etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers being no less than a preset ratio;

[0111] S1-2: forming N-1 steps located on the same side of the stacked structure, the NMth step exposing the NMth dielectric layer, where M is an integer less than N;

[0112] S1 - 3 : forming a field plate covering the N-1 steps and a portion of the upper surface of the Nth dielectric layer.

[0113] Specifically, please perform steps S1-1 and S1-2: provide a semiconductor structure to form a stacked structure covering the upper surface of the semiconductor structure, the stacked structure includes N dielectric layers stacked in sequence, the first dielectric layer covers the upper surface of the semiconductor structure, the Nth dielectric layer covers the N-1th dielectric layer, N is greater than or equal to 2, and the etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers is not less than a preset ratio; form N-1 steps located on the same side of the stacked structure, the NMth step exposes the NMth dielectric layer, and M is an integer less than N.

[0114] Specifically, the semiconductor structure is a structure for manufacturing a field plate. Under the condition of ensuring the performance of subsequent devices, the size, shape and thickness of the semiconductor structure can be selected according to actual conditions; the number of stacked film layers in the semiconductor structure, the thickness of each stacked film layer, and the distribution of each doped region and each component can be selected according to actual conditions. The components here refer to the parts that make up the semiconductor structure, for example, the gate structure of a MOS device.

[0115] As an example, the N-layer dielectric layer includes a first dielectric layer and a second dielectric layer alternately stacked in sequence, the material of the first dielectric layer includes silicon nitride or a silicon oxide / silicon nitride composite dielectric layer, or other suitable dielectric materials, such as silicon oxynitride and aluminum nitride; the second dielectric layer includes silicon oxide or other suitable dielectric materials, such as aluminum oxide. Preferably, a composite film layer composed of stacked silicon oxide layers and silicon nitride layers is used as the first dielectric layer, and a silicon oxide layer is used as the second dielectric layer.

[0116] Specifically, the method of forming each dielectric layer in the stacked structure includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0117] Specifically, the value of N can be selected according to actual conditions while ensuring the performance of subsequent devices.

[0118] As an example, the preset ratio is not less than 15:1, that is, the etching selectivity ratio between two adjacent dielectric layers of the N dielectric layers is not less than 15:1.

[0119] Specifically, since there is a high etching selectivity ratio between two adjacent dielectric layers in the N-layer dielectric layer, during the step formation process, the next dielectric layer serves as an etching stop layer for the previous dielectric layer.

[0120] As an example, the material of the L+1th dielectric layer is different from that of the L-1th dielectric layer, where L is an integer greater than 1 and less than N, that is, among the N dielectric layers, for any three consecutively stacked dielectric layers, the material of the bottom dielectric layer is different from that of the top dielectric layer, and the etching selectivity ratio between the bottom dielectric layer and the middle dielectric layer in the three dielectric layers is not less than a preset ratio, and the etching selectivity ratio between the top dielectric layer and the middle dielectric layer in the three dielectric layers is also not less than a preset ratio.

[0121] Specifically, while ensuring the performance of subsequent devices, the materials of the N dielectric layers may be different.

[0122] As an example, two adjacent dielectric layers in the N dielectric layers have different thicknesses.

[0123] As an example, the thickness of the P-1th dielectric layer is different from the thickness of the P+1th dielectric layer, where P is an integer greater than 1 and less than N.

[0124] Specifically, under the condition of ensuring the performance of subsequent devices, the thicknesses of the N dielectric layers can be different or the same.

[0125] Specifically, forming N-1 steps includes the following steps: forming a patterned first photoresist layer on the upper surface of the stacked structure, and etching each dielectric layer in turn based on the patterned first photoresist layer until the second dielectric layer can be etched to obtain the first step; removing the first photoresist layer, and repeating the above steps until the N-1th step is formed based on the N-1th photoresist layer and the N-1th photoresist layer is removed to obtain the N-1th step.

[0126] Specifically, while ensuring the morphology of the formed N-1 steps, the N-1th step may be formed based on the first photoresist layer, and then the etching steps are repeated until the first step is formed based on the N-1th photoresist layer.

[0127] Specifically, the method of etching each dielectric layer in the stacked structure includes dry etching, wet etching or other suitable methods.

[0128] As an example, the size of the Qth dielectric layer revealed by the Qth step is different from the size of the Q+1th dielectric layer revealed by the Q+1th step, where Q is an integer greater than or equal to 1 and less than N-1, that is, the sizes of the dielectric layers revealed by two adjacent steps are different.

[0129] Specifically, under the condition of ensuring the performance of subsequent devices, the sizes of the dielectric layers exposed by two adjacent steps may also be the same.

[0130] Specifically, step S1 - 3 is performed: forming a field plate covering N−1 steps and a portion of the upper surface of the Nth dielectric layer.

[0131] Specifically, after forming N-1 steps and before forming the field plate, the steps also include forming a field plate material layer covering the exposed surface of the N-1 steps and the exposed upper surface of the Nth dielectric layer and etching the field plate material layer, and the field plate is obtained by etching the field plate material layer.

[0132] Specifically, the method of forming the field plate material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of etching the field plate material layer includes dry etching, wet etching or other suitable methods.

[0133] Specifically, the field plate is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials. Preferably, a tungsten layer is used as the field plate.

[0134] Specifically, while ensuring the performance of subsequent devices, the size of the portion of the field plate covering the Nth dielectric layer can be selected according to actual conditions.

[0135] Specifically, by improving the process of forming the field plate, a stacked structure covering the upper surface of the semiconductor structure and including N dielectric layers stacked in sequence is formed, and a high etching selectivity ratio is provided between two adjacent dielectric layers in the N dielectric layers, so that the next dielectric layer becomes an etching stop layer for the previous dielectric layer, thereby improving the controllability of the process and avoiding damage to the first dielectric layer, thereby ensuring the quality of the first dielectric layer.

[0136] Specifically, by forming N-1 steps and then forming a field plate covering the steps, a field plate with an electric field suppression effect equivalent to that of multiple field plate layers can be obtained by etching the field plate material layer only once, which simplifies the number of etching times of the field plate in the field plate structure, simplifies the manufacturing steps, reduces costs, and is more conducive to large-scale mass production.

[0137] The preparation method of the field plate structure of the present embodiment forms a stacked structure covering the upper surface of the semiconductor structure by improving the manufacturing process of the field plate. The stacked structure includes N dielectric layers stacked in sequence, and there is a high etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers, so that the next dielectric layer is an etching stop layer for the previous dielectric layer, thereby improving the controllability of the process and ensuring the quality of the first dielectric layer covering the upper surface of the semiconductor structure; after forming N-1 steps, a field plate covering the steps is formed, and a field plate with an electric field suppression effect equivalent to that of multiple field plate layers can be obtained by etching the field plate material layer only once, thereby simplifying the number of etching times of the field plate in the field plate structure, simplifying the manufacturing steps, reducing the cost, and being more conducive to large-scale mass production.

[0138] Embodiment 2

[0139] This embodiment provides a field plate structure, which is manufactured by using the above-mentioned method for manufacturing the field plate structure.

[0140] Specifically, the field plate structure includes a semiconductor structure, a stacked structure, N-1 steps and a field plate. The stacked structure includes N dielectric layers stacked in sequence, the first dielectric layer covers the upper surface of the semiconductor structure, the Nth dielectric layer covers the N-1th dielectric layer, N is greater than or equal to 2, and the etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers is not less than a preset value; the N-1 steps are located on the same side of the stacked structure, the NMth step exposes the NMth dielectric layer, and M is an integer less than N; the field plate covers the N-1 steps and a portion of the upper surface of the Nth dielectric layer.

[0141] Specifically, the semiconductor structure is a semiconductor device for manufacturing a field plate, and the structural structure of the semiconductor structure can be selected according to actual conditions.

[0142] Specifically, the preset ratio is not less than 15:1, that is, the etching selection ratio between two adjacent dielectric layers in the N dielectric layers is not less than 15:1.

[0143] Specifically, under the condition of ensuring the performance of the device, the thickness of each dielectric layer in the N dielectric layers can be selected according to actual conditions.

[0144] Specifically, while ensuring the performance of subsequent devices, the thickness of the field plate can be selected according to actual conditions.

[0145] Specifically, by adopting the method for preparing the field plate structure described in the first embodiment to manufacture the field plate structure, the quality of the first dielectric layer covering the upper surface of the semiconductor structure is improved, and the uniformity and reliability of subsequent devices are ensured.

[0146] The field plate structure of this embodiment is manufactured by adopting the method for preparing the field plate structure described in the first embodiment, thereby improving the quality of the first dielectric layer covering the upper surface of the semiconductor structure and ensuring the uniformity and reliability of subsequent devices.

[0147] Embodiment 3

[0148] This embodiment provides a method for preparing a semiconductor device, comprising the following steps:

[0149] S2-1: A field plate structure manufactured by the method for manufacturing the field plate structure described above is provided, wherein the semiconductor structure comprises a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, the semiconductor layer comprises a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure, the N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and an end of the field plate close to the drain electrical contact region is spaced a preset distance from the drain electrical contact region;

[0150] S2-2: forming a first electrode electrically connected to the source electrical contact region, a second electrode electrically connected to the drain electrical contact region, and a third electrode electrically connected to the gate structure.

[0151] See also Figures 3 to 11 The production process diagram of semiconductor structure Figures 12 to 15 The process diagram of the field plate manufacturing process, executing step S2-1: providing a field plate structure manufactured by the method for preparing the field plate structure described above, wherein the semiconductor structure 20 includes a semiconductor layer 1 and a gate structure 2 located on the upper surface of the semiconductor layer 1, the semiconductor layer 1 includes a source electrical contact region 14 and a drain electrical contact region 15 located on opposite sides of the gate structure 2, N-1 steps 4 are located in the stacked structure 3 between the gate structure 2 and the drain electrical contact region 15, and one end of the field plate 5 close to the drain electrical contact region 15 is spaced a preset distance from the drain electrical contact region 15.

[0152] As an example, the semiconductor layer 1 also includes a first conductive type drift region 12, a second conductive type well region 13, and a second conductive type substrate 10 and a second conductive type epitaxial layer 11 stacked in sequence. The doping type of the source electric contact region 14 and the drain electric contact region 15 is the same as the doping type of the drift region 12. The well region 13 and the drift region 12 are located on the upper surface of the epitaxial layer 11, the source electric contact region 14 is located on the upper surface of the well region 13, the drain electric contact region 15 is located on the upper surface of the drift region 12, and the gate structure 2 is located on the upper surface of the semiconductor layer 1 between the source electric contact region 14 and the drift region 12 (that is, the gate structure 2 is located on the upper surface of the epitaxial layer 11 between the source electric contact region 14 and the drift region 12).

[0153] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0154] Specifically, the semiconductor device is a radio frequency LDMOS as an example. Figure 3 As shown, it is a schematic diagram of the structure of the substrate 10. The substrate 10 is used to make a device process platform. Under the condition of ensuring the performance of the device, the thickness and shape of the substrate 10 can be selected according to the actual situation; the thickness of the epitaxial layer 11 can be selected according to the actual situation. In this embodiment, the thickness of the substrate 10 is 1 mm, and the thickness of the epitaxial layer 11 is 5 μm.

[0155] Specifically, the doping concentration of the epitaxial layer 11 is lower than the doping concentration of the substrate, so that the epitaxial layer 11 has a high resistance characteristic and the substrate 10 has a low resistance characteristic.

[0156] As an example, Figure 4 As shown, it is a schematic diagram of the structure after the first contact area 16 is formed. A second conductive type first contact area 16 is also formed in the semiconductor layer 1. The first contact area 16 penetrates the epitaxial layer 11 and extends at least to the top surface of the substrate 10 to lead the first electrode of the device to the back side of the device, thereby reducing the parasitic inductance of the source end of the device.

[0157] Specifically, the method of forming the first contact region 16 includes ion implantation or other suitable methods.

[0158] Specifically, when the first contact region 16 is formed by an ion implantation process, a suitable trivalent element, such as boron, indium, or gallium, may be doped into the epitaxial layer 11 and the region corresponding to the first contact region 16 in the substrate 10. In this embodiment, boron ions are implanted into the region corresponding to the first contact region 16 in the epitaxial layer 11 and the substrate 10, and then a high-temperature well-driving process is performed to activate the doped region doped with boron ions and form the first contact region 16.

[0159] Specifically, the first contact region 16 is a heavily doped region, so as to form a good interconnection with a low-resistance substrate while activating the first contact region 16 .

[0160] Specifically, Figure 5 , which is a schematic diagram of the structure after the isolation structure 18 is formed, the isolation structure 18 is also formed in the semiconductor layer 1, and the isolation structure 18 is used to define the active area of ​​the device, and the isolation structure 18 is embedded in the upper surface layer of the epitaxial layer 11, and the first contact area 16 is located in the active area, wherein the isolation structure 18 can be a shallow trench isolation structure or a local oxidation isolation (LOCOS) structure. In this embodiment, a wet oxidation process is used to form a local oxidation isolation layer in the epitaxial layer as the isolation structure 18.

[0161] As an example, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 stacked in sequence, and the size of the projection of the gate dielectric layer 21 along the stacking direction of the gate dielectric layer 21 and the gate conductive layer 22 is not smaller than the size of the projection of the gate conductive layer 22 along the stacking direction of the gate dielectric layer 21 and the gate conductive layer 22.

[0162] Specifically, forming the gate structure 2 includes the following steps: forming a gate dielectric layer 21 on the upper surface of the epitaxial layer 11 in the active area, and forming a gate conductive material layer of a preset thickness on the upper surface of the gate dielectric layer 21; etching the gate conductive material layer to obtain a gate conductive layer 22, and the gate dielectric layer 21 and the gate conductive layer 22 constitute the gate structure 2.

[0163] Specifically, Figure 6 , which is a schematic diagram of the structure after forming the gate dielectric layer 21, the method of forming the gate dielectric layer 21 includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods. In this embodiment, the gate dielectric layer 21 is formed by dry oxygen oxidation process.

[0164] Specifically, Figure 7 As shown, it is a schematic diagram of the structure after the third contact layer 25 is formed. After the gate conductive material layer is formed and before the gate conductive material layer is etched, it also includes the step of forming the third contact layer 25 on the upper surface of the gate conductive material layer. The third contact layer 25 is used to reduce the contact resistance between the subsequently formed gate conductive layer 22 and the subsequently formed third electrode, so that good contact is formed between the gate conductive layer 22 and the third electrode, so as to improve the RF performance of the device.

[0165] Specifically, the method of forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the third contact layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0166] Specifically, under the condition of ensuring the device performance, the third contact layer 25 may not be formed. In this embodiment, in order to improve the device performance, a stacked gate conductive material layer and a third contact layer 25 are sequentially formed on the upper surface of the gate dielectric layer 21 .

[0167] Specifically, the method for etching the gate conductive material layer includes dry etching, wet etching or other suitable methods. When a third contact layer 25 is formed on the upper surface of the gate conductive material layer, the third contact layer 25 and the gate conductive material layer are etched in sequence, and the process for etching the third contact layer 25 can be the same as the process type for etching the gate conductive material layer, or can be different, that is, both film layers can be etched by dry etching or wet etching process, or one film layer can be etched by dry etching process and the other film layer can be etched by wet etching process, and the etchants for etching the two film layers can be selected according to actual conditions.

[0168] Specifically, Figure 8 As shown, it is a schematic diagram of the structure after the drift region 12 is formed. The drift region 12 is used to ensure the breakdown voltage of the device so that the device can meet the requirements of the application scenario. The method of forming the drift region 12 includes ion implantation or other suitable methods. In this embodiment, the gate self-alignment process is adopted and the upper surface layer of the epitaxial layer 11 on the side of the gate structure 2 away from the first contact region 16 is doped with phosphorus ions by lightly doped ion implantation, and high temperature activation and push junction are performed after doping to obtain the drift region 12.

[0169] Specifically, Fig. 9 As shown, it is a schematic diagram of the structure after the well region 13 is formed. The well region 13 is used to provide the device with a threshold voltage that meets the requirements. By adjusting the doping concentration of the well region 13, the threshold voltage of the device can be adjusted. At the same time, the well region 13 and the drift region 12 work together to limit the electric field strength of the gate structure 2 away from the side of the first contact region 16 (that is, the area between the gate structure 2 and the drain electrical contact region formed subsequently), thereby controlling the hot carrier effect in the device and improving the reliability of the device.

[0170] Specifically, the method for forming the well region 13 includes ion implantation or other suitable methods. In this embodiment, a gate self-alignment process is adopted and the upper surface layer of the epitaxial layer 11 on the side of the gate structure 2 close to the first contact region 16 is doped with boron ions by ion implantation, and high temperature activation and push-junction are performed after doping to obtain the well region 13, and the well region 13 extends at least to the bottom of the gate structure 2.

[0171] Specifically, the method for forming the source electrical contact region 14 includes ion implantation or other suitable methods; the method for forming the drain electrical contact region 15 includes ion implantation or other suitable methods. In this embodiment, As ions are implanted into the corresponding regions of the epitaxial layer 11 to form heavily doped N-type source electrical contact regions (i.e., source regions of the RF LDMOS device) 14 and N-type drain electrical contact regions (i.e., drain regions of the RF LDMOS device) 15.

[0172] Specifically, the gate conductive layer 22 is located above the area between the source electrical contact region 14 and the drift region 12 . Considering the process deviation, the two ends of the gate conductive layer 22 along the direction from the source electrical contact region 14 to the drain electrical contact region 15 can extend to above the source electrical contact region 14 and the drift region 12 .

[0173] Specifically, the source electrical contact region 14 and the drain electrical contact region 15 can be formed simultaneously or in steps. In this embodiment, a source / drain mask layer is first formed on the upper surface of the epitaxial layer 11 after the well region 13 is formed, and then arsenic ions are injected into the epitaxial layer 11 based on the source / drain mask layer, and high-temperature annealing is performed after the ion injection is completed to simultaneously form heavily doped source and drain regions, that is, to simultaneously form the source electrical contact region 14 and the drain electrical contact region 15.

[0174] As an example, Fig.10 As shown, it is a schematic diagram of the structure after the second contact region 17 is formed. A second conductive type second contact region 17 located on the upper surface of the well region 13 is also formed in the semiconductor layer 1. The second contact region 17 is close to the side wall of the drift region 12 and is adjacent to the side wall of the source contact region 14 away from the drift region 12.

[0175] Specifically, the side wall of the well region 13 away from the drift region 12 is adjacent to the side wall of the first contact region 16 close to the drift region 12, the second contact region 17 is located on the upper surface of the well region 13 between the source electrical contact region 14 and the first contact region 16, and the second contact region 17 is in contact with the side wall of the source electrical contact region 14 away from the drift region 12, and the side surface of the first contact region 16 is in contact with the second contact region 17.

[0176] Specifically, the method of forming the second contact region 17 includes ion implantation or other suitable methods.

[0177] Specifically, when the second contact region 17 is formed in the semiconductor layer 1, ion implantation can be performed based on the source / drain mask layer and then the source / drain mask layer can be removed. A mask layer for making the second contact region 17 can be formed on the upper surface of the epitaxial layer after the source / drain mask layer is removed. Then, boron ions are implanted into the epitaxial layer 11 based on the mask. Finally, after the boron ion implantation is completed, high-temperature annealing is performed to obtain the heavily doped second contact region 17, the source electrical contact region 14 and the drain electrical contact region 15.

[0178] As an example, Fig.11 As shown, it is a schematic diagram of the structure after the first contact layer 23 and the second contact layer 24 are formed. The first contact layer 23 and the second contact layer 24 are also formed in the semiconductor structure 20. The first contact layer 23 covers the exposed upper surface of the source electrical contact area 14, and the second contact layer 24 covers the exposed upper surface of the drain electrical contact area 15.

[0179] Specifically, forming the first contact layer 23 and the second contact layer 24 includes the following steps: forming a patterned shielding layer on the upper surface of the epitaxial layer 11 after forming the source electrical contact region 14 and the drain electrical contact region 15; etching the gate dielectric layer 21 based on the patterned shielding layer to expose the first contact region 16, the second contact region 17, the source electrical contact region 14 and the drain electrical contact region 15; forming a metal layer covering the exposed surface of the first contact region 16, the second contact region 17, the source electrical contact region 14 and the drain electrical contact region 15, and annealing so that the metal layer forms an alloy with silicon at a high temperature, and then obtaining a metal silicide layer as the first contact layer 23 and the second contact layer 24.

[0180] Specifically, by forming the first contact layer 23 and the second contact layer 24 on the exposed surfaces of the source electrical contact region 14 and the drain electrical contact region 15 , the contact resistance between the subsequently formed first electrode and the second electrode and the corresponding source electrical contact region 14 and the drain electrical contact region 15 can be reduced.

[0181] Specifically, the shielding layer is a mask material commonly used in the silicide manufacturing process that does not react with the metal during the annealing process, and its manufacturing process and material are not described in detail; the material of the metal layer includes Ti, Co, Ni or other suitable metal materials, and its formation process is a commonly used metal deposition process, which is not described in detail here. In this embodiment, the metal deposited on the exposed surface of the source electrical contact region 14 and the drain electrical contact region 15 is Ti. After high-temperature annealing, Ti reacts with the silicon on the surface of the source electrical contact region 14 and the drain electrical contact region 15 to form a TiSi alloy.

[0182] Specifically, after forming the metal layer covering the exposed surfaces of the first contact region 16, the second contact region 17, the source electrical contact region 14 and the drain electrical contact region 15, the annealing temperature and annealing time are related to the material of the corresponding metal layer and are not limited here.

[0183] Specifically, after forming the first contact layer 23 and the second contact layer 24 and before forming the stacked structure 3 , a step of removing the shielding layer and the unreacted metal layer is further included to obtain the semiconductor structure 20 .

[0184] Specifically, the method of removing the shielding layer includes dry etching, wet etching or other suitable methods; the method of removing the unreacted metal layer includes dry etching, wet etching or other suitable methods.

[0185] Specifically, under the condition of ensuring the performance of the device, the first contact layer 23 and the second contact layer 24 may also be formed separately.

[0186] Specifically, Fig.12 As shown, it is a schematic diagram of the structure after the stacked structure 3 is formed. Under the condition of ensuring the performance of the device, the number of dielectric layers in the stacked structure 3 can be selected according to the actual situation. In this embodiment, two dielectric layers are used as an example for explanation. First, a thin silicon oxide layer with a thickness of 20nm is formed on the upper surface of the semiconductor structure as a buffer layer, and then a silicon nitride layer with a thickness of 130nm is formed. The composite film layer composed of the thin silicon oxide layer and the silicon nitride layer is used as the first dielectric layer 31. At the same time, the thin silicon oxide layer is used to relieve the stress generated by the formed silicon nitride layer. After the first dielectric layer 31, a silicon oxide layer stacked on the upper surface of the first dielectric layer is formed as the second dielectric layer 32, and then the stacked structure 3 composed of the first dielectric layer 31 and the second dielectric layer 32 is obtained. In other embodiments, the thickness of the buffer layer can be selected between 5nm and 50nm, the thickness of the silicon nitride layer can be selected between 50nm and 300nm, and the thickness of the second dielectric layer 32 can be selected between 100nm and 500nm.

[0187] Specifically, Fig.13 As shown, it is a schematic diagram of the structure after the step 4 is formed. Under the condition of ensuring the performance of the device, the distance between the end of the step 4 close to the gate structure 2 and the gate structure 2 can be selected according to the actual situation; the distance between the end of each step 4 close to the drain electrical contact area 15 and the gate structure 2 can be selected according to the actual situation. In this embodiment, only one step is formed in the stacked structure 3, and the distance between the end of the step 4 close to the gate structure 2 and the gate structure 2 is the thickness of the first dielectric layer 31 covering the side wall of the gate structure 2, and the distance between the end of the step 4 close to the drain electrical contact area 15 and the gate structure 2 is 0.7μm. In other embodiments, the distance between the end of the step 4 close to the drain electrical contact area 15 and the gate structure 2 can be selected to be between 0.5μm and 1.5μm.

[0188] Specifically, Fig.14 and Fig.15As shown, they are schematic diagrams of the structure after forming the field plate material layer 51 and the schematic diagram of the structure after forming the field plate 5, respectively. Under the condition of ensuring the device performance, the distance between the end of the field plate 5 close to the drain electrical contact area 15 and the gate structure 2 can be selected according to the actual situation. In this embodiment, a tungsten metal layer is formed on the upper surface of the structure after the step 4 is formed as the field plate material layer, and then a patterned field plate mask layer is formed on the upper surface of the field plate material layer 51, and the field plate material layer 51 is etched once based on the patterned field plate mask layer to obtain the field plate 5, and the distance between the end of the field plate 5 close to the drain electrical contact area 15 and the gate structure 2 is 1.5μm. In other embodiments, the distance between the end of the field plate 5 close to the drain electrical contact area 15 and the gate structure 2 is between 0.8μm and 2.5μm.

[0189] Specifically, while ensuring device performance, the end of the field plate 5 close to the gate structure 2 can be flush with the end of the step 4 close to the gate structure 2, or it can extend to just above the gate structure 2 and be separated from the edge of the gate structure 2 close to the drain electrical contact area 15 by a preset distance.

[0190] See also Figures 16 to 24 , perform step S2 - 2 : form a first electrode 6 electrically connected to the source electrical contact region 14 , a second electrode 7 electrically connected to the drain electrical contact region 15 , and a third electrode electrically connected to the gate structure 2 .

[0191] As an example, Fig.16 and Fig.17 As shown, there are respectively a schematic diagram of a structure after forming an interlayer dielectric layer 52 (1 step) and another schematic diagram of a structure after forming the interlayer dielectric layer 52 (2 steps). After forming the field plate 5 and before forming the first electrode 6, the second electrode 7 and the third electrode, the step of forming the interlayer dielectric layer 52 covering the exposed upper surface of the stacked structure 3 and the exposed surface of the field plate 5 is also included. The first electrode 6 penetrates the interlayer dielectric layer 52 and is electrically connected to the source electrical contact area 14. The second electrode 7 penetrates the interlayer dielectric layer 52 and the stacked structure 3 and is electrically connected to the drain electrical contact area 15.

[0192] Specifically, the method of forming the interlayer dielectric layer 52 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0193] Specifically, after forming the interlayer dielectric layer 52 and before forming the first electrode 6 , the second electrode 4 and the third electrode, a step of thinning the interlayer dielectric layer 52 is further included to make the thickness of the interlayer dielectric layer 52 reach a preset thickness.

[0194] Specifically, the method of thinning the interlayer dielectric layer 52 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods. In this embodiment, the interlayer dielectric layer 52 is thinned by using a chemical mechanical polishing process.

[0195] Specifically, under the condition of ensuring the device performance, the thickness of the interlayer dielectric layer 52 can be selected according to the actual situation, and no limitation is given here. In this embodiment, the thickness of the interlayer dielectric layer 52 obtained after thinning is 3 μm.

[0196] Specifically, the first electrode 6 is electrically connected to the source electrical contact region 14 through the first contact layer 23 , the second electrode 7 is electrically connected to the drain electrical contact region 15 through the second contact layer 24 , and the third electrode is electrically connected to the gate conductive layer 22 through the third contact layer 25 .

[0197] Specifically, Fig.18 and Fig.19 As shown, the schematic diagrams of the structure after forming the first plug 61 and the second plug 71 and the schematic diagrams of the structure after forming the first interconnection layer 62 and the second interconnection layer 72 are shown respectively. The formation of the first electrode 6, the second electrode 7 and the third electrode comprises the following steps: forming a first contact hole, a second contact hole and a third contact hole penetrating the interlayer dielectric layer 52 in the interlayer dielectric layer 52, the bottom surfaces of the first contact hole respectively reveal the first contact layer 23 and the field plate 5, and the first contact hole revealing the field plate 5 and revealing the first contact layer 23 are separated by a preset distance, the bottom surface of the second contact hole reveals the second contact layer 24, and the bottom surface of the third contact hole reveals the third contact layer 25; forming a first contact hole, a second contact hole and a third contact hole filled with the first contact hole, and a covering layer The first filling layer on the upper surface of the interlayer dielectric layer 52 is removed to obtain a first plug 61 filling the first contact hole, a second plug 71 filling the second contact hole, and a third plug filling the third contact hole; an interconnection material layer covering the upper surface of the interlayer dielectric layer 52 is formed and the interconnection material layer is etched to simultaneously obtain a first interconnection layer 62, a second interconnection layer 72, and a third interconnection layer, the first interconnection layer 62 and the first plug 61 are electrically connected and together form a first electrode 6 with the first plug 61, the second interconnection layer 72 and the second plug 71 are electrically connected and together form a second electrode 7 with the second plug 71, and the third interconnection layer and the third plug are electrically connected and together form a third electrode with the third plug. In this embodiment, two first contact holes spaced apart are formed above the first contact layer 23 to reduce the contact resistance between the first electrode 6 and the first contact region 16 and the second contact region 17. Under the condition of ensuring the device performance, one first contact hole may be formed on the side of the gate structure 2 close to the first contact region 16, or three or more first contact holes may be formed.

[0198] Specifically, the method of forming the first contact hole in the interlayer dielectric layer 52 includes dry etching, wet etching or other suitable methods; the method of forming the second contact hole and the third contact hole is the same as the method of forming the first contact hole, which will not be repeated here.

[0199] Specifically, while ensuring device performance, the number, size and shape of the first contact holes can be selected according to actual conditions; the size and shape of the third contact holes can be selected according to actual conditions and are no longer restricted here; the size and shape of the second contact holes can be selected according to actual conditions.

[0200] Specifically, the method of forming the first filling layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of forming the interconnection material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0201] Specifically, the method of removing the first filling layer covering the upper surface of the interlayer dielectric layer 52 includes dry etching, wet etching, chemical mechanical polishing or other suitable methods; the method of etching the interconnect material layer includes dry etching, wet etching or other suitable methods.

[0202] Specifically, the first electrode 6 is electrically connected to the source electrical contact region 14, the second contact region 17, the first contact region 16 and the field plate 5 respectively through the first contact hole penetrating the interlayer dielectric layer 52, the second electrode 7 is electrically connected to the drain electrical contact region 15 through the second contact hole, and the third electrode is electrically connected to the gate conductive layer through the third contact hole.

[0203] Specifically, Fig.21 and Fig. 22As shown in the figure, they are schematic diagrams of the structure after the fourth plug 63 and the fifth plug 73 are formed, and schematic diagrams of the structure after the first pad 64 and the second pad 74 are formed. After the first electrode 6, the second electrode 7 and the third electrode are formed, the following steps are also included: forming an insulating layer 8 covering the upper surface of the interlayer dielectric layer 52 and the exposed surface of each electrode (the first electrode 6, the second electrode 7 and the third electrode); forming a first lead-out hole, a second lead-out hole and a third lead-out hole penetrating the insulating layer 8; forming a second filling layer filling the first lead-out hole, the second lead-out hole and the third lead-out hole and covering the upper surface of the insulating layer 8, and removing the second filling layer covering the upper surface of the insulating layer 8 to obtain a fourth lead-out hole filling the first lead-out hole Plug 63, a fifth plug 73 filling the second lead-out hole and a sixth plug filling the third lead-out hole; forming a pad layer covering the upper surfaces of the insulating layer 8, the fourth plug 63, the fifth plug 73 and the sixth plug, and etching the pad layer to obtain the first pad 64, the second pad 74 and the third pad; forming a passivation layer 9 covering the exposed surfaces of the first pad 64, the second pad 74 and the third pad and the upper surface of the insulating layer 8, and etching the passivation layer 9 to expose the first pad 64, the second pad 74 and the third pad; thinning the substrate 10 from the back side of the substrate 10 to a preset thickness, and forming a back electrode layer 65 on the back side of the thinned substrate 10, and then obtaining a MOS device.

[0204] Specifically, Fig. 20 , which is a schematic diagram of the structure after the insulating layer 8 is formed. The method of forming the insulating layer 8 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0205] Specifically, after forming the insulating layer 8 and before forming the first lead-out hole, the second lead-out hole and the third lead-out hole, the step of thinning the insulating layer 8 to a preset thickness is also included.

[0206] Specifically, the method of thinning the insulating layer 8 includes dry etching, wet etching, chemical mechanical polishing or other suitable methods.

[0207] Specifically, the method of forming the first lead-out hole, the second lead-out hole and the third lead-out hole penetrating the insulating layer 8 includes dry etching, wet etching or other suitable methods.

[0208] Specifically, the method of forming the second filling layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of removing the second filling layer covering the upper surface of the insulating layer 8 includes dry etching, wet etching, chemical mechanical grinding or other suitable methods; the method of forming the pad layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of etching the pad layer includes dry etching, wet etching or other suitable methods.

[0209] It should be noted that, depending on the needs and performance requirements of the semiconductor device, only one electrode layer may be included, that is, no Fig.21 and Fig. 22 The plugs and pads above the first electrode 6, the second electrode 7 and the third electrode may also include an electrode structure with more than two layers, which is not limited here.

[0210] Specifically, Fig.23 , which is a schematic diagram of the structure after the passivation layer 9 is formed. The method of forming the passivation layer 9 includes physical vapor deposition, chemical vapor deposition or other suitable methods.

[0211] Specifically, Fig.24 As shown, it is a schematic diagram of the structure after the back electrode layer 65 is formed. The method of etching the passivation layer 9 includes dry etching, wet etching or other suitable methods; the method of thinning the substrate 10 from the back side of the substrate 10 includes chemical mechanical grinding, dry etching, wet etching or other suitable methods; the method of forming the back electrode layer 65 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods. In this embodiment, the thickness of the thinned substrate is 100μm.

[0212] Specifically, by adopting the above-mentioned method for preparing the field plate structure to manufacture the field plate structure in the device, the quality of the first dielectric layer 31 between the field plate 5 and the semiconductor structure 20 is improved, and the reliability of the device is improved.

[0213] The method for preparing the semiconductor device of this embodiment improves the manufacturing process of the device and adopts the above-mentioned method for preparing the field plate structure to manufacture the field plate structure of the device, thereby improving the quality of the first dielectric layer 31 covering the upper surface of the semiconductor structure 20 and improving the reliability of the device.

[0214] Embodiment 4

[0215] This embodiment provides another method for preparing a semiconductor device, comprising the following steps:

[0216] S3-1: A field plate structure manufactured by the method for manufacturing the field plate structure described above is provided, wherein the semiconductor structure comprises a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, the semiconductor layer comprises a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure, the N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and an end of the field plate close to the drain electrical contact region is spaced a preset distance from the drain electrical contact region;

[0217] S3-2: forming a first electrode electrically connected to the source electrical contact region, a second electrode electrically connected to the drain electrical contact region, and a third electrode electrically connected to the gate structure.

[0218] Specifically, please perform step S3-1: provide a field plate structure manufactured by the preparation method of the field plate structure described above, wherein the semiconductor structure includes a gate structure and a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure and respectively spaced apart from the gate structure by a preset distance, N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and one end of the field plate close to the drain electrical contact region is spaced apart from the drain electrical contact region by a preset distance.

[0219] The following description will be given by taking a HEMT device as an example of a semiconductor device.

[0220] As an example, the semiconductor layer also includes a channel layer and a barrier layer stacked in sequence, the gate structure is located on the upper surface of the barrier layer, the source electrical contact region includes at least a barrier layer and a channel layer stacking region spaced a preset distance from the gate structure, and the drain electrical contact region includes at least a barrier layer and a channel layer stacking region spaced a preset distance from the gate structure.

[0221] Specifically, the semiconductor layer also includes a substrate, which is a process platform for forming a channel layer. The material of the substrate includes silicon, silicon germanium, glass, silicon carbide, sapphire, diamond, gallium nitride or other suitable materials.

[0222] Specifically, while ensuring device performance, the size, shape and thickness of the substrate can be selected according to actual conditions.

[0223] Specifically, the material of the channel layer includes GaN, AlGaN, InGaN or other suitable semiconductor materials; the material of the barrier layer includes In x Al y Ga 1-x-y N、Al x Ga 1-x N、In x Al 1-x N or other suitable materials.

[0224] Specifically, under the condition of ensuring the device performance, the thickness of the channel layer can be selected according to the actual situation; the thickness of the barrier layer can be selected according to the actual situation.

[0225] Specifically, when the lattice of the channel layer does not match that of the substrate, a buffer layer is formed between the channel layer and the substrate. The buffer layer is usually an insulating film layer with a smaller lattice mismatch with the channel layer. The thickness of the buffer layer can be selected according to actual conditions while ensuring the quality of the formed channel layer.

[0226] Specifically, the gate structure is usually a cap layer located on the upper surface of the barrier layer. The cap layer is made of P-type GaN, P-type AlGaN or other semiconductor materials that can completely deplete the two-dimensional electron gas at the interface between the barrier layer and the channel layer 12 below the layer.

[0227] Specifically, under the condition of ensuring the performance of the device, the gate structure may also be a metal layer located on the upper surface of the barrier layer, and a Schottky contact is formed between the metal layer and the barrier layer.

[0228] Specifically, while ensuring device performance, the distance between the source electric contact region and the gate structure can be selected according to actual conditions; the distance between the drain electric contact region and the gate structure can be selected according to actual conditions; the size, thickness and shape of the source electric contact region (i.e., the stacking region of the barrier layer and the channel layer) can be selected according to actual conditions; the size, thickness and shape of the drain electric contact region (i.e., the stacking region of the barrier layer and the channel layer) can be selected according to actual conditions.

[0229] Specifically, please perform step S3-2: forming a first electrode electrically connected to the source electrical contact region, a second electrode electrically connected to the drain electrical contact region, and a third electrode electrically connected to the gate structure.

[0230] Specifically, after forming the field plate structure and before forming the first electrode, the second electrode and the third electrode, the step of forming an interlayer dielectric layer covering the exposed upper surface of the stacked structure and the exposed surface of the field plate is also included, the first electrode penetrates the interlayer dielectric layer and is electrically connected to the source electrical contact region, the second electrode penetrates the interlayer dielectric layer and the stacked structure and is electrically connected to the drain electrical contact region, and the third electrode penetrates the interlayer dielectric layer above the gate structure and is electrically connected to the gate structure, so as to form a HEMT device.

[0231] Specifically, the first electrode is connected to the two-dimensional electron gas layer formed between the barrier layer and the channel layer, and the second electrode is connected to the two-dimensional electron gas layer between the barrier layer and the channel layer. While ensuring the performance of the device, the first electrode can be electrically connected to the barrier layer in the source contact region, or it can penetrate the barrier layer in the source electrical contact region and be electrically connected to the channel layer. The second electrode can be electrically connected to the barrier layer in the drain contact region, or it can penetrate the barrier layer in the drain electrical contact region and be electrically connected to the channel layer.

[0232] Specifically, by adopting the method for preparing the field plate structure described in the first embodiment to manufacture the field plate structure in the device, the reliability of the semiconductor device is improved.

[0233] The method for preparing a semiconductor device in this embodiment improves the reliability of the device by adopting the method for preparing the field plate structure described in the first embodiment to manufacture the field plate structure of the device.

[0234] Embodiment 5

[0235] The present embodiment provides a semiconductor device, including a field plate structure, a first electrode 6, a second electrode 7 and a third electrode. The field plate structure is manufactured by the method for preparing the field plate structure described above, wherein the semiconductor structure 20 includes a semiconductor layer 1 and a gate structure 2 located on the upper surface of the semiconductor layer 1, the semiconductor layer 1 includes a source electrical contact region 14 and a drain electrical contact region 15 located on opposite sides of the gate structure 2, N-1 steps 4 are located in a stacked structure 3 between the gate structure 2 and the drain electrical contact region 15, and one end of the field plate 5 close to the drain electrical contact region 15 is spaced a preset distance from the drain electrical contact region 15; the first electrode 6 is electrically connected to the source electrical contact region 14, the second electrode 7 is electrically connected to the drain electrical contact region 15, and the third electrode is electrically connected to the gate structure 2.

[0236] Specifically, the semiconductor device is a radio frequency LDMOS as an example. Fig.24 As shown, it is a schematic diagram of the cross-sectional structure of the semiconductor device, the semiconductor layer 1 also includes a first conductive type drift region 12, a second conductive type well region 13, and a second conductive type substrate 10 and a second conductive type epitaxial layer 11 stacked in sequence, the doping type of the source electric contact region 14 and the drain electric contact region 15 is the same as the doping type of the drift region 12, the drift region 12 is located on the upper surface layer of the epitaxial layer 11, the well region 13 is located on the upper surface layer of the epitaxial layer 11, the source electric contact region 14 is located on the upper surface layer of the well region 13, the drain electric contact region 15 is located on the upper surface layer of the drift region 12, and the gate structure 2 is located on the upper surface of the epitaxial layer 11 between the source electric contact region 14 and the drift region 12.

[0237] Specifically, the material of the substrate 10 includes silicon, silicon germanium, silicon carbide, gallium nitride or other suitable semiconductor materials; the material of the epitaxial layer 11 includes silicon, silicon germanium, silicon carbide, gallium nitride or other suitable semiconductor materials. In this embodiment, a 100 μm thick silicon layer is used as the substrate 10, and a 5 μm thick silicon layer on the upper surface of the substrate 10 is used as the epitaxial layer 11.

[0238] Specifically, an isolation structure 18 for defining an active region of the device is provided in the epitaxial layer 11. Cells of the device are formed in the active region. The structure, size and shape of the isolation structure 18 can be selected according to actual conditions while ensuring device performance.

[0239] Specifically, the semiconductor layer 1 is also provided with a first contact region 16 of the second conductive type located in the active region of the device. The doping concentration of the first contact region 16 is greater than the doping concentration of the well region 13 and the first contact region 16 penetrates the epitaxial layer 11. The first contact region 16 can be adjacent to the side wall of the well region 13 away from the drift region 12, or can be spaced a preset distance from the side wall of the well region 13 away from the drift region 12.

[0240] Specifically, the contact type between the first contact region 16 and the first electrode 6 is an ohmic contact. Under the condition of ensuring the device performance, the size, doping concentration and thickness of the first contact region 16 can be selected according to the actual situation. The thickness here refers to the distance between the upper surface and the bottom surface of the first contact region 16.

[0241] Specifically, the drift region 12 is used to ensure the withstand voltage of the device, and the well region 13 is used to adjust the threshold voltage of the device. The drift region 12 can be spaced apart from the well region 13, or can be adjacent to the well region 13. Under the condition of ensuring the performance of the device, the size, shape, doping concentration and thickness of the drift region 12 can be selected according to actual conditions; the size, shape, doping concentration and thickness of the well region 13 can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the drift region and the well region and the upper surface thereof.

[0242] Specifically, the contact type between the source electrical contact region 14 and the first electrode 6 is an ohmic contact, and the source electrical contact region 14 is spaced apart from the sidewall of the well region 13 close to the drift region 12 by a preset distance. Under the condition of ensuring the device performance, the doping concentration, size, thickness of the source electrical contact region 14 and the distance between the sidewall of the well region 13 close to the drift region 12 can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the source electrical contact region 14 and the upper surface of the source electrical contact region 14.

[0243] Specifically, the contact type between the drain region 15 and the second electrode 7 is an ohmic contact, and the drain electrical contact region 15 is spaced a preset distance from the sidewall of the drift region 12 close to the well region 13. Under the condition of ensuring the device performance, the doping concentration, size, thickness of the drain electrical contact region 15 and the distance between the sidewall of the drift region 12 close to the well region can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the drain electrical contact region 15 and the upper surface of the drain electrical contact region 15.

[0244] Specifically, the semiconductor layer 1 is further provided with a second conductive type second contact region 17 located on the upper surface of the well region 13 and adjacent to the side wall of the source electrical contact region 14 away from the drift region 12. The contact between the second contact region 17 and the first electrode 6 is an ohmic contact. When the first contact region 16 is adjacent to the side wall of the well region 13 away from the drift region, the first contact region 16 can be adjacent to the side wall of the second contact region 17 away from the source electrical contact region 14, or can be spaced from the second contact region 17 by a preset distance. While ensuring the performance of the device, the size, shape, thickness and doping concentration of the second contact region 17 can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the second contact region 17 and the upper surface of the second contact region 17.

[0245] Specifically, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 stacked in sequence, the size of the gate dielectric layer 21 is not smaller than the size of the gate conductive layer 22, the gate conductive layer 22 is located above the area between the source electrical contact region 14 and the drift region 12, and the gate conductive layer 22 extends to above the source electrical contact region 14 and the drift region 12 at both ends in the direction from the source electrical contact region 14 to the drain electrical contact region 15, respectively.

[0246] Specifically, the material of the gate dielectric layer 21 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials; the material of the gate conductive layer 22 includes polysilicon or other suitable conductive materials; the thickness of the gate dielectric layer 21 can be selected according to actual conditions while ensuring the performance of the device; the thickness of the gate conductive layer 22 can be selected according to actual conditions. Generally, the thickness of the gate dielectric layer 21 is between 10nm and 50nm, and generally, the thickness of the gate conductive layer 22 is between 100nm and 500nm. In this embodiment, a silicon oxide layer with a thickness of 30nm is used as the gate dielectric layer 21, and a N-type doped polysilicon layer with a thickness of 300nm is used as the gate conductive layer 22.

[0247] Specifically, the semiconductor structure 20 also includes a first contact layer 23, a second contact layer 24 and a third contact layer 25. The first contact layer 23 covers the upper surfaces of the source electrical contact region 14, the second contact region 17 and the first contact region 16. The second contact layer 25 covers the upper surface of the drain electrical contact region 15. The third contact layer 25 covers the upper surface of the gate conductive layer 22. The first contact layer 23 is used to reduce the contact resistance between the first electrode 6 and the source electrical contact region 14, the second contact region 17 and the first contact region 16. The second contact layer 24 is used to reduce the contact resistance between the second electrode 7 and the drain electrical contact region 15. The third contact layer 25 is used to reduce the contact resistance between the gate conductive layer 22 and the third electrode.

[0248] Specifically, the material of the first contact layer 23 includes TiSi alloy, CoSi alloy, MoSi alloy, NiSi alloy, NiPtSi alloy, WSi alloy or other suitable metal silicide materials; the material of the second contact layer 24 includes TiSi alloy, CoSi alloy, MoSi alloy, NiSi alloy, NiPtSi alloy, WSi alloy or other suitable metal silicide materials; the material of the third contact layer 25 includes TiSi alloy, CoSi alloy, MoSi alloy, NiSi alloy, NiPtSi alloy, WSi alloy or other suitable metal silicide materials; while ensuring the performance of the device, the thickness and shape of the first contact layer 23 can be selected according to actual conditions; the thickness and shape of the second contact layer 24 can be selected according to actual conditions; the thickness and shape of the third contact layer 25 can be selected according to actual conditions. Generally, the thickness of the first contact layer 23 , the second contact layer 24 , and the third contact layer 25 is between 50 nm and 300 nm. In this embodiment, a TiSi alloy layer is used as the first contact layer 23 and the second contact layer 24 , and a WSi alloy layer with a thickness of 100 nm is used as the third contact layer 25 .

[0249] Specifically, under the condition of ensuring the device performance, the thickness of each dielectric layer in the N dielectric layers can be selected according to actual conditions.

[0250] Specifically, under the condition of ensuring the device performance, the distance between the end of the field plate 5 close to the drain electrical contact region 15 and the drain electrical contact region 15 can be selected according to actual conditions.

[0251] Specifically, the field plate 5 is made of titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials. In this embodiment, a tungsten layer is used as the field plate 5 .

[0252] Specifically, under the condition of ensuring the device performance, the thickness and size of the field plate 5 can be selected according to actual conditions.

[0253] Specifically, the device is further provided with an interlayer dielectric layer 52 covering the exposed surface of the field plate 5 and the exposed upper surface of the stacked structure 3. The material of the interlayer dielectric layer 52 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In this embodiment, a silicon oxide layer is used as the interlayer dielectric layer 52.

[0254] Specifically, under the condition of ensuring the performance of the device, the thickness of the interlayer dielectric layer 52 can be selected according to the actual situation. In this embodiment, the thickness of the interlayer dielectric layer 52 is 3 μm.

[0255] Specifically, the interlayer dielectric layer 52 is also provided with a first contact hole, a second contact hole and a third contact hole penetrating the interlayer dielectric layer. The bottom surface of the first contact hole exposes the first contact layer 23 and the field plate 5, the bottom surface of the second contact hole exposes the second contact layer 24, and the bottom surface of the third contact hole exposes the third contact layer 25.

[0256] Specifically, the first electrode 6 includes a first plug 61 filling the first contact hole and a first interconnection layer 62 electrically connecting the first plugs 61, the second electrode 7 includes a second plug 71 filling the second contact hole and a second interconnection layer 72 interconnecting the second plug 71, the third electrode includes a third plug filling the third contact hole and a third interconnection layer interconnecting the third plug, the material of the first plug 61 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the second plug 71 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials. The material of the third plug includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the first interconnection layer 62 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, copper-aluminum alloy or other suitable conductive materials; the material of the second interconnection layer 72 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, copper-aluminum alloy or other suitable conductive materials; the material of the third interconnection layer includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, copper-aluminum alloy or other suitable conductive materials. In this embodiment, tungsten plugs are used as the first plug 61, the second plug 71 and the third plug, and a copper-aluminum alloy layer with a thickness of 3μm is used as the first interconnection layer 62, the second interconnection layer 72 and the third interconnection layer.

[0257] Specifically, the upper surface of the interlayer dielectric layer 52 is also provided with an insulating layer 8 and a first lead-out hole, a second lead-out hole and a third lead-out hole penetrating the insulating layer 8. The insulating layer 8 covers the exposed surfaces of the first electrode 6, the second electrode 7 and the third electrode and the upper surface of the interlayer dielectric layer 52. The bottom surface of the first lead-out hole exposes the first interconnection layer 62, the bottom surface of the second lead-out hole exposes the second interconnection layer 72, and the bottom surface of the third lead-out hole exposes the third interconnection layer.

[0258] Specifically, the material of the insulating layer 8 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In this embodiment, a silicon oxide layer is used as the insulating layer 8.

[0259] Specifically, under the condition of ensuring the performance of the device, the thickness of the insulating layer 8 can be selected according to the actual situation; the opening size and shape of the first lead-out hole can be selected according to the actual situation; the opening size and shape of the second lead-out hole can be selected according to the actual situation; the opening size and shape of the third lead-out hole can be selected according to the actual situation. In this embodiment, the thickness of the insulating layer 8 is 3 μm, where the thickness refers to the distance between the upper surface of each interconnection layer and the upper surface of the insulating layer 8.

[0260] Specifically, the device is also provided with a fourth plug 63 filling the first contact hole, a fifth plug 73 filling the second lead-out hole, a sixth plug filling the third lead-out hole, a first soldering pad 64 located on the upper surface of the insulating layer 8 and electrically connected to the fourth plug 63, a third soldering pad located on the upper surface of the insulating layer 8 and electrically connected to the sixth plug, and a second soldering pad 74 located on the upper surface of the insulating layer 8 and electrically connected to the fifth plug 73, wherein the material of each soldering pad is the same as the material of each interconnection layer, and the material of the fourth to sixth plugs is the same as the material of the first to third plugs, which will not be repeated here.

[0261] Specifically, the device is further provided with a back electrode layer 65 covering the back of the substrate 10 and a passivation layer 9 covering each pad and the upper surface of the insulating layer 8. The material of the passivation layer 9 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable materials; the material of the back electrode layer 65 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials. In this embodiment, a composite film layer structure consisting of a 300nm silicon oxide layer and an 800nm ​​silicon nitride layer is used as the passivation layer 9, and a Ti / Ni / Ag layer is used as the back electrode layer 65.

[0262] Specifically, by improving the structure of the device, a high etching selectivity ratio is achieved between two adjacent dielectric layers in the stacked structure 3 covering the semiconductor structure 20, thereby improving the controllability of the process and the quality of the first dielectric layer 31 in the stacked structure 2, thereby improving the reliability of the device.

[0263] The semiconductor device of this embodiment improves the structure of the device so that there is a high etching selectivity ratio between two adjacent dielectric layers in the stacked structure 3 covering the semiconductor structure 20, thereby improving the controllability of the process and the quality of the first dielectric layer 31 in the stacked structure and improving the reliability of the device.

[0264] In summary, the field plate structure and preparation method, semiconductor device and preparation method of the present invention improve the manufacturing process of the field plate structure to form a stacked structure on the upper surface of the semiconductor structure. The stacked structure includes N dielectric layers stacked in sequence, and there is a high etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers, so that in the process of forming the step, the next dielectric layer is the etching stop layer of the previous dielectric layer, which improves the controllability of the process, avoids damaging the first dielectric layer when forming the step, ensures the quality of the first dielectric layer covering the semiconductor structure, and improves the uniformity and reliability of the device; because the field plate covers N-1 steps and part of the upper surface of the Nth dielectric layer, the field plate covering the step formed by etching the field plate material layer once can be equivalent to the electric field suppression effect of multiple field plate layers, which reduces the cost and is convenient for large-scale mass production. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0265] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a field plate structure, characterized in that: The following steps are involved: A semiconductor structure is provided, and a stacked structure is formed covering an upper surface of the semiconductor structure, wherein the stacked structure comprises N dielectric layers stacked in sequence, wherein a first dielectric layer covers the upper surface of the semiconductor structure, an Nth dielectric layer covers an N-1th dielectric layer, N is greater than or equal to 2, and an etching selectivity ratio between two adjacent dielectric layers in the N dielectric layers is not less than a preset ratio; Forming N-1 steps located on the same side of the stacked structure, the NMth step exposing the NMth dielectric layer, where M is an integer less than N; A field plate is formed covering the N-1 steps and a portion of an upper surface of the Nth dielectric layer.

2. The method for preparing the field plate structure according to claim 1, characterized in that: The N-layer dielectric layer includes a first dielectric layer and a second dielectric layer alternately stacked in sequence, the material of the first dielectric layer includes silicon nitride or a silicon oxide / silicon nitride composite dielectric layer, and the second dielectric layer includes silicon oxide.

3. The method for preparing the field plate structure according to claim 1, characterized in that: The preset ratio is not less than 15:

1.

4. The method for preparing a field plate structure according to claim 1, characterized in that: The L+1th dielectric layer and the L-1th dielectric layer are made of different materials, where L is an integer greater than 1 and less than N.

5. The method for preparing a field plate structure according to claim 1, characterized in that: The size of the Qth dielectric layer revealed by the Qth step is different from the size of the Q+1th dielectric layer revealed by the Q+1th step, where Q is an integer greater than or equal to 1 and less than N-1.

6. A field plate structure, characterized in that: The field plate structure is manufactured by using the method for preparing a field plate structure according to any one of claims 1 to 5.

7. A method for preparing a semiconductor device, characterized in that: The following steps are involved: A field plate structure manufactured by the method for manufacturing a field plate structure according to any one of claims 1 to 5 is provided, wherein the semiconductor structure comprises a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, the semiconductor layer comprises a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure, the N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and an end of the field plate close to the drain electrical contact region is spaced a preset distance from the drain electrical contact region; A first electrode electrically connected to the source electrical contact region, a second electrode electrically connected to the drain electrical contact region, and a third electrode electrically connected to the gate structure are formed.

8. The method for preparing a semiconductor device according to claim 7, wherein: The semiconductor layer also includes a first conductive type drift region and a second conductive type well region. The doping type of the source electric contact region and the drain electric contact region is the same as the doping type of the drift region. The source electric contact region is located on the upper surface of the well region, the drain electric contact region is located on the upper surface of the drift region, and the gate structure is located on the upper surface of the semiconductor layer between the source electric contact region and the drift region.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: A second contact region of the second conductivity type is also formed in the semiconductor layer and is located on the upper surface of the well region. The second contact region is close to the side wall of the drift region and is adjacent to the side wall of the source contact region away from the drift region.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The semiconductor layer also includes a second conductive type substrate and a second conductive type epitaxial layer stacked in sequence, the well region and the drift region are located in the upper surface layer of the epitaxial layer, and a second conductive type first contact region is also formed in the semiconductor layer, the first contact region penetrates the epitaxial layer and extends at least to the top surface of the substrate, wherein the side surface of the first contact region is in contact with the second contact region.

11. The method for preparing a semiconductor device according to claim 7, wherein: A first contact layer and a second contact layer are also formed in the semiconductor structure. The first contact layer covers the exposed upper surface of the source electrical contact region, and the second contact layer covers the exposed upper surface of the drain electrical contact region.

12. The method for preparing a semiconductor device according to claim 7, wherein: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, and a size of a projection of the gate dielectric layer along a stacking direction of the gate dielectric layer and the gate conductive layer is not smaller than a size of a projection of the gate conductive layer along a stacking direction of the gate dielectric layer and the gate conductive layer.

13. The method for preparing a semiconductor device according to claim 7, wherein: After forming the field plate and before forming the first electrode, the second electrode and the third electrode, the step of forming an interlayer dielectric layer covering the exposed upper surface of the stacked structure and the exposed surface of the field plate is also included, the first electrode penetrates the interlayer dielectric layer and is electrically connected to the source electrical contact area, and the second electrode penetrates the interlayer dielectric layer and the stacked structure and is electrically connected to the drain electrical contact area.

14. The method for preparing a semiconductor device according to claim 7, wherein: The semiconductor layer also includes a channel layer and a barrier layer stacked in sequence, the gate structure is located on the upper surface of the barrier layer, the source electrical contact region at least includes a stacked region of the barrier layer and the channel layer spaced a preset distance from the gate structure, and the drain electrical contact region at least includes a stacked region of the barrier layer and the channel layer spaced a preset distance from the gate structure.

15. A semiconductor device, characterized in that: include: A field plate structure manufactured by the method for preparing a field plate structure according to any one of claims 1 to 5, wherein the semiconductor structure comprises a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, the semiconductor layer comprises a source electrical contact region and a drain electrical contact region located on opposite sides of the gate structure, the N-1 steps are located in the stacked structure between the gate structure and the drain electrical contact region, and an end of the field plate close to the drain electrical contact region is spaced a preset distance from the drain electrical contact region; A first electrode, a second electrode and a third electrode, wherein the first electrode is electrically connected to the source electrical contact region, the second electrode is electrically connected to the drain electrical contact region, and the third electrode is electrically connected to the gate structure.

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