CMOS device with BPR structure and preparation method thereof

Abstract

The invention discloses a CMOS device with a BPR structure and a preparation method of the CMOS device, the BPR technology is applied to a planar CMOS device, the CMOS device with the BPR structure comprises a substrate, a well region located on the upper surface of the substrate, a grid located on the upper surface of the well region, shallow trench isolation regions located at the two ends of the well region, and a source and a drain located in the well region, the dielectric layer is positioned above the well region; a first metal layer is arranged on the top of the dielectric layer, and a BPR groove extending into the substrate from the lower surface of the first metal layer through the shallow groove isolation area is arranged in the dielectric layer. According to the invention, the power rail is embedded in the substrate so as to reduce the voltage drop caused by the subsequent interconnection resistance, and the power rail structure is compatible with the integrated circuit process and adapts to the development requirements of the high-density power supply network of the integrated circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a CMOS device with a BPR structure and a preparation method thereof. Background Art

[0002] In the complementary metal oxide semiconductor (CMOS) process, the back end of line (BEOL) interconnection process plays a vital role in achieving high-performance logic and memory. Due to the miniaturization of transistor size, the continuous reduction of transistors and wires has led to a significant increase in interconnect resistance and voltage drop (IR drop). Traditionally, the front-end power supply network (FSPDN) and signal network layout are achieved through front-end wafer metallization. In order to achieve further area scaling, a new method of burying power rails (such as VDD and VSS) into the substrate, namely the buried power rail technology (BPR), and the backside power delivery network technology (BSPDN) is proposed to transfer the power supply network from the front end to the back of the wafer, eliminating the competition between the power supply power and signal networks, and providing excellent area scaling, higher module utilization and higher performance.

[0003] At present, the embedded power rail technology is only used in advanced process nodes, such as FinField Effect Transistor (FinFET) and Nanosheet Field Effect Transistor, to alleviate the increase in interconnection resistance and voltage drop caused by size reduction and relieve metal wiring pressure. It has not yet been put into use in planar devices. Summary of the invention

[0004] The object of the present invention is to provide a CMOS device and a method for preparing the same. The technology introduces a BPR structure and is implemented based on a planar process to improve device performance and optimize interconnect metal layout.

[0005] In a first aspect of the present invention, a CMOS device having a BPR structure is provided, comprising: A substrate, a well region located on the upper surface of the substrate, a gate located on the upper surface of the well region, and sidewall structures located at both ends of the gate; A shallow trench isolation region, wherein the shallow trench isolation region is located at two ends of the well region; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located inside the well region and are respectively arranged on both sides of the gate electrode; A dielectric layer, the dielectric layer is arranged above the well region; a first metal layer is arranged on the top of the dielectric layer, a BPR trench extending from the lower surface of the first metal layer through the shallow trench isolation region to the inside of the substrate, and a contact hole extending from the lower surface of the first metal layer to the upper surface of the source and the drain is arranged inside the dielectric layer; A front-end metal layer is arranged on an upper surface of the first metal layer.

[0006] Furthermore, the BPR trench and the contact hole have the same structure, both comprising a barrier layer and a filling metal located inside the barrier layer.

[0007] Furthermore, the BPR trench barrier layer material can generally be titanium / titanium nitride, tantalum / tantalum nitride, etc., and the filling metal can generally be copper, tungsten, ruthenium, molybdenum, etc.; preferably, tungsten metal.

[0008] Furthermore, the BPR trench is in an inverted trapezoidal shape and embedded in the shallow trench isolation region.

[0009] Furthermore, the diameter of the BPR trench is smaller than the diameter of the shallow trench isolation region.

[0010] Furthermore, the BPR groove is connected to the front-end metal layer through the first metal layer to form a power supply network. The front-end metal layer includes at least one metal layer, and a metal through hole is provided between the front-end metal layer and the first metal layer.

[0011] Furthermore, the well region includes an n-well and a p-well.

[0012] In a second aspect of the present invention, a method for preparing a CMOS device having a BPR structure is provided, comprising: 1) Selectively etch a trench on the substrate and fill the trench area with an oxide layer to form a shallow trench isolation area; 2) Perform ion implantation on the substrate to form a well region; 3) Deposit a gate oxide layer and polysilicon on the well region, etch to form a gate, then deposit silicon nitride on the surface, perform anisotropic etching, and form sidewall structures on both sides of the gate; 4) Perform ion implantation on the well region to form a source and a drain; 5) Etching a BPR trench in the shallow trench isolation region, and filling the etched BPR trench with a barrier layer and a metal material to form a BPR trench; 6) The contact holes are patterned and etched, the barrier layer and metal are filled, and then chemical mechanical polishing is performed to make the top surface of the contact holes and the BPR trench flush; 7) Fill the dielectric layer, form the first metal layer on the BPR trench and contact hole, and fill the barrier layer and metal; 8) Metal vias and front-end metal layers are continuously formed on the first metal layer to complete the post-interconnection process.

[0013] The above steps 1) to 4) are the front-end process flow of traditional CMOS planar devices. The BPR structure should be formed after the front-end process is completed to avoid contamination of the front-end process by metal materials.

[0014] In the above step 5), the diameter of the etched BPR groove should be smaller than the diameter of the groove area, and the BPR groove should be etched into the silicon substrate to form a BPR groove with a high aspect ratio.

[0015] In the above step 6), the material of the barrier layer may be titanium / titanium nitride, and the metal may be tungsten; in the above step 7), the material of the barrier layer may be tantalum / tantalum nitride, and the metal may be copper.

[0016] In the above step 7), a metal interconnection layout should be designed separately for the BPR area to form a power supply network.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The method for forming a BPR structure proposed in the present invention is suitable for CMOS planar device technology and has strong compatibility with traditional processes. It provides a feasible technical path for introducing the BPR structure into planar devices, optimizes the interconnect metal layout, and reduces IRdrop (voltage drop) and interconnect RC delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a CMOS device with a BPR structure of the present invention; Figure 2 The present invention can be used in Figure 1 A schematic diagram of a mask layout in an embodiment of the method is shown.

[0019] Numbers in the figure: 1-substrate; 2-shallow trench isolation region; 3-well region; 4-gate; 5-sidewall structure; 6-source; 7-drain; 8-contact hole; 9-BPR trench; 10-dielectric layer; 11-first metal layer; 12-metal through hole; 13-second metal layer; 14-diffusion layer. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific examples and with reference to the accompanying drawings. It should be noted that the directional terms mentioned in the examples, such as "upper", "lower", "middle", "left", "right", "front", "back", etc., are only referenced to the directions of the accompanying drawings. Therefore, the directions used are only used for illustration and are not used to limit the scope of protection of the present invention.

[0021] The present invention provides a CMOS device with a BPR structure, such as Figure 1 As shown, it includes: substrate 1, shallow trench isolation region 2, well region 3, gate 4, sidewall structure 5, source 6, drain 7, contact hole 8, BPR trench 9, dielectric layer 10, first metal layer 11, metal through hole 12, front metal layer. Shallow trench isolation region 2 is formed on substrate 1; sidewall structure 5 is formed on both sides of gate; source 6 and drain 7 are formed on both sides of gate 4; contact hole 8 is formed on gate 4, source 6 and drain 7; BPR trench 9 is formed in shallow trench isolation region 2; the front metal layer includes at least one metal layer, in this embodiment, the front metal layer is second metal layer 13; first metal layer 11, metal through hole 12 and second metal layer 13 are formed in dielectric layer 10.

[0022] The material of substrate 1 is usually p-type doped silicon. A shallow trench isolation (STI) region 2 is etched on substrate 1 through a mask pattern, and a thin oxide layer is formed by annealing to repair the corners of the shallow trench. The STI region is filled with high-density oxide to isolate the well 3. Well 3 is formed by ion implantation. The left side is formed by n-type implantation to form an n-well. The substrate, n-well, source, drain, and gate constitute the first transistor, and the first transistor is a PMOS device; the right side is formed by p-type implantation to form a p-well. The substrate, p-well, source, drain, and gate constitute the second transistor, and the second transistor is an NMOS device; the first transistor and the second transistor form a simple inverter. The gate-first process is adopted to form a gate oxide layer and a gate 4 on the well region 3 by patterned deposition and etching, wherein the gate oxide layer material is usually silicon dioxide, and the gate material is usually polysilicon. Ion implantation is performed on the well 3 to form a lightly doped drain (LDD). P-type ions are implanted into the PMOS device and n-type ions are implanted into the NMOS device. This technology is usually used for CMOS devices below the 180nm technology node. Silicon nitride is deposited and anisotropically etched to form a gate sidewall structure 5 to reduce the impact of the short channel effect. Ion implantation is performed on the well 3 to form a source 6 and a drain 7.

[0023] A dielectric layer 10 is deposited on the aforementioned device. The dielectric layer is usually silicon dioxide, or a low-k dielectric material (Low-kMaterial), such as organic silicon glass (SiCOH), etc., to reduce the impact of the metal layer RC delay. The dielectric layer is etched through a pre-designed BPR mask pattern, usually by dry etching. The BPR structure is usually a contact hole or trench with a high aspect ratio. The bottom of the BPR needs to be buried in the substrate 1, which is to improve the power transmission efficiency. A barrier layer is deposited on the BPR trench. This step is to prevent the filling metal from diffusing into the transistor. Fill the BPR trench with metal material. In some embodiments, the BPR trench barrier layer material can generally be titanium (Titanium) / titanium nitride (Titanium Nitride), tantalum (Tantalum) / tantalum nitride (Tantalum Mononitride), etc., and the filled metal material can generally be copper (Copper), tungsten (Tungsten), ruthenium (Ruthenium), molybdenum (Molybdenum), etc. Among them, the use of metal tungsten material to fill the BPR trench is more compatible with the planar device contact hole formation process.

[0024] Next, a contact hole 8 is patterned and etched on the aforementioned device. The contact hole 8 connects the gate 4, the source 6 and the drain 7. The contact hole 8 usually uses titanium / titanium nitride as a barrier layer and metal tungsten as a filling material. Excess metal materials are removed by a planarization process such as chemical mechanical polishing (CMP), so that the top surfaces of the contact hole 8, the BPR trench 9 and the dielectric layer 10 are flush after the planarization process.

[0025] Next, the aforementioned device is subjected to a back-end interconnection process to complete the metal wiring layout. A dielectric layer 10 is deposited on the aforementioned device. The dielectric layer 10 is patterned and etched, and a thin layer of tantalum / tantalum nitride is deposited on the etched groove as a barrier layer. This step is to prevent the filling metal from diffusing into the dielectric layer 10 and the substrate. Copper is used as the filling metal material to fill the first metal layer 11. A connecting metal is designed above the BPR groove 9 and the contact hole 8. The BPR groove is electrically connected through the first metal layer and the contact hole 8 to supply power to the transistor source 6. After the first metal layer is deposited, the dual-Damascene process is used to etch and deposit the metal through hole 12 and the second metal layer 13 to complete the second metal layer deposition. The same method is used for the subsequent front-end metal layer to complete the back-end interconnection process.

[0026] Figure 2This is an example diagram of a mask layout of the above embodiment. The mask layout is an inverter unit, which is composed of a first transistor and a second transistor to form an inverter. The source of the first transistor is connected to the left BPR structure, the source of the second transistor is connected to the right BPR structure, the drains of the first and second transistors are connected through a metal layer, and the gates of the first and second transistors are connected through polysilicon. Among them, the diffusion layer 14 is used to define the position of the shallow trench isolation region and the ion implantation diffusion region. The area outside the diffusion layer 14 is the shallow trench isolation region 2, and the source and drain are formed in the diffusion layer 14.

[0027] In some embodiments, the BPR trench is connected to the first metal layer to supply power to the transistor, and the BPR trench is connected to the front-end metal layer to form a front-end power supply network.

[0028] In some embodiments, the BPR trench is connected to the first metal layer to supply power to the transistor. After completing the back process, the wafer is flipped and thinned, and a through silicon via (TSV) is etched under the BPR. The TSV is connected to the first metal layer on the back, and back metallization is performed to form a back power supply network.

[0029] It is easy for those skilled in the art to understand that the above is only an embodiment of the present invention and is not intended to limit the present invention. Any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection scope of the present invention.

Claims

1. A CMOS device with a BPR structure, characterized in that: include: A substrate, a well region located on the upper surface of the substrate, a gate located on the upper surface of the well region, and sidewall structures located at both ends of the gate; a diffusion layer is provided inside the well region; A shallow trench isolation region, wherein the shallow trench isolation region is located at two ends of the well region and is not located inside the diffusion layer; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located inside the diffusion layer and are respectively arranged on both sides of the gate electrode; A dielectric layer, the dielectric layer is arranged above the well region; a first metal layer is arranged on the top of the dielectric layer, a BPR trench extending from the lower surface of the first metal layer through the shallow trench isolation region to the inside of the substrate, and a contact hole extending from the lower surface of the first metal layer to the upper surface of the source and the drain is arranged inside the dielectric layer; A front-end metal layer is arranged on an upper surface of the first metal layer.

2. The CMOS device with a BPR structure according to claim 1, characterized in that: The BPR trench and the contact hole have the same structure, both including a barrier layer and a filling metal located inside the barrier layer.

3. The CMOS device with a BPR structure according to claim 1, characterized in that: The BPR trench is in an inverted trapezoidal shape and embedded in the shallow trench isolation region.

4. The CMOS device with a BPR structure according to claim 3, characterized in that: The diameter of the BPR trench is smaller than the diameter of the shallow trench isolation region.

5. The CMOS device with a BPR structure according to claim 1, characterized in that: The well region includes an n-well and a p-well.

6. The CMOS device with a BPR structure according to claim 1, characterized in that: The BPR groove is connected to the front-end metal layer through the first metal layer to form a power supply network.

7. The CMOS device with a BPR structure according to claim 6, characterized in that: The front-end metal layer includes at least one metal layer.

8. The CMOS device with a BPR structure according to claim 7, characterized in that: A metal through hole is provided between the front-end metal layer and the first metal layer.

9. A method for preparing a CMOS device having a BPR structure according to any one of claims 1 to 8, characterized in that: The preparation method comprises the following steps: Selectively etching a trench on the substrate, filling the trench area with an oxide layer to form a shallow trench isolation region; Performing ion implantation on the substrate to form a well region; Depositing a gate oxide layer and polysilicon on the well region, etching to form a gate, then depositing silicon nitride on the surface, performing anisotropic etching, and forming a sidewall structure on both sides of the gate; Performing ion implantation on the well region to form a source and a drain; Etching a BPR trench in the shallow trench isolation region, and filling the etched BPR trench with a barrier layer and a metal material to form a BPR trench; The contact hole is patterned and etched, and then filled with a barrier layer and a fill metal, followed by chemical mechanical polishing, so that the top surface of the contact hole and the BPR trench are flush; Fill the dielectric layer, form a first metal layer on the BPR trench and contact hole, and fill the barrier layer and metal; A metal via and a front-end metal layer are continuously formed on the formed first metal layer to complete a post-interconnection process.

Images