Test system and method based on 2.5 D integration
By adopting a 2.5D integration-based test system in a multi-core integrated system, using TAP state machine and other register components, the problems of increased test signal transmission and complexity are solved, and faster and more efficient testing is achieved.
Patent Information
- Application Number
- CN202411703257.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-02-25
AI Technical Summary
The prior art test signal transmission and increased complexity in multi-core integrated systems lead to low testing efficiency and high cost.
Using a 2.5D integrated test system, the TAP state machine, test shell instruction register WIR, test configuration register WCR and test interface circuit are used to realize efficient transmission of test signals and rapid testing of core particles.
It reduces the design complexity, hardware resource cost and maintenance difficulty of the test system, and improves the testing speed and efficiency.
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Figure CN119511037A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor testing and packaging technology, and in particular to a testing system and method based on 2.5D integration. Background Art
[0002] With the rapid development of multi-dimensional packaging technology, multi-chip integrated systems with complex stacking structures such as 2.5D, 3D, and 5.5D have gradually emerged. Due to the complex stacking structure of these multi-chip integrated systems, it is difficult to test their internal signals, making it difficult to ensure the performance and reliability of the chips during manufacturing and subsequent use.
[0003] In order to solve the internal signal testing problem of multi-chip integrated systems, the IEEE 1838 standard defines a DFT architecture for testing stacked chips. This architecture defines standard test interfaces, such as test access ports (TAP) and secondary test access ports (STAP), and forms a cascade structure between stacked chips, so that test signals can be transmitted between stacked chips, thereby realizing the testing of each chip.
[0004] However, although the IEEE 1838 standard solves the test problem of stacked cores to a certain extent, the standard requires adding a TAP state machine to each core, which leads to a significant increase in test complexity. Summary of the invention
[0005] Based on the above problems, the present application provides a test system and method based on 2.5D integration, which can speed up the test and improve the test efficiency while reducing the design complexity, hardware resource cost and maintenance difficulty of the test system.
[0006] The embodiments of the present application disclose the following technical solutions:
[0007] In a first aspect, the present application discloses a test system based on 2.5D integration, the system comprising: a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit;
[0008] The TAP state machine is used to generate a test shell serial control WSC signal; send the WSC signal to the WIR;
[0009] The WIR is used to generate a register selection signal according to the WSC signal; when the register selection signal indicates that the WCR is selected, the test data input TDI signal is sent to the WCR;
[0010] The WCR is used to generate a selection SEL signal by analyzing the TDI signal, wherein the SEL signal is used to indicate a chip to be tested; and send the SEL signal to the interface test circuit to instruct the interface test circuit to test the chip to be tested.
[0011] Optionally, the WCR is also used to: generate a SEL signal and a Jump signal by parsing the TDI signal, the SEL signal and the Jump signal together indicating skipping the test of the core particle to be tested; and send the SEL signal and the Jump signal to the interface test circuit to instruct the interface test circuit to test the next layer of core particles of the core particle to be tested.
[0012] Optionally, the system further comprises a test shell bypass register WBY;
[0013] The WIR is further configured to send the TDI signal to the WBY when the register selection signal indicates that the WBY is selected;
[0014] The WBY is used to send the TDI signal to the next level of the current core particle.
[0015] Optionally, the system further comprises a test shell boundary register WBR;
[0016] The WIR is specifically used to generate a scan test mode signal and a register selection signal according to the WSC signal; when the register selection signal indicates that the WBR is selected, the TDI signal and the scan test mode signal are sent to the WBR;
[0017] The WBR is used to perform a scan test on the current chip according to the test type corresponding to the scan test mode signal.
[0018] Optionally, the test type includes at least one of a serial internal scan test, a serial external scan test, a parallel internal scan test and a parallel external scan test.
[0019] Optionally, the system further comprises a memory self-test circuit MBIST;
[0020] The WIR is also used for sending the TDI signal to the MBIST when the register selection signal indicates that the MBIST is selected;
[0021] The MBIST is used to perform an MBIST test on the current chip according to the TDI signal.
[0022] Optionally, the MBIST is also used to obtain a test result of the MBIST test performed on the current chip; and send the test result to a test device via a test data output signal.
[0023] In a second aspect, the present application discloses a test method based on 2.5D integration, the method is applied to a test system based on 2.5D integration, the test system based on 2.5D integration includes a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit; the method includes:
[0024] The TAP state machine generates a test shell serial control WSC signal;
[0025] The TAP state machine sends the WSC signal to the WIR;
[0026] The WIR generates a register selection signal according to the WSC signal;
[0027] When the register selection signal indicates that the WCR is selected, the WIR sends a test data input TDI signal to the WCR;
[0028] The WCR generates a selection SEL signal by analyzing the TDI signal, and the SEL signal is used to indicate a core particle to be tested;
[0029] The WCR sends the SEL signal to the interface test circuit to instruct the interface test circuit to test the chip to be tested.
[0030] Optionally, the method further comprises:
[0031] The WCR generates a SEL signal and a Jump signal by analyzing the TDI signal, wherein the SEL signal and the Jump signal together indicate to skip testing the chip to be tested;
[0032] The WCR sends the SEL signal and the Jump signal to the interface test circuit to instruct the interface test circuit to test the next layer of the chip to be tested.
[0033] Optionally, the system further comprises a test shell bypass register WBY; the method further comprises:
[0034] When the register selection signal indicates that the WBY is selected, the WIR sends the TDI signal to the WBY;
[0035] The WIR sends the TDI signal to a next-level chiplet of the current chiplet.
[0036] Compared with the prior art, this application has the following beneficial effects:
[0037] The embodiment of the present application provides a test system and method based on 2.5D integration, the system including: a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit. Among them, the TAP state machine is used to generate a WSC signal; send the WSC signal to the WIR; the WIR is used to generate a register selection signal according to the WSC signal; when the register selection signal indicates the selection of WCR, the TDI signal is sent to the WCR; the WCR is used to generate a SEL signal by parsing the TDI signal, and the SEL signal is used to indicate the core to be tested; the SEL signal is sent to the interface test circuit to instruct the interface test circuit to test the core to be tested. The present application only requires one TAP state machine, instead of one TAP state machine for each core, which not only reduces the design complexity, hardware resource cost and maintenance difficulty of the test system, but also can test the core to be tested more quickly and accurately, thereby speeding up the test speed and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0039] Figure 1 A schematic diagram of a 2.5D integrated test system provided in an embodiment of the present application;
[0040] Figure 2A A schematic diagram of an active 2.5D integrated test system provided in an embodiment of the present application;
[0041] Figure 2B A schematic diagram of a passive 2.5D integrated test system provided in an embodiment of the present application;
[0042] Figure 3 A schematic diagram of a test interface circuit provided in an embodiment of the present application;
[0043] Figure 4 A flowchart of a testing method based on 2.5D integration provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] First, the technical terms involved in this application are explained:
[0045] Chips are pre-fabricated chips with specific functions that can be combined and integrated. They are designed for use in chiplet-based architectures, where multiple chiplets are connected together to create a single complex integrated circuit.
[0046] The IEEE 1838 protocol refers to the DFT test protocol proposed in 2019, which provides a universal solution for the testing of 3D chips, provides a standardized test port interface for 3D stacked devices, supports plug-and-play integration, and provides test access across multiple cores.
[0047] As described above, in order to solve the problem that it is difficult to directly control and observe the internal signals of multiple cores after stacking, the IEEE 1838 standard defines a design for testability (internal signal DFT) architecture for testing stacked cores. This architecture defines standard test interfaces, such as test access ports (TAP) and secondary test access ports (STAP), and forms a cascade structure between stacked cores, so that test signals and control signals can be transmitted between stacked cores, thereby realizing the testing of each core.
[0048] Although the IEEE 1838 standard solves the test problem of stacked cores to a certain extent, it requires adding a TAP state machine to each core, which is used to communicate with external test equipment, control the test process and transmit test data. However, adding a TAP state machine leads to a significant increase in test complexity. At the same time, the need for an additional TAP state machine also increases test cost and time.
[0049] After research, the inventor provides a test system and method based on 2.5D integration, which includes: a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit. Among them, the TAP state machine is used to generate a WSC signal; send the WSC signal to the WIR; the WIR is used to generate a register selection signal according to the WSC signal; when the register selection signal indicates the selection of WCR, the TDI signal is sent to the WCR; the WCR is used to generate a SEL signal by parsing the TDI signal, and the SEL signal is used to indicate the core to be tested; the SEL signal is sent to the interface test circuit to instruct the interface test circuit to test the core to be tested. The present application only requires one TAP state machine, instead of one TAP state machine for each core, which not only reduces the design complexity, hardware resource cost and maintenance difficulty of the test system, but also can test the core to be tested more quickly and accurately, thereby speeding up the test speed and improving the test efficiency.
[0050] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0051] See also Figure 1 , which is a schematic diagram of a test system based on 2.5D integration provided in an embodiment of the present application.
[0052] The 2.5D integration-based test system (hereinafter referred to as the test system) meets the test requirements of active 2.5D integration and passive 2.5D integration testability design architecture, and can perform efficient and accurate testing on multiple cores integrated on an interposer.
[0053] See also Figure 2A , which is a schematic diagram of an active 2.5D integrated test system provided in an embodiment of the present application. Active 2.5D integration means that the interposer not only has connecting wires, but also includes circuit control parts, such as test access port (TAP) control circuits and test interface circuits. These circuit control parts can realize the transmission and control of test signals, thereby improving the efficiency and accuracy of the test. Specifically, Figure 2A As shown, the test system receives the test signal through the TAP control circuit and passes it to the test interface circuit. The test interface circuit is responsible for distributing the test signal to each core particle and receiving the test response from the core particle. In this way, the test system can realize parallel testing of multiple core particles and improve the test efficiency.
[0054] See also Figure 2B , which is a schematic diagram of a passive 2.5D integrated test system provided in an embodiment of the present application. Passive 2.5D integration means that there are only connection lines in the interposer, and no circuit control part. The main function of the interposer is to provide physical connection, interconnect multiple core particles together, and transmit signals between core particles through metal wires or other conductive materials. Figure 2B As shown in the figure, in the passive 2.5D integrated test system, the test signal is directly connected to the connection line of the interposer through the external test equipment. The test signal is transmitted to each chip through the connection line, and the chip processes the test signal and generates a test response. The test response is transmitted back to the test equipment through the connection line, and the test equipment analyzes and judges it.
[0055] Depend on Figure 1It can be seen that the core components of its 2.5D integrated test system include: Test Access Port (TAP) state machine, Wrapper Instruction Register (WIR), Wrapper Configuration Register (WCR) and test interface circuit. These components work together to achieve efficient and accurate testing.
[0056] The TAP state machine is the core control unit of the test system, responsible for controlling the state transition of the test process. WIR is used to store test instructions received from external test equipment, usually including test type, test parameters and other information, to guide the test interface circuit and core grain to perform specific test operations. WCR is used to store configuration information of the test system, such as test mode, test speed, etc. Figure 3 , which is a schematic diagram of a test interface circuit provided in an embodiment of the present application. The test interface circuit is an interface between the test system and the core particle. Through the test interface circuit, the external test equipment can send test signals to the circuit under test and receive test responses from the circuit under test. The test interface circuit usually includes multiple channels, each channel corresponding to a test connection of a core particle or a group of core particles.
[0057] First, the TAP state machine generates the Wrapper Scan Control (WSC) signal through the Test Mode Selection (TMS) signal. The WSC signal is a set of control signals used to manage and control the entire scan test process. These signals play a vital role inside the test shell. They can control various registers and test paths to ensure that the test process can proceed according to the predetermined steps.
[0058] Specifically, the WSC signal includes a WIR_Select signal, a WR_Capture signal, a WR_Update signal, and a WR_Shift signal.
[0059] The WIR_Select signal is used to select WIR. When the WIR_Select signal is activated, it indicates that the current operation will involve WIR. At this time, the TAP state machine sends the WSC signal to WIR.
[0060] The WR_Capture signal is obtained by ORing the Capture_DR and Capture_IR signals. Capture_DR refers to the data register capture signal, and Capture_IR refers to the instruction register capture signal. The WR_Capture signal is used to instruct the test shell to capture the current state. It is usually used at the beginning of the test to save the current test state to the register.
[0061] The WR_Update signal is obtained by ORing the Update_DR and Update_IR signals. Update_DR refers to the data register update signal, and Update_IR refers to the instruction register update signal. The WR_Update signal is used to update the state of the test shell. It is usually used at the end of the test to output the test results from the register.
[0062] The WR_Shift signal is obtained by ORing the Shift_DR and Shift_IR signals. Shift_DR refers to the data register shift signal, and Shift_IR refers to the instruction register shift signal. The WR_Shift signal is used to instruct the test shell to perform a data shift operation. During the test process, this signal is used to shift the test data from one register to another, thereby realizing data transmission and processing.
[0063] Since the test shell may contain multiple registers, after the TAP state machine sends the WSC signal to the WIR, the WIR will generate corresponding register selection signals according to the WSC signal. These register selection signals are used to instruct different registers to operate.
[0064] Specifically, if the WIR_Select signal in the WSC signal is high, the WIR will generate the wcr_wir signal, indicating that the WCR is selected for subsequent operations. When the generated wcr_wir signal is high, it means that the test data input (Test Data Input, TDI) signal needs to be sent to the WCR so that the WCR can receive and process the test data (such as setting the test mode, configuring the test parameters, etc.). Among them, the TDI signal is the test data input signal, which is used to input the test data into the test system.
[0065] Finally, after receiving the TDI signal, the WCR can first parse the TDI signal through the internal logic circuit or microprocessor, for example, extract the identification information of the core to be tested, the test type, the test parameters, etc. in the TDI signal, and then generate the corresponding control signal, such as the SEL signal, according to the parsing result. The SEL signal is a control signal containing the identification information of the core to be tested. Its main function is to indicate which core to be selected as the core to be tested by the test system. After the SEL signal is generated, the WCR will send it to the interface test circuit. The interface test circuit is a bridge between the test system and the circuit under test. It is responsible for selecting and testing the specified core to be tested according to the received control signal (such as the SEL signal). During the test process, the interface test circuit will send test data to the core to be tested and receive test results from the core. These test results will then be sent to the test system for analysis and evaluation. As a result, this process ensures that the test system can accurately select and test the target core, thereby improving the efficiency and accuracy of the test.
[0066] It should be noted that when parsing the TDI signal, the WCR can not only generate the SEL signal, but also the Jump signal. Among them, the SEL signal is used to indicate the core to be tested. When the SEL signal is activated, it contains the identification information of the core to be tested, telling the test system which core should be selected for testing. The Jump signal is used to indicate to skip the current core to be tested and select the next layer of cores for testing. The existence of the Jump signal makes the test process more flexible, and some unnecessary test steps can be skipped as needed. Then, after the SEL signal and the Jump signal are generated, the WCR will send these signals to the interface test circuit. After the interface test circuit receives the SEL signal and the Jump signal, it will test the next layer of cores of the core to be tested according to these signals. Therefore, through the Jump signal, some cores (such as cores that are known to be fault-free, do not need to be tested, or have high testing costs) can be flexibly skipped, thereby avoiding unnecessary test steps, improving test efficiency, and reducing test time.
[0067] In a specific implementation, the test system based on 2.5D integration also includes a test wrapper bypass register (WBY). WBY is a register used to implement bypass testing. Its main function is to pass the test signal directly to the next level of core particles without passing through the current core particle, thereby avoiding unnecessary testing of certain core particles and improving test efficiency.
[0068] When the register selection signal generated by WIR according to the received WSC signal is wby_wir, it means that the register selection signal indicates to select WBY, and the current operation will involve WBY. Then, WIR needs to send the TDI signal to WBY. After receiving the TDI signal, WBY directly passes it to the next level of core particles without passing through the current core particle, making the test process more flexible and efficient, and improving the efficiency and accuracy of the test.
[0069] In another specific implementation, the test system based on 2.5D integration further includes a Wrapper Boundary Register (WBR). The WBR is a register for performing scan tests, and can perform different types of scan tests on the current chip according to different scan test mode signals.
[0070] When the register selection signal generated by WIR according to the received WSC signal is wbr_wir, it means that the register selection signal indicates the selection of WBR, and the current operation will involve WBR. Then, after WIR generates the scan test mode signal and the register selection signal according to the WSC signal, it sends the TDI signal and the scan test mode signal to WBR. The scan test mode signals include the ws_intest signal, the ws_extest signal, the wp_intest signal, and the wp_extest signal. Among them, the ws_intest signal indicates that the circuit inside the current chip is subjected to a serial internal scan test mode. In this mode, the trigger or latch inside the chip is configured as a scan chain, the test vector is serially input through the scan chain, and the test result is captured. The ws_extest signal indicates that the connection between the current chip and other chip is subjected to a serial external scan test. This test mode is used to verify the correctness of the connection between chiplets and ensure that data can be correctly transmitted between different chiplets. The wp_intest signal indicates that a parallel internal scan test is performed on the circuit inside the current core. Compared with the serial internal scan test, the parallel test can input the test vector faster and capture the test results, thereby improving the test efficiency. The wp_extest signal indicates that a parallel external scan test is performed on the connection between the current core and other cores. This test mode is also used to verify the correctness of the connection between cores, but it is faster and suitable for time-sensitive test scenarios. Subsequently, WBY performs a scan test according to the test type corresponding to the scan test mode signal. Therefore, by introducing WBR, the test system can flexibly select different scan test modes according to different test requirements and scenarios. This not only improves the flexibility of the test, but also significantly improves the test coverage. Because different test modes can test different parts and connections of the circuit, the comprehensiveness of the test is ensured. In addition, WBR also supports multiple scan test modes, which enables the test system to detect and locate faults more efficiently. For example, in the serial internal scan test mode, the test system can check the triggers or latches inside the core one by one, making it easier to locate the fault point. In the parallel test mode, the test system can check multiple elements at the same time, thereby speeding up the test.
[0071] In another specific implementation, the test system based on 2.5D integration further includes a memory built-in self-test circuit (MBIST). MBIST can automatically execute a series of predefined test operations to detect whether there is a fault in the memory.
[0072] When the register selection signal generated by WIR according to the received WSC signal is mbist_wir, it means that the register selection signal indicates that MBIST is selected and the current operation will involve MBIST. Then, WIR needs to send the TDI signal to MBIST. MBIST will perform MBIST test on the current chip according to the TDI signal. Specifically, the MBIST test circuit automatically writes a series of predefined test patterns into the memory. These test patterns are usually carefully designed to cover various possible failure conditions, such as bit flips, address decoding errors, data path failures, etc. By writing these test patterns, it can be ensured that all parts of the memory are fully tested. After writing the test pattern, the MBIST test circuit reads the written data and verifies whether it is consistent with the expected test pattern. This step is the key to detecting memory failures. If the read data does not match the expected data, it means that the memory may be faulty. The MBIST test circuit records these inconsistent data and generates corresponding test results.
[0073] Therefore, by introducing MBIST, the test system can automatically perform memory testing without the involvement of external test equipment. This not only simplifies the test process, but also improves the accuracy and efficiency of the test. Because the MBIST test circuit is integrated inside the chip, it can access the memory more directly, thereby detecting faults more accurately.
[0074] It should be noted that, after obtaining the test result (such as including information such as fault address and fault type) of the current core grain, MBIST can also send the test result to the test equipment through the test data output signal (Test Data Output, TDO). The test equipment can locate and analyze the faults of the memory according to this information, thereby taking corresponding repair measures. Thus, through MBIST, the memory can be fully automatically tested to ensure the reliability and correctness of the memory. In addition, the MBIST test process is fully automated, without the need for manual intervention, avoiding the cumbersome and errors of manual testing, and improving the efficiency and accuracy of the test.
[0075] In summary, the embodiment of the present application discloses a test system based on 2.5D integration, wherein the TAP state machine is used to generate a WSC signal; the WSC signal is sent to the WIR; the WIR is used to generate a register selection signal according to the WSC signal; when the register selection signal indicates the selection of the WCR, the TDI signal is sent to the WCR; the WCR is used to generate a SEL signal by parsing the TDI signal, and the SEL signal is used to indicate the core particle to be tested; the SEL signal is sent to the interface test circuit to instruct the interface test circuit to test the core particle to be tested. The present application only requires one TAP state machine, instead of one TAP state machine for each core particle, which not only reduces the design complexity, hardware resource cost and maintenance difficulty of the test system, but also can test the core particle to be tested more quickly and accurately, thereby speeding up the test speed and improving the test efficiency.
[0076] See also Figure 4 , which is a flow chart of a test method based on 2.5D integration provided by an embodiment of the present application. The method is applied to a test system based on 2.5D integration, and the test system based on 2.5D integration includes a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit. The method includes:
[0077] S401: The TAP state machine generates a test shell serial control WSC signal.
[0078] S402: The TAP state machine sends a WSC signal to the WIR.
[0079] S403: WIR generates a register selection signal according to the WSC signal.
[0080] S404: When the register selection signal indicates that WCR is selected, WIR sends the test data input TDI signal to WCR.
[0081] S405: The WCR generates a selection SEL signal by analyzing the TDI signal. The SEL signal is used to indicate the chip to be tested.
[0082] S406: The WCR sends a SEL signal to the interface test circuit to instruct the interface test circuit to test the chip to be tested.
[0083] In a specific implementation, the method also includes: the WCR generates a SEL signal and a Jump signal by parsing the TDI signal, and the SEL signal and the Jump signal together indicate skipping the test of the core particle to be tested; the WCR sends the SEL signal and the Jump signal to the interface test circuit to instruct the interface test circuit to test the next layer of core particles of the core particle to be tested.
[0084] In a specific implementation, the test system based on 2.5D integration also includes a test shell bypass register WBY; the method also includes: when the register selection signal indicates that WBY is selected, WIR sends a TDI signal to WBY; WIR sends the TDI signal to the next level core particle of the current core particle.
[0085] In a specific implementation, the test system based on 2.5D integration also includes a test shell boundary register WBR; WIR generates a register selection signal according to a WSC signal, including: WIR generates a scan test mode signal and a register selection signal according to the WSC signal; when the register selection signal indicates the selection of WCR, WIR sends the test data input TDI signal to WCR, including: when the register selection signal indicates the selection of WBR, WIR sends the TDI signal and the scan test mode signal to WBR; the method also includes: WBR performs a scan test on the current core particle according to the test type corresponding to the scan test mode signal.
[0086] In a specific implementation, the test type includes at least one of a serial internal scan test, a serial external scan test, a parallel internal scan test, and a parallel external scan test.
[0087] In a specific implementation, the test system based on 2.5D integration also includes a memory self-test circuit MBIST; the method also includes: when the register selection signal indicates that MBIST is selected, WIR sends a TDI signal to MBIST; MBIST performs an MBIST test on the current chip according to the TDI signal.
[0088] In a specific implementation, the method further includes: MBIST obtains a test result of the current chiplet undergoing the MBIST test; MBIST sends the test result to the test device via a test data output signal.
[0089] To sum up, the embodiment of the present application discloses a testing method based on 2.5D integration. The present application only requires one TAP state machine, instead of one TAP state machine for each chip. This not only reduces the design complexity, hardware resource cost and maintenance difficulty of the test system, but also can test the chip to be tested more quickly and accurately, thereby speeding up the test speed and improving the test efficiency.
[0090] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0091] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A test system based on 2.5D integration, characterized in that: The system comprises: a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit; The TAP state machine is used to generate a test shell serial control WSC signal; send the WSC signal to the WIR; The WIR is used to generate a register selection signal according to the WSC signal; when the register selection signal indicates that the WCR is selected, the test data input TDI signal is sent to the WCR; The WCR is used to generate a selection SEL signal by analyzing the TDI signal, wherein the SEL signal is used to indicate a chip to be tested; and send the SEL signal to the interface test circuit to instruct the interface test circuit to test the chip to be tested.
2. The system according to claim 1, characterized in that The WCR is also used to: generate a SEL signal and a Jump signal by parsing the TDI signal, the SEL signal and the Jump signal together indicating skipping the test of the core particle to be tested; and send the SEL signal and the Jump signal to the interface test circuit to instruct the interface test circuit to test the next layer of core particles of the core particle to be tested.
3. The system according to claim 1, characterized in that The system also includes a test shell bypass register WBY; The WIR is further configured to send the TDI signal to the WBY when the register selection signal indicates that the WBY is selected; The WBY is used to send the TDI signal to the next level of the current core particle.
4. The system according to claim 1, characterized in that The system also includes a test shell boundary register WBR; The WIR is specifically used to generate a scan test mode signal and a register selection signal according to the WSC signal; when the register selection signal indicates that the WBR is selected, the TDI signal and the scan test mode signal are sent to the WBR; The WBR is used to perform a scan test on the current chip according to the test type corresponding to the scan test mode signal.
5. The system according to claim 4, characterized in that The test type includes at least one of a serial internal scan test, a serial external scan test, a parallel internal scan test, and a parallel external scan test.
6. The system according to claim 1, characterized in that The system also includes a memory self-test circuit MBIST; The WIR is also used for sending the TDI signal to the MBIST when the register selection signal indicates that the MBIST is selected; The MBIST is used to perform an MBIST test on the current chip according to the TDI signal.
7. The system according to claim 6, characterized in that The MBIST is also used to obtain the test result of the MBIST test performed on the current core particle; and send the test result to the test equipment through a test data output signal.
8. A testing method based on 2.5D integration, characterized in that: The method is applied to a test system based on 2.5D integration, wherein the test system based on 2.5D integration includes a test access port TAP state machine, a test shell instruction register WIR, a test configuration register WCR and a test interface circuit; the method includes: The TAP state machine generates a test shell serial control WSC signal; The TAP state machine sends the WSC signal to the WIR; The WIR generates a register selection signal according to the WSC signal; When the register selection signal indicates that the WCR is selected, the WIR sends a test data input TDI signal to the WCR; The WCR generates a selection SEL signal by analyzing the TDI signal, and the SEL signal is used to indicate a core particle to be tested; The WCR sends the SEL signal to the interface test circuit to instruct the interface test circuit to test the chip to be tested.
9. The method according to claim 8, characterized in that The method further comprises: The WCR generates a SEL signal and a Jump signal by analyzing the TDI signal, wherein the SEL signal and the Jump signal together indicate to skip testing the chip to be tested; The WCR sends the SEL signal and the Jump signal to the interface test circuit to instruct the interface test circuit to test the next layer of the chip to be tested.
10. The method according to claim 8, characterized in that The system further includes a test shell bypass register WBY; the method further includes: When the register selection signal indicates that the WBY is selected, the WIR sends the TDI signal to the WBY; The WIR sends the TDI signal to a next-level chiplet of the current chiplet.