Multilayer circuit wafer for silicon carbide MOSFET wafer level aging and manufacturing method thereof

Abstract

The invention relates to the technical field of chip testing and aging tests, in particular to a multilayer circuit wafer for silicon carbide MOSFET wafer-level aging and a manufacturing method thereof.The wafer comprises arrayed detection chips, each detection chip comprises a source electrode contact salient point electrode and a grid electrode contact salient point electrode which are opposite to the front face of a silicon carbide MOSFET, and the source electrode contact salient point electrode and the grid electrode contact salient point electrode are arranged on the front face of the silicon carbide MOSFET. And a current detection circuit and an analog switch are arranged in each detection chip. When the leakage current of the drain electrode or the leakage current of the grid electrode exceeds a certain threshold value, the analog switch is immediately driven to be switched off, so that the main circuit is switched off, an aged chip is prevented from being burnt out due to heating caused by overlarge leakage current, and adverse effects on surrounding chips caused by burning of the chip are further avoided. During installation and use, good contact between each bump electrode and the silicon carbide MOSFET chip can be ensured only by applying small pressure to the back surface of the multi-layer circuit wafer. The wafer is fast in response and short in time delay, and the protection capability of chips and circuits is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing and aging test, and in particular to a multilayer circuit wafer for silicon carbide MOSFET wafer-level aging and a manufacturing method thereof. Background Art

[0002] Silicon carbide MOSFET chips have begun to gradually replace silicon IGBT chips and are used in the main electric drive of new energy vehicles. In the main electric drive, silicon carbide MOSFET chips are usually connected in parallel in the form of bare chips and packaged into power modules. The failure of one chip will lead to the failure of the entire module. On the one hand, the application scenarios of the main electric drive have the most stringent requirements on the early failure rate and long-term reliability of the chip. On the other hand, silicon carbide MOSFET chips cannot fully match silicon IGBT chips in terms of technical maturity. Therefore, before packaging into a power module, it is very important to reduce the failure rate of silicon carbide MOSFET chips.

[0003] SiC MOSFET bare chips cannot undergo complete testing or aging screening like discrete devices, so it is extremely necessary to develop wafer-level testing and aging screening technology. The existing wafer-level aging technology mainly uses precision machining technology to make fixtures and use probe cards to press and contact the electrodes on the surface of the SiC wafer. Although this solution is currently a common solution, it still has some shortcomings. For example: (1) There are too many probes, usually more than 1,000, which is expensive; (2) Sufficient pressure needs to be applied during the test to ensure that each probe card is in firm contact with the chip. Under such pressure, the probe card is prone to wear, and if 1 to 2 probes are damaged, the entire probe card cannot be used; (3) After the test, the probe card will leave an imprint on the chip surface, affecting the subsequent bonding or welding reliability; (4) If the probes are not firmly pressed during the test, the leakage current will be concentrated on a few probes, affecting the life of the probes and the chip. Therefore, a simple and reliable wafer-level aging test technology is needed, and its components are low-cost and easy to maintain or replace. Summary of the invention

[0004] In view of this, the purpose of the present invention is to propose a multi-layer circuit wafer for silicon carbide MOSFET wafer-level aging and a manufacturing method thereof, so as to solve the above-mentioned technical problems of existing silicon carbide MOSFET wafer-level aging chips.

[0005] Based on the above purpose, the present invention provides a multilayer circuit wafer for silicon carbide MOSFET wafer-level aging, comprising: A wafer containing a multi-layer circuit, wherein an arrayed detection chip is arranged inside a first concentric circle area of ​​the wafer, and an external circuit interface area is arranged in a circular ring area outside the first concentric circle, and each of the detection chips is arranged inside with a plurality of source contact bumps and a plurality of gate contact bumps, which are respectively used to connect the source electrode and the gate electrode of the aged silicon carbide MOSFET chip; Each detection chip is provided with a current detection circuit and an analog switch, and the external circuit interface area is provided with a common power supply terminal, a common ground terminal, a common reset terminal, a common source terminal, a common gate terminal of all detection chips, and a drain current detection output terminal and a gate current detection output terminal of each detection chip.

[0006] Preferably, the wafer is a silicon or silicon carbide wafer or a thick film circuit on a ceramic substrate. When the wafer is a silicon or silicon carbide wafer, the integrated circuit inside it is manufactured by a BCD process. When the wafer is a thick film circuit on a ceramic substrate, the integrated circuit inside it is assembled on the substrate by thick film circuit technology.

[0007] Preferably, the diameter of the wafer is 8 inches or 12 inches, wherein when the wafer diameter is 8 inches, the diameter of the first concentric circle area is 6 inches, and when the wafer diameter is 12 inches, the diameter of the first concentric circle area is 8 inches.

[0008] Preferably, when the diameter of the wafer is 8 inches, it is used to age a 6-inch silicon carbide MOSFET wafer, and when the diameter of the wafer is 12 inches, it is used to age an 8-inch silicon carbide MOSFET wafer; The array period of the in-wafer detection chip is the same as the array period of the aged silicon carbide MOSFET chip. The source contact bumps and gate contact bumps of the detection chip correspond one-to-one with the source electrode and gate electrode of the aged silicon carbide MOSFET chip, respectively, to achieve front-aligned crimping contact.

[0009] Preferably, the current detection circuit includes a sampling resistor, the sampling resistor and the analog switch are connected in series in the main circuit, the analog switch is placed before the sampling resistor, the differential mode voltage across the sampling resistor is input to the operational amplifier, so that a voltage is formed at the output end of the operational amplifier, i.e., across the load resistor, and the voltage value is a function of the leakage current of the main circuit. When the voltage VOUT across the load resistor reaches a set threshold, the analog switch is driven to turn off, thereby disconnecting the main circuit. The drain leakage current threshold corresponding to the VOUT threshold is set at IDSS between 100μA and 1mA, and the corresponding gate leakage current threshold is set at IGSS between 100nA and 100μA.

[0010] Preferably, the analog switch is controlled by the terminal voltage VOUT of the load resistor. When VOUT is higher than a set threshold, the analog switch is turned off to stop aging the corresponding silicon carbide MOSFET chip. After the common reset terminal obtains a reset signal, the analog switch is switched to the on state.

[0011] Preferably, in the external circuit interface region, the interface electrode is located on the back side of the multi-layer circuit wafer.

[0012] The present invention also provides a method for manufacturing the multilayer circuit wafer for wafer-level aging of silicon carbide MOSFET. When the wafer is a silicon or silicon carbide wafer, the manufacturing method comprises the following steps: S1. Using the BCD process, an arrayed integrated circuit unit is manufactured on the front side of an 8-inch or 12-inch wafer, including an operational amplifier, a sampling resistor R_SENSE_1 / 2, a load resistor RL_1 / 2, a pull-up resistor R1 / 2, an analog switch SWITCH_1 / 2, a SOURCE electrode and a GATE electrode connected to the silicon carbide chip, a source electrode SOURCE_PIN, a gate electrode GATE_PIN, a drain current output terminal IDSS_OUT, a gate current output terminal IGSS_OUT connected to an external circuit, a power supply electrode VCC, a ground electrode GND, and a reset electrode RESET; S2. Perform secondary wiring on the front side of the wafer to lead the SOURCE electrode and the GATE electrode connected to the silicon carbide chip to a position opposite to the front side of the silicon carbide MOSFET chip, and make a first bump electrode; S3. Perform secondary wiring on the back side of the wafer, lead the external circuit interface electrode to the range of the ring outside the first concentric circle, and make a second bump electrode.

[0013] Preferably, the bump electrode is a solder bump electrode or a copper pillar plus a solder bump electrode.

[0014] When the wafer is a thick film circuit on a ceramic substrate, the manufacturing method includes: Thick film technology is used to manufacture sampling resistors R_SENSE_1 / 2, load resistors RL_1 / 2, pull-up resistors R1 / 2 and electrodes. The operational amplifier bare chip and analog switch bare chip are encapsulated in the thick film circuit using welding technology. The characteristics of the laser adjustment group are used to accurately control the resistance value and improve the accuracy of current detection and control functions.

[0015] Beneficial effects of the present invention: The invention provides a multilayer circuit wafer for silicon carbide MOSFET wafer-level aging. The wafer is easy to install and use, the pressure applied during installation is small, and the protection of the aged wafer is good. Specifically, the wafer includes an arrayed detection chip, each detection chip includes a source contact bump electrode and a gate contact bump electrode opposite to the front of the silicon carbide MOSFET, and each detection chip contains a current detection circuit and an analog switch. When the drain leakage current or the gate leakage current exceeds a certain threshold, the analog switch is immediately driven to turn off, so that the main circuit is disconnected, so that the aged chip is prevented from heating and burning due to excessive leakage current, and the chip burning is further prevented from causing adverse effects on surrounding chips. When installed and used, only a small pressure is applied to the back of the multilayer circuit wafer to ensure that each bump electrode is in good contact with the silicon carbide MOSFET chip. When it is detected that the leakage current exceeds the threshold, the main circuit can be immediately turned off in the local circuit, with fast response and short delay, thereby improving the protection capability of the chip and the circuit.

[0016] The present invention provides a method for manufacturing a multilayer circuit wafer for wafer-level aging of silicon carbide MOSFET. The manufacturing process of the multilayer circuit wafer is simple, the electrode setting is flexible and changeable, and it can withstand high temperature operation. Specifically, the method is as follows: a detection unit is manufactured on the front side of a silicon or silicon carbide wafer using a BCD process. The detection unit is an analog integrated circuit, which includes a current detection function and an overcurrent protection shutdown function. Each electrode is led out to a corresponding position through secondary wiring (RDL) on the front and back sides, and a bump electrode is manufactured. As an alternative, a multilayer circuit wafer can be manufactured based on thick film circuit technology, and the circuit can be operated at an optimal operating point using laser resistance adjustment technology. The multilayer circuit wafer is easy to manufacture, the electrode position setting is flexible and accurate, and the multilayer circuit wafer manufactured using thick film technology supports high temperature operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the specific structure of a multi-layer circuit wafer according to an embodiment of the present invention; Figure 2 is a circuit schematic diagram of a detection unit according to an embodiment of the present invention; Figure 3 A schematic diagram of the position of bump electrodes of the secondary wiring (RDL) of an embodiment of the present invention; DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0020] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] like Figure 1 As shown, the embodiment of this specification provides a multilayer circuit wafer for silicon carbide MOSFET wafer-level aging, the wafer includes an arrayed detection chip, each detection chip includes a source contact bump electrode and a gate contact bump electrode opposite to the front of the silicon carbide MOSFET, and each detection chip contains a current detection circuit and an analog switch. When the drain leakage current or the gate leakage current exceeds a certain threshold, the analog switch is immediately driven to turn off, so that the main circuit is disconnected, so that the aged chip is prevented from heating and burning due to excessive leakage current, and the chip burning is also prevented from causing adverse effects on surrounding chips. When installing and using, only a small pressure needs to be applied to the back of the multilayer circuit wafer to ensure good contact between each bump electrode and the silicon carbide MOSFET chip. When it is detected that the leakage current exceeds the threshold, the main circuit can be immediately turned off in the local circuit, with fast response and short delay, which improves the protection capability of the chip and the circuit.

[0022] Specifically, the structure includes a wafer 100 with a diameter of 8 inches (or 12 inches) and containing multi-layer circuits, an arrayed detection chip is arranged inside the 6-inch (or 8-inch) concentric circle area, and an interface for an external circuit is arranged in the circular ring area outside the 6-inch (or 8-inch) area. Each detection chip is provided with one or more source contact bumps and one or more gate contact bumps, which are used to respectively connect the source electrode and gate electrode of the aged silicon carbide MOSFET chip. Each detection chip is also provided with a current detection circuit and an analog switch. The external circuit interface area is provided with a common power supply terminal (VCC), a common ground terminal (GND), a common reset terminal (RESET), a common source terminal (SOURCE), a common gate terminal (GATE) of all detection chips, and a drain current detection output terminal (IDSS_OUT) and a gate current detection output terminal (IGSS_OUT) of each detection chip.

[0023] As an implementation method, the wafer 100 is a silicon or silicon carbide wafer, and a functional integrated circuit is manufactured inside the wafer 100 by a BCD process. The wafer 100 can also be a thick film circuit on a ceramic substrate, and the functional chip is assembled on the substrate by thick film circuit technology. The latter supports the entire wafer 100 to work in a higher ambient temperature, including but not limited to Ta=200°C.

[0024] When the size of the wafer 100 is 8 inches, it can be used to age a 6-inch silicon carbide MOSFET wafer. When the size of the wafer 100 is 12 inches, it can be used to age an 8-inch silicon carbide MOSFET wafer. The array period of the detection chip in the wafer 100 is the same as the array period of the aged silicon carbide MOSFET chip, and the source contact bumps and gate contact bumps of the detection chip correspond one-to-one with the source electrode and gate electrode of the aged silicon carbide MOSFET chip, respectively, to achieve front-aligned crimping contact.

[0025] As an implementation method, a current detection circuit and an analog switch are provided in the detection chip, and the circuit diagram is shown in FIG. Figure 2 As shown, the analog switch and the sampling resistor are connected in series in the main circuit, and the analog switch is placed before the sampling resistor. The differential mode voltage across the sampling resistor is input to the operational amplifier 201, so that a voltage is formed at the output end of the operational amplifier, that is, at both ends of the load resistor RL, and the voltage value is a function of the leakage current of the main circuit. When the voltage VOUT across RL reaches a certain threshold, that is, the silicon carbide MOSFET corresponding to the detection chip has failed due to the large leakage current, at this time VOUT drives the analog switch to turn off, thereby disconnecting the main circuit, and the silicon carbide MOSFET chip stops aging. The drain leakage current threshold corresponding to the VOUT threshold can be set at IDSS between 100μA~1mA, and the corresponding gate leakage current threshold can be set at IGSS between 100nA~100μA.

[0026] The analog switch is controlled by the terminal voltage VOUT of the load resistor RL. When VOUT is higher than the threshold, the analog switch is turned off and the corresponding silicon carbide MOSFET chip stops aging. When the common reset terminal RESET receives a reset signal, the analog switch switches to the on state.

[0027] As an implementation method, the external circuit interface is within a 6-inch (or 8-inch) to 8-inch (or 12-inch) circular ring, and the interface electrode is located on the back of the multilayer circuit wafer. The external circuit interface includes a common power supply terminal (VCC), a common ground terminal (GND), a common main circuit source terminal (SOURCE), and a common main circuit gate terminal (GATE) shared by all detection chips, and also includes the voltage output terminal VOUT of each detection chip, namely the drain current detection output terminal (IDSS_OUT) and the gate current detection output terminal (IGSS_OUT).

[0028] Furthermore, when installing and using the multi-layer circuit wafer, only a small pressure needs to be applied to the back side to achieve firm contact with the silicon carbide MOSFET wafer, and it is highly tolerant to the warping of the wafer itself.

[0029] The embodiments of this specification also provide a method for manufacturing the above-mentioned multi-layer circuit wafer for wafer-level aging of silicon carbide MOSFET. The detection unit is manufactured on the front of the silicon or silicon carbide wafer using the BCD process. The detection unit is an analog integrated circuit that includes a current detection function and an overcurrent protection shutdown function. Through the secondary wiring (RDL) on the front and back, each electrode is led out to the corresponding position, and a bump electrode is made. As an alternative, a multi-layer circuit wafer can be made based on thick film circuit technology, and the circuit can be operated at the optimal operating point using laser resistance adjustment technology. The multi-layer circuit wafer is easy to manufacture, and the electrode position setting is flexible and accurate. The multi-layer circuit wafer made using thick film technology supports high temperature operation.

[0030] Specifically, the manufacturing method includes the following steps: S1. Using the BCD process, an arrayed integrated circuit unit 200 is manufactured on the front side of an 8-inch (or 12-inch) wafer 100, including an operational amplifier 201, a sampling resistor R_SENSE_1 / 2, a load resistor RL_1 / 2, a pull-up resistor R1 / 2, an analog switch SWITCH_1 / 2, a SOURCE electrode and a GATE electrode connected to the silicon carbide chip, a source electrode SOURCE_PIN, a gate electrode GATE_PIN, a drain current output terminal IDSS_OUT, and a gate current output terminal IGSS_OUT connected to an external circuit, a power supply electrode VCC, a ground electrode GND, and a reset electrode RESET; S2. Perform secondary wiring (RDL) on the front side of the 8-inch (or 12-inch) wafer 100, lead the SOURCE electrode and the GATE electrode connected to the silicon carbide chip to a position opposite to the front side of the silicon carbide MOSFET chip, and make a first bump electrode 300; S3. Perform secondary wiring (RDL) on the back of the 8-inch (or 12-inch) wafer 100, lead the external circuit interface electrode to a circular range of 6 inches (or 8 inches) to 8 inches (or 12 inches), and make a second bump electrode 400. The secondary wiring is as follows Figure 3 shown.

[0031] The 8-inch (or 12-inch) wafer 100 can also be a ceramic substrate thick film circuit, and the sampling resistor R_SENSE_1 / 2, the load resistor RL_1 / 2, the pull-up resistor R1 / 2 and the electrode are manufactured using thick film technology. The operational amplifier 201 bare chip and the analog switch bare chip are packaged in the thick film circuit using welding technology. The characteristics of the laser adjustment group are used to accurately control the resistance value and improve the accuracy of the current detection and control functions.

[0032] As an implementation mode, the bump electrode may be a solder bump electrode or a copper pillar+solder bump electrode.

[0033] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present invention is limited to these examples; under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multilayer circuit wafer for silicon carbide MOSFET wafer-level aging, characterized in that: include: A wafer containing a multi-layer circuit, wherein an arrayed detection chip is arranged inside a first concentric circle area of ​​the wafer, and an external circuit interface area is arranged in a circular ring area outside the first concentric circle, and each of the detection chips is arranged inside with a plurality of source contact bumps and a plurality of gate contact bumps, which are respectively used to connect the source electrode and the gate electrode of the aged silicon carbide MOSFET chip; Each detection chip is provided with a current detection circuit and an analog switch, and the external circuit interface area is provided with a common power supply terminal, a common ground terminal, a common reset terminal, a common source terminal, a common gate terminal of all detection chips, and a drain current detection output terminal and a gate current detection output terminal of each detection chip.

2. The multilayer circuit wafer for silicon carbide MOSFET wafer-level aging according to claim 1, characterized in that: The wafer is a silicon or silicon carbide wafer or a thick film circuit on a ceramic substrate. When the wafer is a silicon or silicon carbide wafer, the integrated circuit inside it is manufactured using a BCD process. When the wafer is a thick film circuit on a ceramic substrate, the integrated circuit inside it is assembled on the substrate using thick film circuit technology.

3. The multilayer circuit wafer for silicon carbide MOSFET wafer-level aging according to claim 1, characterized in that: The diameter of the wafer is 8 inches or 12 inches. When the diameter of the wafer is 8 inches, the diameter of the first concentric circle area is 6 inches. When the diameter of the wafer is 12 inches, the diameter of the first concentric circle area is 8 inches.

4. The multilayer circuit wafer for silicon carbide MOSFET wafer-level aging according to claim 3, characterized in that: When the diameter of the wafer is 8 inches, it is used to age a 6-inch silicon carbide MOSFET wafer; when the diameter of the wafer is 12 inches, it is used to age an 8-inch silicon carbide MOSFET wafer; The array period of the in-wafer detection chip is the same as the array period of the aged silicon carbide MOSFET chip. The source contact bumps and gate contact bumps of the detection chip correspond one-to-one with the source electrode and gate electrode of the aged silicon carbide MOSFET chip, respectively, to achieve front-aligned crimping contact.

5. The multilayer circuit wafer for silicon carbide MOSFET wafer-level aging according to claim 1, characterized in that: The current detection circuit includes a sampling resistor, the sampling resistor and the analog switch are connected in series in the main circuit, the analog switch is placed before the sampling resistor, the differential mode voltage across the sampling resistor is input to the operational amplifier, so that the output end of the operational amplifier, i.e., the two ends of the load resistor, forms a voltage, and the voltage value is a function of the leakage current of the main circuit. When the voltage VOUT across the load resistor reaches a set threshold, the analog switch is driven to turn off, thereby disconnecting the main circuit. The drain leakage current threshold corresponding to the VOUT threshold is set at IDSS between 100μA~1mA, and the corresponding gate leakage current threshold is set at IGSS between 100nA~100μA.

6. The multilayer circuit wafer for silicon carbide MOSFET wafer-level aging according to claim 5, characterized in that: The analog switch is controlled by the terminal voltage VOUT of the load resistor. When VOUT is higher than a set threshold, the analog switch is turned off to stop aging the corresponding silicon carbide MOSFET chip. After the common reset terminal obtains a reset signal, the analog switch is switched to the on state.

7. The multilayer circuit wafer for silicon carbide MOSFET wafer-level aging according to claim 1, characterized in that: In the external circuit interface region, the interface electrode is located on the back side of the multilayer circuit wafer.

8. A method for manufacturing a multilayer circuit wafer for wafer-level aging of silicon carbide MOSFET according to any one of claims 1 to 7, characterized in that: When the wafer is a silicon or silicon carbide wafer, the manufacturing method comprises the following steps: S1. Using the BCD process, an arrayed integrated circuit unit is manufactured on the front side of an 8-inch or 12-inch wafer, including an operational amplifier, a sampling resistor R_SENSE_1 / 2, a load resistor RL_1 / 2, a pull-up resistor R1 / 2, an analog switch SWITCH_1 / 2, a SOURCE electrode and a GATE electrode connected to the silicon carbide chip, a source electrode SOURCE_PIN, a gate electrode GATE_PIN, a drain current output terminal IDSS_OUT, a gate current output terminal IGSS_OUT connected to an external circuit, a power supply electrode VCC, a ground electrode GND, and a reset electrode RESET; S2. Perform secondary wiring on the front side of the wafer to lead the SOURCE electrode and the GATE electrode connected to the silicon carbide chip to a position opposite to the front side of the silicon carbide MOSFET chip, and make a first bump electrode; S3. Perform secondary wiring on the back side of the wafer, lead the external circuit interface electrode to the range of the ring outside the first concentric circle, and make a second bump electrode.

9. The method for manufacturing a multilayer circuit wafer for wafer-level aging of silicon carbide MOSFET according to claim 8, characterized in that: The bump electrode is a solder bump electrode or a copper pillar plus a solder bump electrode.

10. A method for manufacturing a multilayer circuit wafer for wafer-level aging of silicon carbide MOSFET according to any one of claims 1 to 7, characterized in that: When the wafer is a thick film circuit of a ceramic substrate, the manufacturing method includes: Thick film technology is used to manufacture sampling resistors R_SENSE_1 / 2, load resistors RL_1 / 2, pull-up resistors R1 / 2 and electrodes. The operational amplifier bare chip and analog switch bare chip are encapsulated in the thick film circuit using welding technology. The characteristics of the laser adjustment group are used to accurately control the resistance value and improve the accuracy of current detection and control functions.

Images