Wide common mode input circuit exceeding power rail

Abstract

The invention discloses a wide common-mode input circuit exceeding a power rail, and the circuit comprises a resistor network, the input port of which is connected with a positive input detection end INP and a negative input detection end INN; an input port of the pressure drop pipeline and the resistance network are coupled at nodes P3 and P4; two drain electrodes of the pair transistors MON14 and MON15 are respectively coupled with the pressure drop pipeline at nodes P5 and P6; the current mirror is connected with the source electrode of the MON 14 and the source electrode of the MON 15; the output end of the charge pump serves as a reference level of the negative power supply and is connected with the common source end of the current mirror; the oscillator is coupled between the node P3 and the node P5, the floating voltage VDD1 of the node P3 supplies power to the oscillator, and the node P5 is a first grounding end GND1 and is connected with the oscillator; and the current detection amplifier OPA is coupled between the node P4 and the node P6, the floating voltage VDD2 of the node P4 supplies power to the current detection amplifier OPA, and the node P6 is a second grounding end GND2 and is connected with the current detection amplifier OPA. The common-mode input range is not limited by the power supply voltage, and the circuit is widely suitable for large PWM driving signals.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a wide common-mode input circuit exceeding a power rail. Background Art

[0002] In motor control and drone propeller control systems, it is necessary to monitor the operating current of the system or subsystem in real time to help achieve precise control of the motor and drone propeller. In recent years, due to the rapid development of technology in the field of integrated circuits, motor control systems have widely used pulse width modulation (PWM) signals to control the operation of motors. The switching voltage of PWM signals has become higher and higher, which can greatly exceed the power supply voltage, and even be negative voltage. The input common-mode voltage of common integrated circuits is limited by the power supply voltage, generally between the ground and the power supply voltage. Therefore, it is extremely urgent to design a wide common-mode input circuit that exceeds the power rail for large PWM drive signals. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a wide common mode input circuit that exceeds the power rail, wherein the common mode input range is not restricted by the power supply voltage and is widely applicable to large PWM drive signals.

[0004] The technical solution adopted by the present invention is:

[0005] A wide common-mode input circuit exceeding the power rail includes: a resistor network, whose input port is connected to a positive input detection terminal INP and a reverse input detection terminal INN; a voltage drop circuit, whose input port and the output port of the resistor network are coupled to nodes P3 and P4; a pair of tubes MON14 and MON15, whose two drains are respectively coupled to the output port of the voltage drop circuit at nodes P5 and P6; a current mirror, whose output port is connected to the source of MON14 and the source of MON15; a charge pump, whose output terminal is used as a reference level of a negative power supply and is connected to the common source terminal of the current mirror; an oscillator, coupled between node P3 and node P5, and node P3 has a floating voltage V DD1 , V DD1 The oscillator is powered, and the node P5 is the first ground terminal GND1, which is connected to the ground terminal of the oscillator; the current detection amplifier OPA is coupled between the node P4 and the node P6, and the node P4 has a floating voltage V DD2 , V DD2 The current detection amplifier OPA is powered, and the node P6 is the second ground terminal GND2, which is connected to the ground terminal of the current detection amplifier OPA.

[0006] As an optional technical solution, the wide common mode input circuit also includes: a first bias circuit connected to the input port of the current mirror to provide bias for the current mirror; a second bias circuit connected to the common gate end of the pair of tubes MON14 and MON15 to provide bias for MON14 and MON15.

[0007] As an optional technical solution, the first bias circuit includes a resistor R1, MOS tubes MON1 and MON2, the drain of MON1 is connected to the resistor R1, the source of MON1 is connected to the drain of MON2, and the two ends of the resistor R1 are respectively connected to the gate of MON1 and the gate of MON2, and then respectively connected to the connection terminals NP1 and NP2.

[0008] As an optional technical solution, the second bias circuit includes a MOS tube MON6 and MOS tubes MON3, MON4, MON5_1, MON5_2, MON5_3, MON7, MON8_1, and MON8_2 whose gates and drains are short-circuited, wherein MON3 and MON6 share a gate, MON3, MON4, MON5_1, MON5_2, and MON5_3 are connected in series in sequence, and MON6, MON7, MON8_1, and MON8_2 are connected in series in sequence, and the series connection means that the source of the previous MOS tube is connected to the drain of the next MOS tube.

[0009] As an optional technical solution, the resistor network includes resistors R2_1, R2_2, R3_1, and R3_2, the reverse input detection terminal INN is connected to one end of the resistor R2_1 and one end of the resistor R3_1, the forward input detection terminal INP is connected to one end of the resistor R2_2 and one end of the resistor R3_2, the other end of the resistor R2_1 and the other end of R2_2 are coupled to a node P3, and the other end of the resistor R3_1 and the other end of R3_2 are coupled to a node P4.

[0010] As an optional technical solution, the voltage drop circuit includes MOS tubes MON17_0, MON17_1, MON17_2, MON17_3, MON17_4, MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4, whose gates and drains are short-circuited respectively, wherein MON17_0, MON17_1, MON17_2, MON17_3, and MON17_4 are connected in series in sequence, and MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4 are connected in series in sequence, the drain of MON17_0 is coupled to the node P3, the drain of MON18_0 is coupled to the node P4, the source of MON17_4 is coupled to the node P5, and the source of MON18_4 is coupled to the node P6.

[0011] As an optional technical solution, the current mirror includes MON9, MON10, MON11, and MON12, wherein MON14, MON10, and MON9 are connected in series in sequence, MON15, MON12, and MON11 are connected in series in sequence, MON9 and MON11 have a common source and a common gate, and the common source end is connected to the charge pump, and the common gate end is connected to the connection terminal NP2, and MON10 and MON12 have a common gate, and the common gate end is connected to the connection terminal NP1.

[0012] As an optional technical solution, the wide common mode input circuit also includes a first protection circuit for preventing the gate-source voltage of the field effect transistors MON14 and MON15 from being too large; the first protection circuit includes MOS transistors MOP2_1 and MOP2_2, wherein the gate-source of MOP2_1 is short-circuited and its source and drain are respectively connected to the gate and source of MON14, and the gate-drain of MOP2_2 is short-circuited and its source and drain are respectively connected to the source and gate of MON15.

[0013] As an optional technical solution, the wide common mode input circuit also includes a second protection circuit for preventing the voltage difference between the first ground terminal GND1 and the second ground terminal GND2 from exceeding a first threshold; the second protection circuit includes MOS tubes MON13_1 and MON13_2, wherein the gate source of MON13_1 is short-circuited and connected to the node P6, the drain of MON13_1 is connected to the node P5, the gate source of MON13_2 is short-circuited and connected to the node P5, and the drain of MON13_2 is connected to the node P6.

[0014] As an optional technical solution, the wide common mode input circuit further includes a third protection circuit for preventing the floating voltage V DD1 With floating voltage V DD2 The voltage difference between them exceeds the second threshold; the third protection circuit includes MOS tubes MOP1_1 and MOP1_2, wherein the gate source of MOP1_1 is short-circuited and connected to the node P3, the drain of MOP1_1 is connected to the node P4, the gate source of MOP1_2 is short-circuited and connected to the node P4, and the drain of MOP1_2 is connected to the node P3.

[0015] The beneficial effects of the present invention are as follows: the present invention provides a wide common-mode input circuit that exceeds the power rail, and ensures that the current detection amplifier circuit works normally when a wide common-mode voltage range is input in current monitoring, so that the common-mode voltage is not limited by the power supply; since the negative voltage generated by the charge pump is used as the ground of the circuit structure, the common-mode input voltage of the current detection amplifier OPA can be as low as a negative voltage while ensuring the normal working conditions of the circuit structure; when using a single power supply, the current detection amplifier OPA can work normally within the common-mode input voltage range of negative several volts to hundreds of volts, has a wider common-mode input voltage range, and greatly improves the input range of the common-mode voltage of the current detection amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit block diagram of a wide common-mode input circuit that exceeds the power supply rails in an exemplary embodiment.

[0017] Figure 2 FIG. 4 is a detailed circuit schematic diagram of a wide common-mode input circuit exceeding the power supply rail in an exemplary embodiment. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] In the description of the present application, the words "first" and "second" are used to distinguish objects with similar names, functions or effects. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity and execution order. Therefore, the features defined as "first", "second", etc. may explicitly or implicitly include one or more of the similar features. Unless otherwise clearly specified and limited, the term "coupled" in the present application is used to indicate electrical connection, including direct connection through wires or connection terminals or indirect connection through other devices. Therefore, "coupling" should be regarded as a broad electronic communication connection.

[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] Example

[0022] like Figure 1 and Figure 2 As shown, this embodiment discloses a wide common-mode input circuit exceeding the power rail, including: a resistor network 9, whose input port is connected to a positive input detection terminal INP and a reverse input detection terminal INN; a voltage drop circuit 7, whose input port is coupled to the output port of the resistor network 9 at nodes P3 and P4; a pair of transistors MON14 and MON15, whose two drains are respectively coupled to the output port of the voltage drop circuit 7 at nodes P5 and P6; a current mirror 4, whose output port is connected to the source of MON14 and the source of MON15; a charge pump 3, whose output terminal is used as a reference level of a negative power supply and is connected to the common source terminal of the current mirror 4; an oscillator 10, coupled between node P3 and node P5, and node P3 has a floating voltage V DD1 , V DD1 The oscillator 10 is powered, and the node P5 is the first ground terminal GND1, which is connected to the ground terminal of the oscillator 10; the current detection amplifier OPA is coupled between the node P4 and the node P6, and the node P4 has a floating voltage V DD2 , V DD2 Power is supplied to the current detection amplifier OPA, and node P6 is the second ground terminal GND2, which is connected to the ground terminal of the current detection amplifier OPA; the in-phase terminal of the current detection amplifier OPA is connected to the positive input detection terminal INP, and the inverting terminal is connected to the reverse input detection terminal INN, and a resistor R is also connected between the in-phase terminal and the inverting terminal.

[0023] As an optional implementation, the wide common-mode input circuit further includes: a first bias circuit 1, connected to the input port of the current mirror 4, to provide bias for the current mirror 4; a second bias circuit 2, connected to the common gate end of the pair of tubes MON14 and MON15, to provide bias for MON14 and MON15.

[0024] As an optional implementation, the first bias circuit 1 includes a resistor R1, MOS tubes MON1 and MON2, one end of the resistor R1 is connected to the external bias current NIB0, and the other end is connected to the drain of MON1, the source of MON1 is connected to the drain of MON2, and the two ends of the resistor R1 are also connected to the gate of MON1 and the gate of MON2, and then connected to the connection terminals NP1 and NP2 respectively.

[0025] As an optional implementation, the second bias circuit 2 includes a MOS tube MON6 and MOS tubes MON3, MON4, MON5_1, MON5_2, MON5_3, MON7, MON8_1, and MON8_2 whose gates and drains are short-circuited, wherein MON3 and MON6 share a common gate, MON3, MON4, MON5_1, MON5_2, and MON5_3 are connected in series in sequence, and MON6, MON7, MON8_1, and MON8_2 are connected in series in sequence. In the present application, all series connections refer to the source of the previous MOS tube being connected to the drain of the next MOS tube; the gate and drain of MON3 are short-circuited to connect to the external bias current NIB1, and the drain of MON6 is grounded.

[0026] As an optional embodiment, the resistor network 9 includes resistors R2_1, R2_2, R3_1, and R3_2, the reverse input detection terminal INN is connected to one end of the resistor R2_1 and one end of the resistor R3_1, the forward input detection terminal INP is connected to one end of the resistor R2_2 and one end of the resistor R3_2, the other end of the resistor R2_1 and the other end of R2_2 are coupled to a node P3, and the other end of the resistor R3_1 and the other end of R3_2 are coupled to a node P4.

[0027] As an optional implementation, the voltage drop circuit 7 includes MOS tubes MON17_0, MON17_1, MON17_2, MON17_3, MON17_4, MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4, whose gates and drains are short-circuited, wherein MON17_0, MON17_1, MON17_2, MON17_3, and MON17_4 are connected in series in sequence, and MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4 are connected in series in sequence, and the drain of MON17_0 is coupled to the node P3, the drain of MON18_0 is coupled to the node P4, the source of MON17_4 is coupled to the node P5, and the source of MON18_4 is coupled to the node P6. A protection tube MON16 is also provided between the nodes P3 and P5.

[0028] As an optional implementation, the current mirror 4 includes MON9, MON10, MON11, and MON12, wherein MON14, MON10, and MON9 are connected in series in sequence, MON15, MON12, and MON11 are connected in series in sequence, MON9 and MON11 share a common source and a common gate, and the common source end is connected to the charge pump 3, and the common gate end is connected to the connection terminal NP2, and MON10 and MON12 share a common gate, and the common gate end is connected to the connection terminal NP1.

[0029] As an optional implementation, the wide common mode input circuit further includes a first protection circuit 5, which is used to prevent the gate-source voltage of the field effect transistors MON14 and MON15 from being too large; the first protection circuit 5 includes MOS transistors MOP2_1 and MOP2_2, wherein the gate-source of MOP2_1 is short-circuited and its source and drain are respectively connected to the gate and source of MON14, and the gate-drain of MOP2_2 is short-circuited and its source and drain are respectively connected to the source and gate of MON15. Among them, MON7, MON14 and MON15 share a common gate.

[0030] As an optional implementation, the wide common mode input circuit further includes a second protection circuit 6, which is used to prevent the voltage difference between the first ground terminal GND1 and the second ground terminal GND2 from exceeding a first threshold value, wherein the value range of the first threshold value is -Von to Von, wherein Von is the forward conduction voltage of the body diode; the second protection circuit 6 includes MOS tubes MON13_1 and MON13_2, wherein the gate source of MON13_1 is short-circuited and connected to the node P6, the drain of MON13_1 is connected to the node P5, the gate source of MON13_2 is short-circuited and connected to the node P5, and the drain of MON13_2 is connected to the node P6.

[0031] As an optional implementation, the wide common mode input circuit further includes a third protection circuit 8 for preventing the floating voltage V DD1 With floating voltage V DD2 The voltage difference between them exceeds the second threshold value, the value range of the second threshold value is -Von~Von, where Von is the forward conduction voltage of the body diode; the third protection circuit 8 includes MOS tubes MOP1_1 and MOP1_2, wherein the gate source of MOP1_1 is short-circuited and connected to the node P3, the drain of MOP1_1 is connected to the node P4, the gate source of MOP1_2 is short-circuited and connected to the node P4, and the drain of MOP1_2 is connected to the node P3.

[0032] It should be noted that, in this embodiment, MON refers to an N-type MOS transistor, and MOP refers to a P-type MOS transistor.

[0033] In order to better understand this embodiment, a circuit analysis of this embodiment is performed below.

[0034] In this embodiment, the negative voltage generated by the charge pump 3 (CHARGE_PUMP) is used as the negative voltage source of the circuit to ensure that the circuit can work normally when the common-mode input voltage is the lowest value. The floating voltage V DD2 and GND2 to power the current sensing amplifier OPA, V DD1 and GND1 to power the oscillator 10 (OSCILLATOR).

[0035] according to Figure 2From the circuit structure shown, we can see that:

[0036] V DD1 =V INN -V R2_1 ;

[0037] V GND1 =V DD1 -(V GS1 +V GS2 +V GS3 +V GS4 +V GS5 );

[0038] V DD2 =V INP -V R3_2 ;

[0039] V GND2 =V DD2 -(V GS6 +V GS7 +V GS8 +V GS9 +V GS10 );

[0040] Among them, V R2_1 is the voltage across resistor R2_1, V R3_2 is the voltage across resistor R3_2, V GS1 、V GS2 、V GS3 、V GS4 、V GS5 、V GS6 、V GS7 、V GS8 、V GS9 、V GS10 They are the gate-source voltages of MON17_0, MON17_1, MON17_2, MON17_3, MON17_4, MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4 respectively. Therefore, the power supply voltage of the current detection amplifier OPA is only related to the common-mode input voltage and has nothing to do with the external power supply.

[0041] Floating voltage V DD2 and GND2 to power the current sensing amplifier OPA, V DD1and GND1 to power the oscillator 10 (OSCILLATOR). Through this structure, the power supply voltage of the current detection amplifier OPA and the oscillator 10 is associated with the common-mode input voltage, and the external power supply voltage only involves the construction of the bias circuit. This also allows the input common-mode voltage of the current detection amplifier OPA to be free from the limitation of the external power supply voltage. When the external power supply voltage is low, the common-mode input voltage of the current detection amplifier OPA can be as high as tens of volts or even hundreds of volts.

[0042] In this embodiment, the field effect transistors MOP1_1, MOP1_2, MON13_1 and MON13_2 are protection transistors for preventing V DD1 and V DD2 The voltage difference between GND1 and GND2 is too large.

[0043] The resistor R1, the field effect transistors MON1, MON2 and the external bias current NIB0 work together to provide a bias voltage for the field effect transistors MON10, MON12 and MON9, MON11.

[0044] The field effect transistors MON3, MON4, MON5_1, MON5_2, MON5_3, the external bias current NIB1 and the field effect transistors MON6, MON7, MON8_1, MON8_2 work together to provide bias voltages for the field effect transistors MON14 and MON15.

[0045] The field effect transistors MOP2_1 and MOP2_2 are protection transistors to prevent the gate-source voltage of the field effect transistors MON14 and MON15 from being too large.

[0046] Field effect transistors MON3, MON4, MON6, MON7, MOP2_1 and MOP2_2 all use high voltage resistant devices, and field effect transistor MON16 is used as a protection tube for the circuit when large current is generated.

[0047] Field effect transistors MON14 and MON15 use high-voltage devices. The higher the device's voltage resistance, the higher the common-mode input voltage range of the current detection amplifier OPA.

[0048] The negative voltage generated by the charge pump CHARGE_PUMP is used as the ground of the entire circuit structure. While ensuring the normal working conditions of the entire circuit shown, the common-mode input voltage of the current detection amplifier OPA can be as low as a negative voltage.

[0049] The oscillator 10 (OSCILLATOR) provides a clock signal required for chopping to the current detection amplifier OPA through the output terminal P1.

[0050] This embodiment provides Figure 2The wide common-mode input circuit that exceeds the power rail shown, when applied to current monitoring, can monitor the input common-mode voltage that is lower than the power supply voltage or higher than the power supply voltage, and achieve a wide input common-mode voltage range without being constrained by the power supply voltage. Since the negative voltage generated by the charge pump is used as the ground of the entire circuit structure, the common-mode input voltage of the current detection amplifier can be as low as a negative voltage within the normal working conditions of the circuit. When using a single power supply, the current detection amplifier can work normally in the range of a common-mode input voltage of negative several volts to hundreds of volts, with a wide common-mode input voltage range, which greatly improves the input range of the common-mode voltage of the current detection amplifier circuit.

[0051] The above description is only a specific implementation mode of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. All technical solutions that fall within the scope defined by the claims of the present invention fall within the protection scope of the present invention.

Claims

1. A wide common-mode input circuit that exceeds the power rail, characterized in that, include: A resistor network, whose input port is connected to a positive input detection terminal INP and a reverse input detection terminal INN; a pressure drop circuit, whose input port and the output port of the resistor network are coupled to nodes P3 and P4; For the tubes MON14 and MON15, the two drains thereof are respectively coupled to the output ports of the voltage drop circuit at nodes P5 and P6; A current mirror, whose output port is connected to the source of MON14 and the source of MON15; A charge pump, whose output terminal is used as a reference level of the negative power supply and is connected to the common source terminal of the current mirror; The oscillator is coupled between the node P3 and the node P5, and the node P3 has a floating voltage V DD1 , V DD1 Powering the oscillator, the node P5 is the first ground terminal GND1, and GND1 is connected to the ground terminal of the oscillator; The current detection amplifier OPA is coupled between the node P4 and the node P6, and the node P4 has a floating voltage V DD2 , V DD2 The current detection amplifier OPA is powered, and the node P6 is the second ground terminal GND2, which is connected to the ground terminal of the current detection amplifier OPA.

2. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The wide common mode input circuit further includes: A first bias circuit, connected to an input port of the current mirror, to provide a bias for the current mirror; The second bias circuit is connected to the common gate terminal of the pair of transistors MON14 and MON15 to provide bias for MON14 and MON15.

3. The wide common mode input circuit exceeding the power rail according to claim 2, characterized in that: The first bias circuit includes a resistor R1, MOS tubes MON1 and MON2, the drain of MON1 is connected to the resistor R1, the source of MON1 is connected to the drain of MON2, and both ends of the resistor R1 are respectively connected to the gate of MON1 and the gate of MON2, and then respectively connected to the connection terminals NP1 and NP2.

4. The wide common mode input circuit exceeding the power rail according to claim 2, characterized in that: The second bias circuit includes a MOS tube MON6 and MOS tubes MON3, MON4, MON5_1, MON5_2, MON5_3, MON7, MON8_1, and MON8_2 whose gates and drains are short-circuited, wherein MON3 and MON6 share a gate, MON3, MON4, MON5_1, MON5_2, and MON5_3 are connected in series in sequence, and MON6, MON7, MON8_1, and MON8_2 are connected in series in sequence, and the series connection means that the source of the previous MOS tube is connected to the drain of the next MOS tube.

5. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The resistor network includes resistors R2_1, R2_2, R3_1, and R3_2. The reverse input detection terminal INN is connected to one end of the resistor R2_1 and one end of the resistor R3_1. The forward input detection terminal INP is connected to one end of the resistor R2_2 and one end of the resistor R3_2. The other end of the resistor R2_1 and the other end of R2_2 are coupled to a node P3. The other end of the resistor R3_1 and the other end of R3_2 are coupled to a node P4.

6. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The voltage drop circuit includes MOS tubes MON17_0, MON17_1, MON17_2, MON17_3, MON17_4, MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4, whose gates and drains are short-circuited respectively, wherein MON17_0, MON17_1, MON17_2, MON17_3, and MON17_4 are connected in series in sequence, and MON18_0, MON18_1, MON18_2, MON18_3, and MON18_4 are connected in series in sequence, the drain of MON17_0 is coupled to the node P3, the drain of MON18_0 is coupled to the node P4, the source of MON17_4 is coupled to the node P5, and the source of MON18_4 is coupled to the node P6.

7. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The current mirror includes MON9, MON10, MON11, and MON12, wherein MON14, MON10, and MON9 are connected in series in sequence, MON15, MON12, and MON11 are connected in series in sequence, MON9 and MON11 share a common source and a common gate, and the common source end is connected to the charge pump, and the common gate end is connected to the connection terminal NP2, and MON10 and MON12 share a common gate, and the common gate end is connected to the connection terminal NP1.

8. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The wide common mode input circuit also includes a first protection circuit for preventing the gate-source voltage of the field effect transistors MON14 and MON15 from being too large; the first protection circuit includes MOS transistors MOP2_1 and MOP2_2, wherein the gate and source of MOP2_1 are short-circuited and its source and drain are respectively connected to the gate and source of MON14, and the gate and drain of MOP2_2 are short-circuited and its source and drain are respectively connected to the source and gate of MON15.

9. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The wide common mode input circuit also includes a second protection circuit for preventing a voltage difference between the first ground terminal GND1 and the second ground terminal GND2 from exceeding a first threshold; the second protection circuit includes MOS tubes MON13_1 and MON13_2, wherein the gate source of MON13_1 is short-circuited and connected to the node P6, the drain of MON13_1 is connected to the node P5, the gate source of MON13_2 is short-circuited and connected to the node P5, and the drain of MON13_2 is connected to the node P6.

10. The wide common mode input circuit exceeding the power rail according to claim 1, characterized in that: The wide common mode input circuit further includes a third protection circuit for preventing the floating voltage V DD1 With floating voltage V DD2 The voltage difference between them exceeds the second threshold; the third protection circuit includes MOS tubes MOP1_1 and MOP1_2, wherein the gate source of MOP1_1 is short-circuited and connected to the node P3, the drain of MOP1_1 is connected to the node P4, the gate source of MOP1_2 is short-circuited and connected to the node P4, and the drain of MOP1_2 is connected to the node P3.

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