Filter and preparation method thereof

Abstract

The invention discloses a filter and a preparation method of the filter. A piezoelectric layer is provided with an opening in a connection area of adjacent series bulk acoustic resonators and parallel bulk acoustic resonators. A dielectric layer of the capacitor is filled in the opening. The series bulk acoustic resonator further comprises a first lower electrode located on the side, close to the substrate, of the piezoelectric layer and a first upper electrode located on the side, away from the substrate, of the piezoelectric layer, and the parallel bulk acoustic resonator comprises a second lower electrode located on the side, close to the substrate, of the piezoelectric layer and a second upper electrode located on the side, away from the substrate, of the piezoelectric layer. The capacitor includes a third lower electrode and a third upper electrode located in the connection region. The third upper electrode is electrically connected with the first upper electrode and the second upper electrode, and the third lower electrode is electrically connected with the second lower electrode. Thus, the capacitors are connected in parallel in the connecting areas of the adjacent series bulk acoustic resonators and the parallel bulk acoustic resonators, on one hand, in-band insertion loss and out-of-band rejection of the filter can be effectively improved, and on the other hand, redundant chip space is not occupied.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of radio frequency filtering technology, and in particular to a filter and a method for preparing the filter. Background Art

[0002] RF filters are key components in 5G and 6G wireless communications and signal processing systems, used to select or suppress signals in a specific frequency range. Film Bulk Acoustic Resonator (FBAR) is a basic component in RF filters. Generally speaking, FBARs of at least two frequencies can be connected in a ladder or lattice to form a filter with bandpass filtering function.

[0003] In the prior art, the performance of the filter can be improved by adding an external matching circuit, but it also brings many defects: first, the additional circuit occupies a certain substrate space, which will increase the package size of the filter chip. Secondly, in the prior art, conventional means can generally broaden the bandwidth and improve the performance of out-of-band suppression. However, these generally sacrifice some of the filter's insertion loss. Summary of the invention

[0004] The present invention provides a filter and a method for preparing the filter. By connecting capacitors in parallel in the connection area of ​​adjacent series BAW resonators and parallel BAW resonators, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved on the one hand, and on the other hand, no extra chip space is occupied.

[0005] In a first aspect, an embodiment of the present invention provides a filter, comprising a substrate, and at least one parallel bulk acoustic wave resonator, at least one series bulk acoustic wave resonator, and at least one capacitor located on one side of the substrate;

[0006] The series BAW resonator and the parallel BAW resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in a connection region between the adjacent series BAW resonator and the parallel BAW resonator;

[0007] The capacitor comprises a dielectric layer, and the dielectric layer is filled in the opening;

[0008] The series BAW resonator further comprises a first lower electrode located at a side of the piezoelectric layer close to the substrate and a first upper electrode located at a side of the piezoelectric layer away from the substrate, the parallel BAW resonator comprises a second lower electrode located at a side of the piezoelectric layer close to the substrate and a second upper electrode located at a side of the piezoelectric layer away from the substrate, and the capacitor comprises a third lower electrode and a third upper electrode located at the connection region;

[0009] The third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

[0010] Optionally, the first upper electrode, the second upper electrode and the third upper electrode are all in the same layer and are integrally arranged;

[0011] The first lower electrode, the second lower electrode and the third lower electrode are all arranged in the same layer, and the third lower electrode is arranged integrally with the second lower electrode.

[0012] Optionally, along the thickness direction of the substrate, the opening penetrates the piezoelectric layer, the thickness of the dielectric layer is denoted as D1, the surface area of ​​the dielectric layer is denoted as S1, and the capacitance of the capacitor is set within a first preset range by setting the thickness of the dielectric layer and the surface area of ​​the dielectric layer to satisfy a first relationship;

[0013] The first relationship includes: C=(ε1×S1) / D1, where ε1 is the dielectric constant of the dielectric layer, and C is the capacitance of the capacitor;

[0014] Alternatively, along the thickness direction of the substrate, the opening penetrates part of the piezoelectric layer, the maximum thickness of the piezoelectric layer is denoted as D2, and the capacitance of the capacitor is set within the first preset range by setting the thickness of the dielectric layer, the surface area of ​​the dielectric layer, and the maximum thickness of the piezoelectric layer to satisfy the second relationship:

[0015] The second relationship includes: C = (ε1×S1) / D1+(ε2×S1) / (D2-D1), where ε2 is the dielectric constant of the piezoelectric layer;

[0016] The first preset range includes 0pf-100pf.

[0017] Optionally, the filter comprises a ladder topology filter;

[0018] The ladder topology filter includes a first minimum repeating unit consisting of a parallel BAW resonator, a series BAW resonator and a capacitor arranged in the connection area.

[0019] Optionally, the filter comprises a lattice topology filter;

[0020] The lattice topology filter comprises a second minimum repeating unit consisting of two parallel bulk acoustic wave resonators, two series bulk acoustic wave resonators and a capacitor;

[0021] The two parallel BAW resonators include a first parallel BAW resonator and a second parallel BAW resonator, and the two series BAW resonators include a first series BAW resonator and a second series BAW resonator.

[0022] A connection area between the first parallel BAW resonator and the first series BAW resonator is a first connection area, a connection area between the second parallel BAW resonator and the second series BAW resonator is a second connection area, and the capacitor is disposed in an overlapping area between the first connection area and the second connection area.

[0023] In a second aspect, an embodiment of the present invention further provides a method for preparing a filter, which is used to prepare any filter described in the first aspect. The preparation method comprises:

[0024] providing a substrate;

[0025] At least one parallel bulk acoustic wave resonator, at least one series bulk acoustic wave resonator and at least one capacitor are prepared on one side of the substrate; wherein the series bulk acoustic wave resonator and the parallel bulk acoustic wave resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in a connection area between adjacent series bulk acoustic wave resonators and parallel bulk acoustic wave resonators; the capacitor includes a dielectric layer, and the dielectric layer is filled in the opening; the series bulk acoustic wave resonator also includes a first lower electrode located on a side of the piezoelectric layer close to the substrate and a first upper electrode on a side of the piezoelectric layer away from the substrate, the parallel bulk acoustic wave resonator includes a second lower electrode located on a side of the piezoelectric layer close to the substrate and a second upper electrode on a side of the piezoelectric layer away from the substrate, and the capacitor includes a third lower electrode and a third upper electrode located in the connection area; the third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

[0026] Optionally, providing a substrate includes:

[0027] Preparing a plurality of cavities in the substrate and filling the cavities with a first sacrificial layer, wherein along the thickness direction of the substrate, the cavities at least partially overlap with the first lower electrode or the second lower electrode;

[0028] A seed layer is prepared on a side of the cavity away from the substrate.

[0029] Optionally, preparing at least one parallel bulk acoustic wave resonator, at least one series bulk acoustic wave resonator and at least one capacitor on one side of the substrate comprises:

[0030] Preparing a whole lower electrode layer on one side of the seed layer, and patterning the whole lower electrode layer to form the first lower electrode layer, the second lower electrode layer and the third lower electrode layer, wherein the second lower electrode layer is integrally arranged with the third lower electrode layer;

[0031] The piezoelectric layer is prepared on a side of the entire lower electrode layer away from the substrate, and the opening is etched in the connection area of ​​the piezoelectric layer, and the opening penetrates at least a portion of the piezoelectric layer along the thickness direction of the substrate;

[0032] filling the dielectric layer in the opening;

[0033] Preparing a second sacrificial layer on a side of the piezoelectric layer away from the substrate, and patterning the second sacrificial layer;

[0034] The piezoelectric layer is etched downward to form a first via hole and a second via hole in the piezoelectric layer, wherein the first via hole and the second via hole are staggered with the cavity along the thickness direction of the substrate, and the first via hole at least partially overlaps with the first lower electrode, and the second via hole at least partially overlaps with the second lower electrode.

[0035] Optionally, after etching downward the piezoelectric layer to form a first via hole and a second via hole in the piezoelectric layer, the method further includes:

[0036] Depositing a thickening layer on a side of the second sacrificial layer away from the substrate, and patterning the thickening layer so that the thickening layer at least covers the second sacrificial layer, the dielectric layer, the first via hole, and the second via hole;

[0037] A whole upper electrode layer is deposited on a side of the thickened layer away from the substrate to form a first upper electrode layer, a second upper electrode layer and a third upper electrode layer which are integrally arranged.

[0038] Optionally, after depositing a whole upper electrode layer on a side of the thickened layer away from the substrate, the method further comprises:

[0039] A mass load layer is prepared on a side of the second upper electrode away from the substrate, wherein the mass load layer at least partially overlaps with the second lower electrode layer along a thickness direction of the substrate;

[0040] Depositing a whole passivation layer on a side of the mass load layer away from the substrate, and patterning the whole passivation layer so that the passivation layer exposes a portion of the piezoelectric layer in the first region and a portion of the piezoelectric layer in the second region, and punching a portion of the piezoelectric layer in the first region downward to form a third via hole, and punching a portion of the piezoelectric layer in the second region downward to form a fourth via hole, wherein the third via hole at least partially overlaps with the first lower electrode, and the fourth via hole at least partially overlaps with the second lower electrode;

[0041] Preparing a protective layer on the first via hole and the second via hole;

[0042] The cavity and the first sacrificial layer are released to prepare at least one parallel BAW resonator, at least one series BAW resonator, and at least one capacitor.

[0043] The filter in the embodiment of the present invention includes at least one parallel body acoustic wave resonator, at least one series body acoustic wave resonator and at least one capacitor located on one side of the substrate. The series body acoustic wave resonator and the parallel body acoustic wave resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in the connection area between adjacent series body acoustic wave resonators and parallel body acoustic wave resonators. The capacitor includes a dielectric layer, and the dielectric layer is filled in the opening. The series body acoustic wave resonator also includes a first lower electrode located on the side of the piezoelectric layer close to the substrate and a first upper electrode on the side of the piezoelectric layer away from the substrate. The parallel body acoustic wave resonator includes a second lower electrode located on the side of the piezoelectric layer close to the substrate and a second upper electrode on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection area. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode. In this way, by connecting capacitors in parallel in the connection area between adjacent series BAW resonators and parallel BAW resonators, on the one hand, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved. On the other hand, setting capacitors in the connection area will not occupy excess chip space, which is conducive to realizing the miniaturization of the filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a filter provided by an embodiment of the present invention;

[0045] Figure 2 yes Figure 1 The equivalent circuit diagram of the filter provided in;

[0046] Figure 3 yes Figure 1 A schematic cross-sectional view along the A-A' direction;

[0047] Figure 4 is a schematic diagram of the structure of another filter provided by an embodiment of the present invention;

[0048] Figure 5 yes Figure 4 The equivalent circuit diagram of the filter provided in;

[0049] Figure 6 It is a schematic flow chart of a method for preparing a filter provided by an embodiment of the present invention;

[0050] Figure 7It is a schematic flow chart of another method for preparing a filter provided by an embodiment of the present invention;

[0051] Figure 8 It is a schematic diagram of a preparation process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0053] Figure 1 A schematic diagram of the structure of a filter provided by an embodiment of the present invention, Figure 2 yes Figure 1 The equivalent circuit diagram of the filter provided in Figure 3 yes Figure 1 A schematic cross-sectional view along the A-A' direction. Figure 1-Figure 3 The filter includes a substrate 01, and at least one parallel bulk acoustic wave resonator 20, at least one series bulk acoustic wave resonator 10, and at least one capacitor 30 located on one side of the substrate 01. The series bulk acoustic wave resonator 10 and the parallel bulk acoustic wave resonator 20 both include a piezoelectric layer 40, and the piezoelectric layer 40 is provided with an opening 410 in the connection area B1 between the adjacent series bulk acoustic wave resonator 10 and the parallel bulk acoustic wave resonator 20. The capacitor 30 includes a dielectric layer 310, and the dielectric layer 310 is filled in the opening 410. The series bulk acoustic wave resonator 10 also includes a first lower electrode 110 located on the side of the piezoelectric layer 40 close to the substrate 01 and a first upper electrode 120 on the side of the piezoelectric layer 40 away from the substrate 01. The parallel bulk acoustic wave resonator 20 includes a second lower electrode 210 located on the side of the piezoelectric layer 40 close to the substrate 01 and a second upper electrode 220 on the side of the piezoelectric layer 40 away from the substrate 01. The capacitor 30 includes a third lower electrode 320 and a third upper electrode 330 located in the connection area B1. The third upper electrode 330 is electrically connected to the first upper electrode 120 and the second upper electrode 220 , respectively, and the third lower electrode 320 is electrically connected to the second lower electrode 220 .

[0054] For details, see Figure 1-Figure 3 The filter includes at least one parallel BAW resonator 20, at least one series BAW resonator 10, and at least one capacitor 30. Exemplarily, Figure 1The topological structure of the ladder structure is used as an example for explanation, that is, the filter includes a plurality of parallel BAW resonators 20 and a plurality of series BAW resonators 10. Among them, the adjacent parallel BAW resonators 20 and the series BAW resonators 10 share the same piezoelectric layer 40, and the upper electrodes of the parallel BAW resonators 10 and the series BAW resonators 10 are electrically connected to each other, so that the adjacent parallel BAW resonators 20 and the series BAW resonators 10 are connected to form a minimum repeating unit of the filter, ensuring that the filter can achieve the bandpass filtering function.

[0055] In the prior art, in order to broaden the bandwidth of the filter, it is usually achieved by adding an external matching circuit, such as connecting independent capacitors or inductors in series or in parallel. However, on the one hand, the independently set capacitors or inductors occupy a certain chip space, which will increase the package size of the filter. On the other hand, although the independently set capacitors or capacitors and inductors can broaden the bandwidth and improve out-of-band suppression, they will sacrifice some of the filter's insertion loss, which will have an adverse effect on the filter.

[0056] To this end, the embodiment of the present invention connects the capacitor 10 in parallel at the connection area B1 of the adjacent series BAW resonator 10 and the parallel BAW resonator 20. Specifically, since the adjacent series BAW resonator 10 and the parallel BAW resonator 20 share the same piezoelectric layer 40, an opening 410 is provided in the piezoelectric layer 40 at the connection area B1 of the series BAW resonator 10 and the parallel BAW resonator 20, and a dielectric layer is filled in the opening 410 to form the dielectric layer 310 of the capacitor 30. In addition, the series BAW resonator 10 further includes a first lower electrode 110 and a first upper electrode 120. The first lower electrode 110 is located at a side of the piezoelectric layer 40 in the series BAW resonator 10 close to the substrate 01, and the first upper electrode 120 is located at a side of the piezoelectric layer 40 in the series BAW resonator 10 away from the substrate 01. The parallel BAW resonator 20 further includes a second lower electrode 210 and a second upper electrode 220. Among them, the second lower electrode 210 is located on the side of the piezoelectric layer 40 in the parallel bulk acoustic wave resonator 20 close to the substrate 01, and the second upper electrode 220 is located on the side of the piezoelectric layer 40 in the parallel bulk acoustic wave resonator 20 away from the substrate 01. In one embodiment, the first upper electrode 120 and the second upper electrode 220 can be integrally arranged, that is, formed in the same process. Then, the first upper electrode 120 and the second upper electrode 220 in the connection area B1 can be used as the third upper electrode 230 of the capacitor 30, realizing the electrical connection between the first upper electrode 120, the second upper electrode 220 and the third upper electrode 330. The first lower electrode 110 and the second lower electrode 210 are independent, that is, the first lower electrode 110 and the second lower electrode 210 are insulated, and then the third lower electrode 320 of the capacitor 30 can be prepared on the side of the dielectric layer 310 close to the substrate 01 in the connection area B1, and the third lower electrode 320 is electrically connected to the second lower electrode 210, so that the capacitor 30 is arranged in parallel in the connection area B1 of the adjacent series BAW resonator 10 and the parallel BAW resonator 20. In this way, the arrangement of the capacitor 30 is based on the original film layer of the connection area B1, that is, the capacitor 30 is an area with an inductance function arranged using the original film layer, and is not an introduced new independent device (physical capacitor). Since no independent capacitor or inductor device is introduced, on the one hand, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved, and on the other hand, it will not occupy excess chip space, which is conducive to realizing the small size of the filter.

[0057] It should be noted that, in the embodiment of the present invention, since the substrate is disposed in the filter, and a cavity is further disposed in the substrate 01, the normal operation of the filter can be ensured.

[0058] It should also be noted that Figure 1-Figure 3The filter with a ladder topology structure is only used as an example for illustration, but is not limited to this. In other embodiments, the filter may also have other types of topologies, and those skilled in the art may set them as needed.

[0059] In summary, the filter in the embodiment of the present invention includes at least one parallel body acoustic wave resonator, at least one series body acoustic wave resonator and at least one capacitor located on one side of the substrate. The series body acoustic wave resonator and the parallel body acoustic wave resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in the connection area between adjacent series body acoustic wave resonators and parallel body acoustic wave resonators. The capacitor includes a dielectric layer, and the dielectric layer is filled in the opening. The series body acoustic wave resonator also includes a first lower electrode located on the side of the piezoelectric layer close to the substrate and a first upper electrode on the side of the piezoelectric layer away from the substrate. The parallel body acoustic wave resonator includes a second lower electrode located on the side of the piezoelectric layer close to the substrate and a second upper electrode on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection area. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode. In this way, by connecting capacitors in parallel in the connection area between adjacent series BAW resonators and parallel BAW resonators, on the one hand, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved. On the other hand, setting capacitors in the connection area will not occupy excess chip space, which is conducive to realizing the miniaturization of the filter.

[0060] Optionally, based on the above embodiment, continue to refer to Figure 3 , the first upper electrode 120, the second upper electrode 220 and the third upper electrode 330 are all arranged in the same layer and are integrally arranged. During the production, the first upper electrode 120, the second upper electrode 220 and the third upper electrode 330 can be produced and formed in the same production process using the same mask, and there is no need to produce masks for the first upper electrode 120, the second upper electrode 220 and the third upper electrode 330 respectively, which saves costs, reduces the number of processes and improves production efficiency. The first lower electrode 110, the second lower electrode 210 and the third lower electrode 320 are all arranged in the same layer, and the third lower electrode 320 is integrally arranged with the second lower electrode 210. During the production, the first lower electrode 110, the second lower electrode 210 and the third lower electrode 320 can be produced and formed in the same production process using the same mask, and there is no need to produce masks for the first lower electrode 110, the second lower electrode 210 and the third lower electrode 320 respectively, which saves costs, reduces the number of processes and improves production efficiency.

[0061] Optionally, based on the above embodiment, continue to refer to Figure 3, along the thickness direction of the substrate 01, the opening 410 penetrates the piezoelectric layer 40, the thickness of the dielectric layer 310 is D1, the surface area of ​​the dielectric layer 310 is S1, and the capacitance of the capacitor 30 is set within a first preset range by setting the thickness of the dielectric layer 310 and the surface area of ​​the dielectric layer 310 to satisfy a first relationship. The first relationship includes: C = (ε1×S1) / D1, where ε1 is the dielectric constant of the dielectric layer 310, and C is the capacitance of the capacitor 30. Specifically, when the opening 410 penetrates the piezoelectric layer 40, the capacitance of the capacitor 30 is related to the thickness D1 and the surface area S1 of the dielectric layer 310, that is, the capacitance of the capacitor 30 can be made within the range of 0pf-100pf by adjusting the thickness of the dielectric layer 310 and the surface area of ​​the dielectric layer 310 to satisfy the first relationship, thereby ensuring that when the capacitor 30 is set in parallel in the connection area B1, the in-band insertion loss and out-of-band suppression of the filter are effectively improved.

[0062] In another embodiment, along the thickness direction of the substrate 01, the opening 410 penetrates part of the piezoelectric layer 40, and the maximum thickness of the piezoelectric layer 40 is denoted as D2. The capacitance of the capacitor 30 is set within the first preset range by setting the thickness of the dielectric layer 310, the surface area of ​​the dielectric layer 310, and the maximum thickness of the piezoelectric layer 40 to satisfy the second relationship. The second relationship includes: C = (ε1×S1) / D1+(ε2×S1) / (D2-D1), where ε2 is the dielectric constant of the piezoelectric layer 40. Specifically, when the opening 410 penetrates part of the piezoelectric layer 40, at this time, between the third upper electrode 320 and the third lower electrode 330, not only the dielectric layer 310 but also part of the piezoelectric layer 40 is included, and thus the capacitance of the capacitor 30 is related to the thickness D1 and surface area S1 of the dielectric layer 310, and the thickness (D2-D1) and surface area (S1) of the part of the piezoelectric layer 40 overlapping with the opening 410, that is, the thickness D1 and surface area S1 of the dielectric layer 310, and the thickness (D2-D1) and surface area (S1) of the part of the piezoelectric layer 40 overlapping with the opening 410 can be adjusted to satisfy the second relationship to set the capacitance of the capacitor 30 within the range of 0pf-100pf, thereby ensuring that when the capacitor 30 is arranged in parallel in the connection area B1, the in-band insertion loss and out-of-band suppression of the filter are effectively improved.

[0063] Optionally, based on the above embodiment, continue to refer to Figure 1-Figure 3 The filter includes a ladder topology filter. The ladder topology filter includes a first minimum repeating unit consisting of a parallel BAW resonator 20, a series BAW resonator 10, and a capacitor 30 disposed in the connection area B1. Specifically, Figure 1As shown, a capacitor 30 is arranged in parallel in the connection area B1 of the adjacent parallel BAW resonator 20 and the series BAW resonator 10 to form a first minimum repeating unit, and the ladder topology structure filter includes a plurality of first minimum repeating units. Thus, on the basis of ensuring the original characteristics of the ladder topology structure filter, the in-band insertion loss and out-of-band suppression of the ladder topology structure filter are improved.

[0064] Optional, Figure 4 is a schematic diagram of the structure of another filter provided by an embodiment of the present invention, Figure 5 yes Figure 4 The equivalent circuit diagram of the filter is provided in . Figure 4 and Figure 5 , the filter includes a lattice topology filter. The lattice topology filter includes a second minimum repeating unit consisting of two parallel BAW resonators 20, two series BAW resonators 10 and a capacitor 30. Among them, the two parallel BAW resonators 20 include a first parallel BAW resonator 201 and a second parallel BAW resonator 202, and the two series BAW resonators 10 include a first series BAW resonator 101 and a second series BAW resonator 102. The connection area B1 between the first parallel BAW resonator 201 and the first series BAW resonator 101 is a first connection area B11, the connection area B1 between the second parallel BAW resonator 202 and the second series BAW resonator 102 is a second connection area B12, and the capacitor 30 is arranged in the overlapping area of ​​the first connection area B11 and the second connection area B12.

[0065] Specifically, Figure 4 and Figure 5 As shown, the lattice topology filter includes two series BAW resonators 10 on the upper side, namely, a first series BAW resonator 101 and a second series BAW resonator 102, and two parallel BAW resonators 20 on the lower side, namely, a first parallel BAW resonator 201 and a second parallel BAW resonator 202. The two series BAW resonators 10 on the upper side are cross-electrically connected with the two parallel BAW resonators 20 on the lower side, that is, the connection area B1 between the first parallel BAW resonator 201 and the first series BAW resonator 101 is the first connection area B11, and the connection area B1 between the second parallel BAW resonator 202 and the second series BAW resonator 102 is the second connection area B12, and the capacitor 30 is disposed in the overlapping area of ​​the first connection area B11 and the second connection area B12. In this way, by sharing the same capacitor 30 between two parallel BAW resonators 20 and two series BAW resonators 10 in the second minimum repeating unit, the in-band insertion loss and out-of-band suppression of the ladder topology filter are improved while maintaining the original characteristics of the lattice topology filter.

[0066] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a filter. Figure 6 is a flow chart of a method for preparing a filter provided by an embodiment of the present invention. Figure 6 , the preparation method comprises:

[0067] S110 , providing a substrate.

[0068] Specifically, the material of the substrate may be sapphire (Al2O3), silicon carbide (SiC), silicon (Si), etc. The embodiment of the present invention does not limit the specific material of the substrate, and those skilled in the art may set it as needed.

[0069] S120, preparing at least one parallel bulk acoustic wave resonator, at least one series bulk acoustic wave resonator, and at least one capacitor on one side of the substrate.

[0070] Specifically, the series BAW resonator and the parallel BAW resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in the connection area between adjacent series BAW resonators and parallel BAW resonators. The capacitor includes a dielectric layer, and the dielectric layer is filled in the opening. The series BAW resonator also includes a first lower electrode located on the side of the piezoelectric layer close to the substrate and a first upper electrode on the side of the piezoelectric layer away from the substrate. The parallel BAW resonator includes a second lower electrode located on the side of the piezoelectric layer close to the substrate and a second upper electrode on the side of the piezoelectric layer away from the substrate, and the capacitor includes a third lower electrode and a third upper electrode located in the connection area. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

[0071] Exemplarily, a topological structure of a ladder structure is used as an example for explanation, that is, the filter includes a plurality of parallel bulk acoustic wave resonators and a plurality of series bulk acoustic wave resonators. The embodiment of the present invention connects capacitors in parallel in the connection area between adjacent series bulk acoustic wave resonators and parallel bulk acoustic wave resonators. Specifically, since adjacent series bulk acoustic wave resonators and parallel bulk acoustic wave resonators share the same piezoelectric layer, an opening can be set in the piezoelectric layer in the connection area between the series bulk acoustic wave resonator and the parallel bulk acoustic wave resonator, and a dielectric layer is filled in the opening to form a dielectric layer of the capacitor. In addition, the series bulk acoustic wave resonator also includes a first lower electrode and a first upper electrode. Among them, the first lower electrode is located on the side of the piezoelectric layer in the series bulk acoustic wave resonator close to the substrate, and the first upper electrode is located on the side of the piezoelectric layer in the series bulk acoustic wave resonator away from the substrate. The parallel bulk acoustic wave resonator also includes a second lower electrode and a second upper electrode. Among them, the second lower electrode is located on the side of the piezoelectric layer in the parallel bulk acoustic wave resonator close to the substrate, and the second upper electrode is located on the side of the piezoelectric layer in the parallel bulk acoustic wave resonator away from the substrate. In one embodiment, the first upper electrode and the second upper electrode can be integrally arranged, that is, formed in the same process. Then, the first upper electrode and the second upper electrode in the connection area can be used as the third upper electrode of the capacitor, so as to realize the electrical connection between the first upper electrode, the second upper electrode and the third upper electrode. The first lower electrode and the second lower electrode are independent, that is, the first lower electrode and the second lower electrode are insulated, and then the third lower electrode of the capacitor can be prepared on the side of the dielectric layer close to the substrate in the connection area, and the third lower electrode is electrically connected to the second lower electrode, so that the capacitor is arranged in parallel in the connection area of ​​the adjacent series body acoustic wave resonator and the parallel body acoustic wave resonator. In this way, the arrangement of the capacitor is based on the original film layer of the connection area, that is, the capacitor is an area with inductance function arranged by using the original film layer, and is not a new independent device (physical capacitor) introduced. Since no independent capacitor device or inductor device is introduced, on the one hand, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved, and on the other hand, it will not occupy extra chip space, which is conducive to realizing the small size of the filter.

[0072] In summary, in the embodiment of the present invention, the piezoelectric layer is provided with an opening in the connection area between the adjacent series BAW resonator and the parallel BAW resonator. The dielectric layer of the capacitor is filled in the opening. The series BAW resonator also includes a first lower electrode located on the side of the piezoelectric layer close to the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate. The parallel BAW resonator includes a second lower electrode located on the side of the piezoelectric layer close to the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection area. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode, respectively, and the third lower electrode is electrically connected to the second lower electrode. In this way, by connecting the capacitor in parallel in the connection area between the adjacent series BAW resonator and the parallel BAW resonator, on the one hand, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved, and on the other hand, no extra chip space is occupied.

[0073] Optional, Figure 7 is a flow chart of another method for preparing a filter provided by an embodiment of the present invention, Figure 8 Schematic diagram of a preparation process provided by an embodiment of the present invention. Figure 7 and Figure 8 , the preparation method comprises:

[0074] S210, preparing a plurality of cavities in the substrate, and filling the cavities with a first sacrificial layer, and preparing a seed layer on a side of the cavity away from the substrate.

[0075] Specifically, holes are dug in the substrate 01 to form cavities in the regions of the substrate 01 corresponding to the series BAW resonator 10 and the parallel BAW resonator 20, respectively. Exemplarily, along the thickness direction of the substrate 01, when the cavity at least partially overlaps with the first lower electrode 110, the cavity corresponds to the series BAW resonator 10, and when the cavity at least partially overlaps with the second lower electrode 210, the cavity corresponds to the parallel BAW resonator 20. And fill the cavity with a first sacrificial layer 510. Among them, the sacrificial layer 510 material may include SiO2, silicate glass PSG, Si3N4, etc. Then, a seed layer 520 is deposited on the side of the cavity (first sacrificial layer 510) away from the substrate 01, and the seed layer 520 can ensure that the piezoelectric film formed subsequently has a good crystal orientation.

[0076] S220. Prepare an entire lower electrode layer on one side of the seed layer, and pattern the entire lower electrode layer to form a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer. Prepare a piezoelectric layer on a side of the entire lower electrode layer away from the substrate, etch openings in the connection area of ​​the piezoelectric layer, and fill the openings with a dielectric layer.

[0077] Specifically, a whole lower electrode layer is deposited on the side of the seed layer 520 away from the substrate 01, wherein the material of the whole lower electrode layer can be at least one of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd), etc. Then, the whole lower electrode layer is patterned to form a first lower electrode 110 at a corresponding position of the series bulk acoustic wave resonator 10, a second lower electrode 210 at a corresponding position of the parallel bulk acoustic wave resonator 20, and a third lower electrode 320 at a corresponding position of the capacitor 30. It can be understood that, as Figure 8 In the illustrated embodiment, the second lower electrode 210 and the third lower electrode 320 are integrally arranged. Then, a whole layer of piezoelectric layer 40 is prepared on one side of the first lower electrode 110 and the second lower electrode 210, and an opening 410 is formed by etching in the connection area B1 in the piezoelectric layer 40. Along the thickness direction of the substrate 01, the opening 410 penetrates at least part of the piezoelectric layer 40. Among them, the material of the piezoelectric layer 40 can be at least one of aluminum nitride AlN, lithium niobate LiNbO3, lithium tantalate LiTaO3, lead zirconate titanate PZT, zinc oxide ZnO, scandium-doped aluminum nitride ScAlN, quartz crystal Quatz, lead magnesium niobate (PMN), and lead fluoride (PbTiO3). Finally, a dielectric layer material is filled in the opening 410 to form the dielectric layer 310 of the capacitor 30 in the opening 410.

[0078] S230 , preparing a second sacrificial layer on a side of the piezoelectric layer away from the substrate, patterning the second sacrificial layer, and etching downward the piezoelectric layer to form a first via hole and a second via hole in the piezoelectric layer.

[0079] Specifically, a second sacrificial layer 530 is deposited on the side of the piezoelectric layer 40 away from the substrate 01, and the second sacrificial layer 530 is patterned to form a symmetrical second sacrificial layer pattern on the series BAW resonator 10 and the parallel BAW resonator 20, respectively. Then, a first via hole 540 is formed in the piezoelectric layer 40 at a position corresponding to the series BAW resonator 10, and the first via hole 540 is staggered with the cavity along the thickness direction of the substrate 01, and a second via hole 550 is formed in the piezoelectric layer 40 at a position corresponding to the parallel BAW resonator 20, and the second via hole 550 is staggered with the cavity along the thickness direction of the substrate 01. The first via hole 540 and the second via hole 550 expose the first lower electrode 110 and the second lower electrode 210, respectively.

[0080] S240, depositing a thickening layer on the side of the second sacrificial layer away from the substrate, and patterning the thickening layer, and depositing a whole upper electrode layer on the side of the thickening layer away from the substrate to form an integrated first upper electrode layer, a second upper electrode layer, and a third upper electrode layer.

[0081] Specifically, a thickening layer 560 is deposited on the side of the second sacrificial layer 530 away from the substrate 01, and the thickening layer 560 is patterned so that the thickening layer 560 at least covers the second sacrificial layer 530, the dielectric layer 310, the first via hole 540 and the second via hole 550. In this way, the Q value of the filter is improved by providing the thickening layer 560. Then, a whole upper electrode layer is deposited on the side of the thickening layer 560 away from the substrate, and the whole upper electrode layer is patterned to form an integrally arranged first upper electrode layer 120, a second upper electrode layer 220 and a third upper electrode layer 330. The material of the whole upper electrode layer can be at least one of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd) and the like.

[0082] S250, preparing a mass load layer on the side of the second upper electrode away from the substrate, depositing a whole passivation layer on the side of the mass load layer away from the substrate, and patterning the whole passivation layer to expose part of the piezoelectric layer in the first area and part of the piezoelectric layer in the second area, and drilling downwards through part of the piezoelectric layer in the first area to form a third via hole, and drilling downwards through part of the piezoelectric layer in the second area to form a fourth via hole.

[0083] Specifically, a mass load layer 570 is prepared on the side of the second upper electrode 220 away from the substrate 01, and along the thickness direction of the substrate 01, the mass load layer 570 and the second lower electrode layer 210 are at least partially overlapped, that is, the mass load layer 570 is arranged on the corresponding parallel body acoustic wave resonator 20 to adjust the frequency of the parallel body acoustic wave resonator 20. Then, a whole passivation layer is deposited on the side of the mass load layer 570 away from the substrate 01, and the surface placement device is protected from oxidation by the whole passivation layer. The whole passivation layer is patterned so that the patterned passivation layer 580 exposes part of the piezoelectric layer in the first area and part of the piezoelectric layer in the second area, and the part of the piezoelectric layer in the first area is punched downward to form a third via hole 610, and the part of the piezoelectric layer in the second area is punched downward to form a fourth via hole 620, wherein the third via hole 610 and the fourth via hole 640 are release holes. Exemplarily, the third via hole 610 at least partially overlaps with the first lower electrode 110, that is, the third via hole 610 is arranged corresponding to the series BAW resonator 10, and the fourth via hole 620 at least partially overlaps with the second lower electrode 210, that is, the fourth via hole 620 is arranged corresponding to the parallel BAW resonator 20. The embodiment of the present invention does not limit the specific process sequence of the release hole, and those skilled in the art may need to set it.

[0084] S260, preparing a protective layer on the first via hole and the second via hole, releasing the cavity and the first sacrificial layer, so as to form at least one parallel BAW resonator, at least one series BAW resonator and at least one capacitor.

[0085] In summary, in the embodiment of the present invention, the piezoelectric layer is provided with an opening in the connection area between the adjacent series BAW resonator and the parallel BAW resonator. The dielectric layer of the capacitor is filled in the opening. The series BAW resonator also includes a first lower electrode located on the side of the piezoelectric layer close to the substrate and a first upper electrode located on the side of the piezoelectric layer away from the substrate. The parallel BAW resonator includes a second lower electrode located on the side of the piezoelectric layer close to the substrate and a second upper electrode located on the side of the piezoelectric layer away from the substrate. The capacitor includes a third lower electrode and a third upper electrode located in the connection area. The third upper electrode is electrically connected to the first upper electrode and the second upper electrode, respectively, and the third lower electrode is electrically connected to the second lower electrode. In this way, by connecting the capacitor in parallel in the connection area between the adjacent series BAW resonator and the parallel BAW resonator, on the one hand, the in-band insertion loss and out-of-band suppression of the filter can be effectively improved, and on the other hand, no extra chip space is occupied.

[0086] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A filter, characterized in that: The invention comprises a substrate, and at least one parallel bulk acoustic wave resonator, at least one series bulk acoustic wave resonator and at least one capacitor located on one side of the substrate; The series BAW resonator and the parallel BAW resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in a connection region between the adjacent series BAW resonator and the parallel BAW resonator; The capacitor comprises a dielectric layer, and the dielectric layer is filled in the opening; The series BAW resonator further comprises a first lower electrode located at a side of the piezoelectric layer close to the substrate and a first upper electrode located at a side of the piezoelectric layer away from the substrate, the parallel BAW resonator comprises a second lower electrode located at a side of the piezoelectric layer close to the substrate and a second upper electrode located at a side of the piezoelectric layer away from the substrate, and the capacitor comprises a third lower electrode and a third upper electrode located at the connection region; The third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

2. The filter according to claim 1, characterized in that The first upper electrode, the second upper electrode and the third upper electrode are all in the same layer and are integrally arranged; The first lower electrode, the second lower electrode and the third lower electrode are all arranged in the same layer, and the third lower electrode is arranged integrally with the second lower electrode.

3. The filter according to claim 1, characterized in that Along the thickness direction of the substrate, the opening penetrates the piezoelectric layer, the thickness of the dielectric layer is denoted as D1, the surface area of ​​the dielectric layer is denoted as S1, and the capacitance of the capacitor is set within a first preset range by setting the thickness of the dielectric layer and the surface area of ​​the dielectric layer to satisfy a first relationship; The first relationship includes: C=(ε1×S1) / D1, where ε1 is the dielectric constant of the dielectric layer, and C is the capacitance of the capacitor; Alternatively, along the thickness direction of the substrate, the opening penetrates part of the piezoelectric layer, the maximum thickness of the piezoelectric layer is denoted as D2, and the capacitance of the capacitor is set within the first preset range by setting the thickness of the dielectric layer, the surface area of ​​the dielectric layer, and the maximum thickness of the piezoelectric layer to satisfy the second relationship: The second relationship includes: C = (ε1×S1) / D1+(ε2×S1) / (D2-D1), where ε2 is the dielectric constant of the piezoelectric layer; The first preset range includes 0pf-100pf.

4. The filter according to claim 1, characterized in that The filter comprises a ladder topology filter; The ladder topology filter includes a first minimum repeating unit consisting of a parallel BAW resonator, a series BAW resonator and a capacitor arranged in the connection area.

5. The filter according to claim 1, characterized in that The filter comprises a lattice topology filter; The lattice topology filter comprises a second minimum repeating unit consisting of two parallel bulk acoustic wave resonators, two series bulk acoustic wave resonators and a capacitor; The two parallel BAW resonators include a first parallel BAW resonator and a second parallel BAW resonator, and the two series BAW resonators include a first series BAW resonator and a second series BAW resonator. A connection area between the first parallel BAW resonator and the first series BAW resonator is a first connection area, a connection area between the second parallel BAW resonator and the second series BAW resonator is a second connection area, and the capacitor is disposed in an overlapping area between the first connection area and the second connection area.

6. A method for preparing a filter, characterized in that: Used to prepare the filter according to any one of claims 1 to 5; The preparation method comprises: providing a substrate; At least one parallel bulk acoustic wave resonator, at least one series bulk acoustic wave resonator and at least one capacitor are prepared on one side of the substrate; wherein the series bulk acoustic wave resonator and the parallel bulk acoustic wave resonator both include a piezoelectric layer, and the piezoelectric layer is provided with an opening in a connection area between adjacent series bulk acoustic wave resonators and parallel bulk acoustic wave resonators; the capacitor includes a dielectric layer, and the dielectric layer is filled in the opening; the series bulk acoustic wave resonator also includes a first lower electrode located on a side of the piezoelectric layer close to the substrate and a first upper electrode on a side of the piezoelectric layer away from the substrate, the parallel bulk acoustic wave resonator includes a second lower electrode located on a side of the piezoelectric layer close to the substrate and a second upper electrode on a side of the piezoelectric layer away from the substrate, and the capacitor includes a third lower electrode and a third upper electrode located in the connection area; the third upper electrode is electrically connected to the first upper electrode and the second upper electrode respectively, and the third lower electrode is electrically connected to the second lower electrode.

7. The preparation method according to claim 6, characterized in that: The providing of the substrate comprises: Preparing a plurality of cavities in the substrate and filling the cavities with a first sacrificial layer, wherein along the thickness direction of the substrate, the cavities at least partially overlap with the first lower electrode or the second lower electrode; A seed layer is prepared on a side of the cavity away from the substrate.

8. The preparation method according to claim 7, characterized in that: The step of preparing at least one parallel BAW resonator, at least one series BAW resonator and at least one capacitor on one side of the substrate comprises: Preparing a whole lower electrode layer on one side of the seed layer, and patterning the whole lower electrode layer to form the first lower electrode layer, the second lower electrode layer and the third lower electrode layer, wherein the second lower electrode layer is integrally arranged with the third lower electrode layer; The piezoelectric layer is prepared on a side of the entire lower electrode layer away from the substrate, and the opening is etched in the connection area of ​​the piezoelectric layer, and the opening penetrates at least a portion of the piezoelectric layer along the thickness direction of the substrate; filling the dielectric layer in the opening; Preparing a second sacrificial layer on a side of the piezoelectric layer away from the substrate, and patterning the second sacrificial layer; The piezoelectric layer is etched downward to form a first via hole and a second via hole in the piezoelectric layer, wherein the first via hole and the second via hole are staggered with the cavity along the thickness direction of the substrate, and the first via hole at least partially overlaps with the first lower electrode, and the second via hole at least partially overlaps with the second lower electrode.

9. The preparation method according to claim 8, characterized in that: After etching downward the piezoelectric layer to form a first via hole and a second via hole in the piezoelectric layer, the method further includes: Depositing a thickening layer on a side of the second sacrificial layer away from the substrate, and patterning the thickening layer so that the thickening layer at least covers the second sacrificial layer, the dielectric layer, the first via hole, and the second via hole; A whole upper electrode layer is deposited on a side of the thickened layer away from the substrate to form a first upper electrode layer, a second upper electrode layer and a third upper electrode layer which are integrally arranged.

10. The preparation method according to claim 9, characterized in that: After depositing a whole upper electrode layer on a side of the thickened layer away from the substrate, the method further comprises: A mass load layer is prepared on a side of the second upper electrode away from the substrate, wherein the mass load layer at least partially overlaps with the second lower electrode layer along a thickness direction of the substrate; Depositing a whole passivation layer on a side of the mass load layer away from the substrate, and patterning the whole passivation layer so that the passivation layer exposes a portion of the piezoelectric layer in the first region and a portion of the piezoelectric layer in the second region, and punching a portion of the piezoelectric layer in the first region downward to form a third via hole, and punching a portion of the piezoelectric layer in the second region downward to form a fourth via hole, wherein the third via hole at least partially overlaps with the first lower electrode, and the fourth via hole at least partially overlaps with the second lower electrode; Preparing a protective layer on the first via hole and the second via hole; The cavity and the first sacrificial layer are released to prepare at least one parallel BAW resonator, at least one series BAW resonator, and at least one capacitor.

Images