Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate and a word line structure. The substrate includes an array region and a peripheral region surrounding the array region. The substrate includes at least one active region isolated by a shallow trench isolation structure. The word line structures penetrate through the shallow trench isolation structures and the active regions in the first direction, and the multiple word line structures extend in the first direction and are arranged in the second direction. The word line structure comprises a first word line layer, a first metal oxide layer and a second metal oxide layer. The first word line layer comprises a first part and a second part, and the first part is located on the array region; the second portion is on the peripheral region, wherein an upper surface of the second portion is lower than an upper surface of the first portion in a direction perpendicular to the substrate. The first metal oxide layer is located on the first portion. The second metal oxide layer is located on the second part, and the thickness of the second metal oxide layer is larger than that of the first metal oxide layer. The performance of the memory device can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] The memory device generally includes an array region and a peripheral region surrounding the array region. A memory array can be formed in the array region. Contact plugs can be formed in the peripheral region, and the contact plugs can connect the word line structure with the upper logic circuit in the peripheral region, thereby providing signals for the memory array.

[0003] However, the performance of existing memory devices needs to be further improved. Summary of the invention

[0004] Based on this, the present application provides a semiconductor structure and a preparation method thereof that can improve the performance of a storage device.

[0005] A semiconductor structure comprising:

[0006] A substrate, comprising an array region and a peripheral region surrounding the array region, wherein the substrate comprises at least one active region isolated by a shallow trench isolation structure;

[0007] A word line structure passes through the shallow trench isolation structure and the active area along a first direction, and a plurality of the word line structures extend along the first direction and are arranged along a second direction, and the second direction intersects the first direction;

[0008] Furthermore, the word line structure includes:

[0009] A first word line layer, comprising a first portion and a second portion, wherein the first portion is located on the array region; the second portion is located on the peripheral region, wherein an upper surface of the second portion is lower than an upper surface of the first portion in a direction perpendicular to the substrate;

[0010] a first metal oxide layer, located on the first portion;

[0011] The second metal oxide layer is located on the second portion, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

[0012] In one embodiment, on a side away from the substrate, an upper surface of the second metal oxide layer is lower than an upper surface of the first portion;

[0013] The first metal oxide layer extends from the upper surface of the first portion to the sidewall of the first portion.

[0014] In one embodiment, the thickness of the second metal oxide layer gradually increases from a direction away from the array region to a direction close to the array region.

[0015] In one embodiment, the word line structure further includes:

[0016] The second word line layer is located on the first metal oxide layer.

[0017] In one embodiment, the thickness of the second word line layer gradually increases from a direction close to the peripheral region to a direction away from the peripheral region.

[0018] In one embodiment, the semiconductor structure further comprises:

[0019] A word line trench is located in the substrate and passes through the shallow trench isolation structure and the active area along a first direction, and a plurality of the word line trenches are arranged at intervals along a second direction;

[0020] A gate dielectric layer is located on the sidewalls and bottom of the word line trench; the word line structure is located on the surface of the gate dielectric layer and partially fills the word line trench;

[0021] A filling dielectric layer is provided to fill the remaining space of the word line trench.

[0022] A method for preparing a semiconductor structure comprises the following steps:

[0023] Providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region;

[0024] forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates the substrate into at least one active area;

[0025] forming a plurality of word line trenches in the substrate, the word line trenches extending from the array region to the peripheral region and passing through the shallow trench isolation structure and the active region along a first direction, the plurality of word line trenches extending along the first direction and arranged along a second direction, the second direction intersecting the first direction;

[0026] forming a word line structure in the word line trench;

[0027] Wherein, the word line structure includes a first word line layer, a second metal oxide layer and a first metal oxide layer; the first word line layer includes a first part and a second part, the first part is located on the array area; the second part is located on the peripheral area, wherein the upper surface of the second part is lower than the upper surface of the first part in a direction perpendicular to the substrate; the first metal oxide layer is located on the first part; the second metal oxide layer is located on the second part, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

[0028] In one embodiment, before forming a plurality of word line trenches in the substrate, the method includes:

[0029] forming a mask layer covering the shallow trench isolation structure and the active area on the substrate;

[0030] The forming of a plurality of word line trenches in the substrate comprises:

[0031] Etching the substrate based on the mask layer to form the word line trench;

[0032] Before forming a word line structure in the word line trench, the method includes:

[0033] A gate dielectric layer is formed on the sidewalls and the bottom of the word line trench.

[0034] In one embodiment, forming a word line structure in the word line trench includes:

[0035] forming the first word line layer on the surface of the gate dielectric layer;

[0036] forming a first metal oxide material layer and a second word line material layer in sequence on the first word line layer;

[0037] Sequentially etching and removing the second word line material layer and the first metal oxide material layer located in the peripheral area to form the second word line layer and the first metal oxide layer in the array area;

[0038] The second metal oxide layer is formed on the first word line layer in the peripheral region.

[0039] In one embodiment, after forming the word line structure in the word line trench, the method further includes:

[0040] forming a filling dielectric layer in the remaining space of the word line trench;

[0041] A plurality of bit line structures are formed on the filling dielectric layer, and the plurality of bit line structures extend along the second direction and are arranged along the first direction.

[0042] In the semiconductor structure and the method for manufacturing the same, the thickness of the second metal oxide layer is set to be greater than the thickness of the first metal oxide layer. Therefore, when etching to form the contact hole, the second metal oxide layer can effectively protect the first word line layer and prevent etching damage to the first word line layer, thereby effectively improving the reliability of the word line structure.

[0043] At the same time, the upper surface of the second part of the first word line layer located in the peripheral area is set to be lower than the upper surface of the first part of the first word line layer located in the array area. At this time, on the one hand, a space can be provided for accommodating the second metal oxide layer with a larger thickness, and on the other hand, the distance between the second part of the first word line layer and the bit line structure above the word line structure can be increased, so that the distance between the upper surface of the second metal oxide layer and the bit line structure is increased, thereby preventing the second metal oxide layer and the bit line structure from having a lateral short circuit or leakage.

[0044] Therefore, the present application can effectively improve the performance of storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic top view of a local structure of a semiconductor structure provided in an embodiment;

[0047] Figure 2a The semiconductor structure provided in one embodiment is Figure 1 Schematic diagram of the local structure section after the AA direction section;

[0048] Figure 2b In another embodiment, a semiconductor structure is provided along Figure 1 Schematic diagram of the local structure section after the AA direction section;

[0049] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0050] Figures 4 to 11 FIG. 1 is a schematic cross-sectional view of a local structure during the preparation process of a semiconductor structure provided in an embodiment, wherein Figure 4 , Figure 5 , Figure 6 , Figure 7 as well as Fig.11 In the figure, (a) is along Figure 1 Schematic diagram of the local structure section after the AA' direction section in (a) is along Figure 1 Schematic diagram of the local structure cross section after the BB' direction section.

[0051] Description of reference numerals:

[0052] 100-base; 110-substrate; 111-active area; 120-shallow trench isolation structure; 200-word line structure; 210-first word line layer; 211-first part; 212-second part; 220-first metal oxide layer; 2201-first metal oxide material layer; 230-second word line layer; 2301-second word line material layer; 240-second metal oxide layer; 300-mask layer; 400-gate dielectric layer; 500-filling dielectric layer; 600-bit line structure; 700-first contact plug; 10-word line groove; A1-array area; A2-peripheral area. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intervening element or layer. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there is no intervening element or layer. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type.

[0056] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] In one embodiment, see Figure 1 as well as Figure 2a (or Figure 2b ), a semiconductor structure is provided, which includes a substrate 110 and a word line structure 200.

[0059] The substrate 110 includes an array region A1 and a peripheral region A2 surrounding the array region A1.

[0060] The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator substrates. Therefore, the type of substrate should not limit the scope of protection of the present application.

[0061] The substrate 110 includes at least one active region 111 isolated by a shallow trench isolation structure 120 .

[0062] The shallow trench isolation structure 120 may be located in the substrate and isolate the substrate 110 into a plurality of active regions 111 disposed at intervals.

[0063] The word line structure 200 passes through the shallow trench isolation structure 120 and the active area 111 along a first direction.

[0064] The word line structures 200 extend along a first direction and are arranged along a second direction. The first direction intersects the second direction.

[0065] As an example, the first direction and the second direction may both intersect with the extension direction of the active layer 111. The same word line structure 200 may pass through a plurality of active regions 111 along the first direction. The same active region 111 may be passed through by a plurality of word line structures 200.

[0066] The word line structure 200 includes a first word line layer 210 , a first metal oxide layer 220 and a second metal oxide layer 240 .

[0067] The material of the first word line layer 210 may include a metal material or a conductive material such as metallization, such as metal tungsten.

[0068] The first word line layer 210 extends from the array area A1 to the peripheral area A2, and includes a first portion 211 and a second portion 212. The first portion 211 is located on the array area A1, and the second portion 212 is located on the peripheral area A2.

[0069] Meanwhile, in a direction perpendicular to the substrate, the upper surface of the second portion 212 of the first word line layer 210 is lower than the upper surface of the first portion 211 of the first word line layer 210. That is, the upper surface of the first word line layer 210 in the peripheral area A2 is lower than its upper surface in the array area A1.

[0070] The first metal oxide layer 220 is located on the first portion 211 of the first word line layer 210. The second metal oxide layer 240 is located on the second portion 212 of the first word line layer 210. That is, the first metal oxide layer 220 is located in the array area A1, and the second metal oxide layer 240 is located in the peripheral area A2.

[0071] The material of the first metal oxide layer 220 and the material of the second metal oxide layer 240 can be the same or different, and can be set according to actual needs. As an example, the material of the first metal oxide layer 220 and the material of the second metal oxide layer 240 can be both tungsten oxide.

[0072] The second metal oxide layer 240 and the first metal oxide layer 220 may jointly form a metal diffusion barrier layer, thereby preventing metal diffusion in the first word line layer 310 .

[0073] The second metal oxide layer 240 may be used to form a first contact plug 700. The first contact plug 700 may be used to transmit a signal to the word line structure 200. When forming the first contact plug 700, a contact hole may be first formed by an etching process. Then, a conductive material is filled in the contact hole to form the first contact plug 700.

[0074] In this embodiment, the thickness of the second metal oxide layer 240 is set to be greater than the thickness of the first metal oxide layer 220. Therefore, when etching to form the contact hole, the second metal oxide layer 240 can effectively protect the first word line layer 210 to prevent etching damage to the first word line layer 210, thereby effectively improving the reliability of the word line structure 200.

[0075] At the same time, the upper surface of the second portion 212 of the first word line layer 210 located in the peripheral area A2 is set to be lower than the upper surface of the first portion 211 of the first word line layer 210 located in the array area A1. At this time, on the one hand, a larger accommodation space can be provided for the second metal oxide layer 240, and on the other hand, the distance between the second portion 212 of the first word line layer 210 and the bit line structure 600 above the word line structure 200 can be increased, so that the distance between the upper surface of the second metal oxide layer 240 and the bit line structure 600 is increased, thereby preventing the second metal oxide layer 240, the first contact plug 700 and the bit line structure 600 from lateral short circuit or leakage.

[0076] In one embodiment, see Figure 2a , on the side away from the substrate 110 , the upper surface of the second metal oxide layer 240 is lower than the upper surface of the first portion 211 of the first word line layer 210 .

[0077] At this time, the distance between the upper surface of the second metal oxide layer 240 and the bit line structure 600 is further, so that the lateral short circuit or leakage between the second metal oxide layer 240 , the first contact plug 700 and the bit line structure 600 can be better prevented.

[0078] The first metal oxide layer 220 extends from the upper surface of the first portion 211 of the first word line layer 210 to the sidewall of the first portion 211 .

[0079] It can be understood that the thickness of the first metal oxide layer 220 located on the upper surface of the first part 211 of the first word line layer 210 and the first metal oxide layer (220) located on the side wall of the first part 211 are both smaller than the thickness of the second metal oxide layer (240).

[0080] By extending the first metal oxide layer 220 to the side wall of the first portion 211 of the first word line layer 210 , when the upper surface of the second metal oxide layer 240 is too low to cover the top of the side wall of the first portion 211 , the side wall of the first word line layer 210 can be well covered by the first metal oxide layer 220 .

[0081] At this time, the second metal oxide layer 220 can be connected to the first metal oxide layer 220 located on the side wall of the first part 211, so that the second metal oxide layer 240 and the first metal oxide layer 220 can completely cover the various surfaces of the first word line layer 210, thereby effectively preventing the metal in the first word line layer 210 from diffusing.

[0082] Of course, in other embodiments, the upper surface of the second metal oxide layer 240 may also be higher than the upper surface of the first portion 211 of the first word line layer 210 .

[0083] For example, the upper surface of a portion of the second metal oxide layer 240 close to the array area A1 may be higher than the upper surface of the first portion 211 of the first word line layer 210, while the upper surface of another portion of the second metal oxide layer 240 away from the array area A1 may be lower than the upper surface of the first portion 211 of the first word line layer 210. Of course, the upper surface of the second metal oxide layer 240 may also be higher than the upper surface of the first portion 211 of the first word line layer 210 as a whole, and this is not limited here.

[0084] At this time, the sidewall of the first portion 211 may be covered by the second metal oxide layer 240. At the same time, the first metal oxide layer 220 may be located only on the upper surface of the first portion 211 of the first word line layer 210. The first metal oxide layer 220 is connected to the second metal oxide layer 240, so that the metal diffusion in the first word line layer 210 can also be effectively prevented.

[0085] In one embodiment, see Figure 2b The thickness of the second metal oxide layer (240) gradually increases from a direction away from the array region (A1) to a direction close to the array region (A1).

[0086] At this time, on the one hand, the second metal oxide layer 240 close to the side wall of the first portion 211 of the first word line layer 210 has a larger thickness, thereby ensuring effective coverage of the first word line layer 210. On the other hand, the second metal oxide layer 240 away from the side wall of the first portion 211 of the first word line layer 210 has a relatively smaller thickness, thereby preventing the overall height of the upper surface of the second metal oxide layer 240 from being too high, thereby increasing the risk of short circuit with the bit line structure 700. At the same time, the gradual thickness of the second metal oxide layer 240 is also convenient for process processing.

[0087] In one embodiment, see Figure 2a or Figure 2b The word line structure 200 further includes a second word line layer 230. The material of the second word line layer 230 may include but is not limited to polysilicon.

[0088] The second word line layer 230 is located on the first metal oxide layer 220 in the array area A1 , and thus can be used as a component of the gate of the transistor located in the array area A1 .

[0089] The work function of the second word line layer 230 may be different from the work function of the first word line layer 210 , so that a threshold voltage of a transistor, etc. may be adjusted.

[0090] The first metal oxide layer 220 is located between the second word line layer 230 and the first word line layer 210 , thereby effectively preventing mutual diffusion between the two.

[0091] In one embodiment, the thickness of the second word line layer 230 gradually increases in a direction from close to the peripheral area A2 to far away from the peripheral area A2.

[0092] The first metal oxide layer 220 and the second metal oxide layer 240 are bonded to each other at or near the boundary between the peripheral area A2 and the array area A1. Therefore, at the boundary between the peripheral area A2 and the array area A1, the ability to prevent the metal in the first word line layer 210 from diffusing is relatively weak.

[0093] Therefore, the thickness of the second word line layer 230 is relatively thin near the peripheral area A2, which can reduce the diffusion risk between the second word line layer 230 and the first word line layer 210. At the same time, the gradual thickness of the second word line layer 230 is also convenient for processing.

[0094] In one embodiment, see Fig.11 The semiconductor structure further includes a word line trench 10 , a gate dielectric layer 400 and a filling dielectric layer 500 .

[0095] The word line trench 10 is located in the substrate 110 and passes through the shallow trench isolation structure 120 and the active area 111 along the first direction, thereby extending along the first direction.

[0096] The plurality of word line trenches 10 are arranged at intervals along the second direction. As an example, the plurality of word line trenches 10 may be arranged in parallel and at equal intervals.

[0097] The gate dielectric layer 400 is located on the sidewalls and the bottom of the word line trench 10 .

[0098] The material of the gate dielectric layer 400 may include a high-k dielectric layer. For example, the material of the gate dielectric layer includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0099] Of course, the material of the gate dielectric layer 400 may also include a low-k dielectric layer. For example, the material of the gate dielectric layer includes a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3) or a silicon oxynitride layer (SiON).

[0100] The word line structure 200 is located on the surface of the gate dielectric layer 400 .

[0101] The material filling the dielectric layer 500 may include, but is not limited to, a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (Al 2 O 3 ) or a silicon oxynitride layer (SiON).

[0102] The filling dielectric layer 500 fills the remaining space of the word line trench 10 , thereby insulating and isolating the word line structure 200 .

[0103] In one embodiment, see Figure 3 , a method for preparing a semiconductor structure is provided, comprising the following steps:

[0104] Step S10, see Figure 4 , a substrate 110 is provided, wherein the substrate 110 includes an array area A1 and a peripheral area A2 surrounding the array area A1.

[0105] The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator substrates. Therefore, the type of substrate should not limit the scope of protection of the present application.

[0106] Step S20, see Figure 4 , a shallow trench isolation structure 120 is formed in the substrate 110 , and the shallow trench isolation structure 120 isolates the substrate 110 into at least one active area 111 .

[0107] A shallow trench may be first formed in the substrate 110 , and then a filling insulating material is formed in the shallow trench, thereby forming a shallow trench isolation structure 120 .

[0108] The shallow trench isolation structure 120 can isolate the substrate 110 into a plurality of active regions 111 disposed at intervals.

[0109] Step S40, see Figure 4 A plurality of word line trenches 10 are formed in the substrate 110. The word line trenches 10 extend from the array area A1 to the peripheral area A2 and pass through the shallow trench isolation structure 120 and the active area 111 along a first direction. The plurality of word line trenches 10 extend along the first direction and are arranged along a second direction.

[0110] The shallow trench isolation structure 120 and the active area 111 may be etched simultaneously, so as to form a plurality of word line trenches 10 in the substrate 110 after the shallow trench isolation structure 120 is formed.

[0111] The extension direction of the active region 111 may intersect both the first direction and the second direction. The same word line trench 10 may pass through multiple active regions 111 along the first direction. The same active region 111 may be passed through by multiple word line trenches 10.

[0112] It should be noted that, in this article, "plurality" can mean two or more than two.

[0113] It can be understood that along the first direction, the active region 111 may be arranged unevenly, and the active region and the shallow trench isolation structure 120 are made of different materials, so the depths of the word line trench 10 at different positions in the first direction may be different (see Figure 4 (a) in the figure).

[0114] Step S60, see Fig.11 , a word line structure 200 is formed in the word line trench 10. The word line structure 200 includes a first word line layer 210, a second metal oxide layer 240 and a first metal oxide layer 220; the first word line layer 210 includes a first portion 211 and a second portion 212, the first portion 211 is located on the array area A1; the second portion 212 is located on the peripheral area A2, wherein the upper surface of the second portion 212 is lower than the upper surface of the first portion 211 in a direction perpendicular to the substrate; the first metal oxide layer 220 is located on the first portion 211; the second metal oxide layer 240 is located on the second portion 212, and the thickness of the second metal oxide layer 240 is greater than the thickness of the first metal oxide layer 220.

[0115] The material of the first word line layer 210 may include a metal material (eg, metal tungsten) or a conductive material such as metallization.

[0116] The second metal oxide layer 240 and the first metal oxide layer 220 may jointly form a metal diffusion barrier layer, thereby preventing metal diffusion in the first word line layer 310 .

[0117] The materials of the second metal oxide layer 240 and the first metal oxide layer 220 may include but are not limited to tungsten oxide.

[0118] See also Figure 2a After step S60, the following steps may also be included:

[0119] A first contact plug 700 extending to the second metal oxide layer 240 is formed.

[0120] Specifically, a contact hole may be formed by an etching process first, and then a conductive material is filled in the contact hole to form the first contact plug 700 .

[0121] In this embodiment, after the word line trench 10 is formed, when the word line structure 200 is formed, the thickness of the second metal oxide layer 240 located in the peripheral area A2 is greater than the thickness of the first metal oxide layer 220 located in the array area A1. Therefore, when etching to form the contact hole, the second metal oxide layer 240 can effectively protect the first word line layer 210 to prevent etching damage to the first word line layer 210, thereby effectively improving the reliability of the word line structure 200.

[0122] At the same time, when forming the word line structure 200, the upper surface of the second portion 212 of the first word line layer 210 located in the peripheral area A2 is also made lower than the upper surface of the first portion 211 of the first word line layer 210 located in the array area A1. At this time, on the one hand, a space can be provided for the second metal oxide layer 240 with a larger thickness, and on the other hand, the distance between the second portion 212 of the first word line layer 210 in the peripheral area A2 and the subsequently formed bit line structure 600 can be increased, so that the distance between the surface of the second metal oxide layer 240 and the bit line structure 600 is increased, thereby preventing the second metal oxide layer 240 and the bit line structure 600 from having a lateral short circuit or leakage.

[0123] In one embodiment, see Figure 4 Before forming a plurality of word line trenches 10 in the substrate 110, step S40 includes:

[0124] In step S30 , a mask layer 300 is formed on the substrate 110 to cover the shallow trench isolation structure 120 and the active area 111 .

[0125] A mask material layer may be formed first, and then the mask material layer is patterned by a photolithography process, thereby forming the mask layer 300 .

[0126] Meanwhile, step S40 includes:

[0127] In step S41 , the substrate 110 is etched based on the mask layer 300 to form a word line trench 10 .

[0128] Furthermore, before forming the word line structure 200 in the word line trench 10, step S60 includes:

[0129] In step S50 , a gate dielectric layer 400 is formed on the sidewalls and the bottom of the word line trench 10 .

[0130] As an example, see Figure 5 , a gate dielectric layer 400 may be formed on the upper surface of the mask layer 300 , the sidewalls of the word line trench 10 , and the bottom of the word line trench 10 .

[0131] In one embodiment, step S60 of forming a word line structure 200 in the word line trench 10 includes:

[0132] Step S61, see Figure 6 , a first word line layer 210 is formed on the surface of the gate dielectric layer 400 .

[0133] As an example, a first word line initialization layer with a flat upper surface may be first formed on the surface of the gate dielectric layer 400. Then, the first word line initialization layer in the peripheral area A2 may be etched and thinned to form a first word line layer 210 with a second portion 212 having an upper surface lower than that of the first portion 211.

[0134] Meanwhile, the inclination angle of the sidewall of the first portion 211 may be adjusted by adjusting the etching process conditions.

[0135] As an example, after forming the first word line layer 210 , the gate dielectric layer 400 located on the upper surface of the mask layer 300 may be removed.

[0136] Step S62, see Figure 7 as well as Figure 8 , a first metal oxide material layer 2201 and a second word line material layer 2301 are sequentially formed on the first word line layer 210 .

[0137] The first metal oxide material layer 2201 may be first deposited on the surface of the first word line layer 210 , and then the second word line material layer 2301 may be deposited on the surface of the first metal oxide material layer 2201 .

[0138] Step S63, see Fig. 9 , the second word line material layer 2301 and the first metal oxide material layer 2201 located in the peripheral area A2 are sequentially etched away to form a second word line layer 230 and a first metal oxide layer 220 in the array area A1.

[0139] As an example, a second mask layer (not shown) can be formed on the second word line material layer 2301 in the array area A1, and the second word line material layer 2301 is etched using the first metal oxide material layer 2201 as an etching stop layer to form the second word line layer 230 and the first metal oxide layer 220.

[0140] Step S64, see Fig.10 , a second metal oxide layer 240 is formed on the first word line layer 210 in the peripheral area A2.

[0141] A second metal oxide material layer may be formed first, and then the second metal oxide material layer may be etched to form a second metal oxide layer 240. The second metal oxide layer 240 may be connected to the first metal oxide layer 220, so that the two may jointly prevent metal diffusion in the first word line layer 210.

[0142] As an example, after etching the first metal oxide material layer 2201 in step S63, the first metal oxide material layer 2201 located on the sidewall of the first portion 211 of the first word line layer 210 can be retained. That is, the first metal oxide layer 220 formed after etching can extend from the upper surface of the first portion 211 to the sidewall of the first portion 211.

[0143] At this time, the upper surface of the second metal oxide layer 240 formed in step S64 may be lower than the upper surface of the first portion 211 .

[0144] As another example, after etching the first metal oxide material layer 2201 , the first metal oxide material layer 2201 located on the sidewall of the first portion 211 of the first word line layer 210 may also be etched away, so that the first metal oxide layer 220 is only located on the upper surface of the first portion 211 .

[0145] At this time, the upper surface of the second metal oxide layer 240 formed in step S64 may be higher than the upper surface of the first portion 211 , so that the second metal oxide layer 240 may cover the sidewall of the first portion 211 of the first word line layer 210 and connect to the first metal oxide layer 220 .

[0146] In one embodiment, after forming the word line structure 200 in the word line trench 10, step S60 further includes:

[0147] Step S70, see Fig.11 , a filling dielectric layer 500 is formed in the remaining space of the word line trench 10 .

[0148] The filling dielectric layer 500 may fill the remaining space of the word line trench 10 .

[0149] In step S80 , referring to FIG. 2 , a plurality of bit line structures 600 are formed on the filling dielectric layer 500 . The plurality of bit line structures 600 extend along the second direction and are arranged along the first direction.

[0150] The bit line structure 600 can be connected to the active region located at one side of the word line structure 200 through a second contact plug (not shown), thereby being connected to the source region or the drain region of the transistor, thereby providing a bit line signal for the memory cell.

[0151] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0152] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0153] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising an array region and a peripheral region surrounding the array region, wherein the substrate comprises at least one active region isolated by a shallow trench isolation structure; A word line structure passes through the shallow trench isolation structure and the active area along a first direction, and a plurality of the word line structures extend along the first direction and are arranged along a second direction, and the second direction intersects the first direction; Furthermore, the word line structure includes: A first word line layer, comprising a first portion and a second portion, wherein the first portion is located on the array region; the second portion is located on the peripheral region, wherein an upper surface of the second portion is lower than an upper surface of the first portion in a direction perpendicular to the substrate; a first metal oxide layer, located on the first portion; The second metal oxide layer is located on the second portion, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

2. The semiconductor structure according to claim 1, characterized in that: On a side away from the substrate, an upper surface of the second metal oxide layer is lower than an upper surface of the first portion; The first metal oxide layer extends from the upper surface of the first portion to the sidewall of the first portion.

3. The semiconductor structure according to claim 1, characterized in that: The thickness of the second metal oxide layer gradually increases from a direction away from the array region to a direction close to the array region.

4. The semiconductor structure according to claim 1, characterized in that The word line structure further includes: The second word line layer is located on the first metal oxide layer.

5. The semiconductor structure according to claim 4, characterized in that: The thickness of the second word line layer gradually increases in a direction from close to the peripheral region to far away from the peripheral region.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: A word line trench is located in the substrate and passes through the shallow trench isolation structure and the active area along a first direction, and a plurality of the word line trenches are arranged at intervals along a second direction; A gate dielectric layer is located on the sidewalls and bottom of the word line trench; the word line structure is located on the surface of the gate dielectric layer and partially fills the word line trench; A filling dielectric layer is provided to fill the remaining space of the word line trench.

7. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region; forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates the substrate into at least one active area; forming a plurality of word line trenches in the substrate, the word line trenches extending from the array region to the peripheral region and passing through the shallow trench isolation structure and the active region along a first direction, the plurality of word line trenches extending along the first direction and arranged along a second direction, the second direction intersecting the first direction; forming a word line structure in the word line trench; Wherein, the word line structure comprises a first word line layer, a second metal oxide layer and a first metal oxide layer; The first word line layer includes a first part and a second part, the first part is located on the array area; the second part is located on the peripheral area, wherein the upper surface of the second part is lower than the upper surface of the first part in a direction perpendicular to the substrate; the first metal oxide layer is located on the first part; the second metal oxide layer is located on the second part, and the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Before forming a plurality of word line trenches in the substrate, the method includes: forming a mask layer covering the shallow trench isolation structure and the active area on the substrate; The forming of a plurality of word line trenches in the substrate comprises: Etching the substrate based on the mask layer to form the word line trench; Before forming a word line structure in the word line trench, the method includes: A gate dielectric layer is formed on the sidewalls and the bottom of the word line trench.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The forming of a word line structure in the word line trench comprises: forming the first word line layer on the surface of the gate dielectric layer; forming a first metal oxide material layer and a second word line material layer in sequence on the first word line layer; Sequentially etching and removing the second word line material layer and the first metal oxide material layer located in the peripheral area to form the second word line layer and the first metal oxide layer in the array area; The second metal oxide layer is formed on the first word line layer in the peripheral region.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: After forming the word line structure in the word line trench, the method further includes: forming a filling dielectric layer in the remaining space of the word line trench; A plurality of bit line structures are formed on the filling dielectric layer, and the plurality of bit line structures extend along the second direction and are arranged along the first direction.

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