Automatic test vector generation device and method
Through the coordinated work of automatic testing equipment, controller and device under test, the signals are automatically collected and analyzed, and the test vectors are generated, which solves the problems of low efficiency and high error rate of test vector generation in integrated circuit tests, and achieves efficient and accurate test vector generation.
Patent Information
- Application Number
- CN202411671907.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-02-28
AI Technical Summary
In integrated circuit testing, the test vector generation efficiency is low and the error rate is high. Especially for chips with interface protocols and internal registers, writing test vectors requires in-depth research on the chip's interface protocol and timing signals.
An automatic test vector generation device and method is provided. Through the coordinated work of the automatic test device, controller and device under test, the pin signals and bidirectional pin indicator signals of the device under test are collected, and the test vector is automatically generated. The controller generates a bidirectional pin indication signal based on the interactive state with the device under test to help the automatic test device automatically generate the test vector.
This greatly simplifies the manual programming work of program developers when writing test vectors, reduces the need for in-depth research on the internal structure of the device under test, improves the generation efficiency of test vectors, reduces the error rate, and improves the accuracy and reliability of tests.
Smart Images
Figure CN119535184A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of equipment testing, and more specifically, to an automatic test vector generation device and method. Background Art
[0002] At present, the testing of integrated circuits mainly relies on automatic test equipment (ATE), which applies stimulus vectors to the device under test (DUT) and receives responses. However, there are many types of integrated circuits with various functions. When writing test vectors, it is often necessary to conduct in-depth research on the device under test. Especially for chips with interface protocols and internal registers, program developers need to compile data communication between ATE and DUT according to the protocol, deeply study the meaning of each bit of the DUT control signal, and accurately determine when the IO pin of the DUT is converted from input to output, when the ATE sends data signals and handshake signals, and when it receives response signals. In-depth research on the signals and timing of the integrated circuit interface protocol by program developers often takes a lot of time, and the generation efficiency of test vectors is low and the error rate is high. Summary of the invention
[0003] In view of the defects of the prior art, the purpose of the present application is to provide an automatic test vector generation device and method, aiming to solve the problems of low test vector generation efficiency and high error rate.
[0004] The present application provides an automatic test vector generation device, comprising: an automatic test device, and a controller and a device under test connected to the automatic test device; the automatic test device provides working power to the controller and the device under test, and sends a trigger signal to the controller to start the test;
[0005] The controller is used to provide a DUT bidirectional pin indication signal to the automatic test equipment through the interaction status with the device under test;
[0006] The automatic test equipment is used to collect DUT pin signals of the device under test, and automatically generate test vectors for stimulating the DUT according to the DUT pin signals and the DUT bidirectional pin indication signals.
[0007] Optionally, the controller is specifically used to:
[0008] In the case of sending a stimulus test signal to a pin of a device under test (DUT), setting the DUT bidirectional pin indication signal to 1;
[0009] In the case of receiving a response signal fed back from the device under test (DUT), setting the DUT bidirectional pin indication signal to 0;
[0010] The response signal is a handshake signal or an advanced stimulus test signal generated based on the test requirements after the controller receives the response.
[0011] Optionally, the automatic test equipment includes at least a first digital channel, a second digital channel, a third digital channel and a fourth digital channel; the controller includes at least a first pin, a second pin, a third pin and a fourth pin; the device under test includes at least a functional pin SDA and a functional pin SCL; and the first digital channel is connected to any pin of the controller.
[0012] Optionally, the first pin is connected to the first digital channel, and the third pin and the fourth pin are connected to the function pin SDA and the function pin SCL respectively;
[0013] The second pin is connected to the second digital channel and is used to indicate the signal direction of the function pin SDA of the device under test; the function pin SDA is connected to the third digital channel, and the function pin SCL is connected to the fourth digital channel;
[0014] When the first digital channel sends a trigger signal, the controller executes the driver program of the device under test and automatically completes the interaction with the device under test.
[0015] Optionally, the first pin receives the trigger signal, and sends a test stimulus signal to the device under test through a third pin and a fourth pin;
[0016] When the third pin is in a state of sending a signal to the device under test, the controller sets the second pin to 1;
[0017] When the third pin is in a state of receiving a signal from the device under test, the controller sets the second pin to 0.
[0018] Optionally, the controller is a microcontroller unit MCU or a field programmable gate array FPGA.
[0019] In a second aspect, the present application further provides an automatic test vector generation method, characterized in that it is applied to a test system, the test system comprising an automatic test device, a controller and a device under test, and the method comprises:
[0020] The automatic test equipment sends a trigger signal to the controller, collects data on the pins of the device under test, and obtains the DUT pin signal;
[0021] Receive a trigger signal through the controller and send a test stimulus signal to the device under test;
[0022] Receiving the test stimulus signal through the device under test and responding;
[0023] Determine a DUT bidirectional pin indication signal according to a current operating state through a controller, and provide the DUT bidirectional pin indication signal to the automatic test equipment;
[0024] The test vector is automatically generated according to the DUT pin signal and the DUT bidirectional pin indication signal by automatic test equipment.
[0025] Optionally, determining the DUT bidirectional pin indication signal according to the current operation state by the controller includes:
[0026] When the controller is in the state of sending an excitation test signal to a pin of a device under test (DUT), setting the DUT bidirectional pin indication signal to 1;
[0027] When the controller is receiving a response signal fed back from the device under test (DUT), setting the DUT bidirectional pin indication signal to 0;
[0028] The response signal is a handshake signal or an advanced stimulus test signal generated based on the test requirements after the controller receives the response.
[0029] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.
[0030] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.
[0031] In a fifth aspect, the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.
[0032] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.
[0033] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:
[0034] (1) The present application can automatically generate test vectors based on the pin signals and bidirectional pin indication signals of the device under test collected by the automatic test equipment. This process greatly simplifies the manual programming work required by program developers when writing test vectors, and reduces the need for in-depth research on the internal structure of the DUT. Through the automatic interaction between the controller and the DUT, the operation process of program developers is reduced. The controller can automatically send appropriate test stimulus signals, and based on the response of the DUT, generate subsequent test stimuli and signal indications. By automatically producing signals and responses instead of manual operations by developers, it not only improves the efficiency of test vector generation, but also reduces the error rate and improves accuracy.
[0035] (2) The bidirectional pin indication signal mechanism in this application allows the controller to dynamically determine the input and output status of its IO pins based on the current status of the DUT, reducing the need for program developers to manually determine the signal status and improving the accuracy and timeliness of the test.
[0036] (3) This application reduces the errors that may occur during the programming process by program developers through automated test vector generation, ensuring that the generated test vectors can more accurately correspond to the characteristics of the DUT, thereby improving the reliability and efficiency of the test. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 It is one of the structural schematic diagrams of the automatic test vector generation device provided in the embodiment of the present application;
[0038] Figure 2 This is the second structural diagram of the automatic test vector generation device provided in the embodiment of the present application;
[0039] Figure 3 It is a flowchart of the automatic test vector generation method provided in an embodiment of the present application;
[0040] Figure 4 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0042] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.
[0043] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.
[0044] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
[0045] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.
[0046] Next, the technical solutions provided in the embodiments of the present application are introduced.
[0047] Reference Figure 1 , the present application provides an automatic test vector generation device, comprising: an automatic test device, and a controller and a device under test connected to the automatic test device; the automatic test device provides working power to the controller and the device under test, and sends a trigger signal to the controller to start the test;
[0048] The controller is used to provide a DUT bidirectional pin indication signal to the automatic test equipment through the interaction status with the device under test;
[0049] The automatic test equipment is used to collect DUT pin signals of the device under test, and automatically generate test vectors for stimulating the DUT according to the DUT pin signals and the DUT bidirectional pin indication signals.
[0050] Specifically, the automatic test vector generation device based on the automatic test equipment ATE of this embodiment includes a controller and a device under test DUT both connected to the automatic test equipment, the automatic test equipment provides working power to the controller and the device under test, and the automatic test equipment sends a trigger signal to the controller to start the test. The controller automatically completes the interaction with the device under test and provides the automatic test equipment with a DUT bidirectional pin indication signal, and the automatic test equipment automatically generates a test vector according to the collected DUT pin signal and the bidirectional pin indication signal.
[0051] In this embodiment, the automatic test equipment (e.g., J750Ex) is the core of the entire test system, providing the required working power and communicating with the controller and the device under test (DUT). The equipment is responsible for supplying the appropriate power supply voltage (e.g., 3.3V) to the controller and DUT to ensure that they can work properly. At the beginning of the test, the automatic test equipment sends a trigger signal to the controller to notify the controller to start the test process.
[0052] A controller (such as an STM32F103C8T6 microcontroller or FPGA) is connected between the automatic test equipment and the DUT and is responsible for coordinating the interaction between the two.
[0053] Bidirectional pin indication signal: The controller generates a bidirectional pin indication signal (status indication of this pin) based on the interaction with the DUT and sends it to the automatic test equipment. This signal is used to indicate whether the current controller is sending or receiving data, thereby helping the automatic test equipment to determine the next operation to be performed.
[0054] Processing signals: The controller decides when and how to send test stimulus signals to the automatic test equipment based on the DUT's response and bidirectional pin indication signals.
[0055] The device under test is the hardware component that needs to be tested, such as a sensor, microcontroller, or other electronic component. During the test, the function and response of the DUT will be verified. During the test, the DUT will respond to the test stimulus signal received and output signals through the DUT pins. The controller will collect these output signals to evaluate the performance of the DUT.
[0056] The following is the process of vector generation in the embodiment of the present application:
[0057] When the automatic test equipment sends a trigger signal, the controller starts executing the test program.
[0058] The controller communicates with the DUT through IO pins, sending test stimulus signals and simultaneously collecting the output signals of the DUT. These output signals are called DUT pin signals.
[0059] When the controller handles the interaction with the DUT, it generates bidirectional pin indication signals based on the current state (for example, indicating whether data should be sent or received by the DUT). This signal provides instructions to the automatic test equipment to help it determine the next step.
[0060] The automatic test equipment analyzes the collected DUT pin signals and bidirectional pin indication signals to automatically generate a series of test vectors. The generated test vectors can be used to further stimulate the DUT for functional testing.
[0061] The present application can automatically generate test vectors based on the pin signals and bidirectional pin indication signals of the device under test collected by the automatic test equipment. This process greatly simplifies the manual programming work required by program developers when writing test vectors, and reduces the need for in-depth research on the internal structure of the DUT. Through the automatic interaction between the controller and the DUT, the operation process of program developers is reduced. The controller can automatically send appropriate test stimulus signals, and based on the response of the DUT, generate subsequent test stimuli and signal indications. By automatically producing signals and responses instead of manual operations by developers, it not only improves the efficiency of test vector generation, but also reduces the error rate and improves accuracy.
[0062] Optionally, the controller is specifically used to:
[0063] In the case of sending a stimulus test signal to a pin of a device under test (DUT), setting the DUT bidirectional pin indication signal to 1;
[0064] In the case of receiving a response signal fed back from the device under test (DUT), setting the DUT bidirectional pin indication signal to 0;
[0065] The response signal is a handshake signal or an advanced stimulus test signal generated based on the test requirements after the controller receives the response.
[0066] Optionally, the automatic test equipment includes at least a first digital channel, a second digital channel, a third digital channel and a fourth digital channel; the controller includes at least a first pin, a second pin, a third pin and a fourth pin; the device under test includes at least a functional pin SDA and a functional pin SCL; and the first digital channel is connected to any pin of the controller.
[0067] Optionally, the first pin is connected to the first digital channel, and the third pin and the fourth pin are connected to the function pin SDA and the function pin SCL respectively;
[0068] The second pin is connected to the second digital channel and is used to indicate the signal direction of the function pin SDA of the device under test; the function pin SDA is connected to the third digital channel, and the function pin SCL is connected to the fourth digital channel;
[0069] When the first digital channel sends a trigger signal, the controller executes the driver program of the device under test and automatically completes the interaction with the device under test.
[0070] Optionally, the first pin receives the trigger signal, and sends a test stimulus signal to the device under test through a third pin and a fourth pin;
[0071] When the third pin is in a state of sending a signal to the device under test, the controller sets the second pin to 1;
[0072] When the third pin is in a state of receiving a signal from the device under test, the controller sets the second pin to 0.
[0073] Optionally, the controller is a microcontroller unit MCU or a field programmable gate array FPGA.
[0074] Specifically, refer to Figure 2 In this embodiment, the DUT is a TMP100 chip of a certain company, the controller is a microcontroller chip STM32F103C8T6, and the automatic test equipment is J750Ex, and automatic test vector generation is performed.
[0075] It should be noted that the first digital channel, the second digital channel, the third digital channel and the fourth digital channel of the automatic test equipment in this embodiment correspond to CH00, CH01, CH02 and CH03 below respectively; the first pin, the second pin, the third pin and the fourth pin of the controller correspond to PC10, PC11, PC12 and PC13 below respectively.
[0076] The power channels DPS1 and DPS0 of J750Ex provide 3.3V operating power for STM32F103C8T6 and TMP100 respectively.
[0077] The digital channel CH00 of J750Ex is connected to a general IO pin (such as PC10) of STM32F103C8T6. The general IO pins PC12 and PC13 of STM32F103C8T6 are connected to the functional pins SDA and SCL of TMP100 respectively. The pin PC11 of STM32F103C8T6 is used to indicate the signal direction of the bidirectional pin SDA of TMP100 chip and is connected to the digital channel CH01 of the test equipment J750Ex.
[0078] The functional pins SDA and SCL of TMP100 are connected to the digital channels CH02 and CH03 of the test equipment J750Ex respectively.
[0079] After CH00 of J750Ex sends a valid signal, STM32F103C8T6 executes the driver of TMP100 and automatically completes the interaction with TMP100. At the same time, the automatic test equipment J750Ex automatically generates test vectors based on the collected CH01, CH02 and CH03 signals.
[0080] The present application also provides an automatic test vector generation method, characterized in that it is applied to a test system, the test system includes an automatic test device, a controller and a device under test, and the method includes:
[0081] The automatic test equipment sends a trigger signal to the controller, collects data on the pins of the device under test, and obtains the DUT pin signal;
[0082] Receive a trigger signal through the controller and send a test stimulus signal to the device under test;
[0083] Receiving the test stimulus signal through the device under test and responding;
[0084] Determine a DUT bidirectional pin indication signal according to a current operating state through a controller, and provide the DUT bidirectional pin indication signal to the automatic test equipment;
[0085] The test vector is automatically generated according to the DUT pin signal and the DUT bidirectional pin indication signal by automatic test equipment.
[0086] Specifically, the steps for generating the test vector are as follows:
[0087] S1. The automatic test equipment controls the controller and the device under test at the same time, provides working power to the controller and the device under test, and puts the controller and the device under test in working state;
[0088] S2, the automatic test equipment sends a trigger signal to the controller and starts data collection on the pins of the device under test;
[0089] S3. After receiving the trigger signal from the automatic test equipment, the controller sends a test stimulus signal to the device under test; if the controller is in a state of sending a signal to the input / output (IO) bidirectional pin of the DUT, the controller sets the bidirectional pin indication signal to 1.
[0090] S4, after receiving the test stimulus from the controller, the device under test responds;
[0091] S5. After receiving the response from the device under test, the controller sends a handshake signal or a further test stimulus signal as needed; if the controller is in a state of receiving the IO pin signal of the DUT, the controller sets the bidirectional pin indication signal to 0.
[0092] S6. The automatic test equipment automatically generates a test vector according to the collected DUT pin signal and the bidirectional pin indication signal.
[0093] Further, description is given in combination with the models of the automatic testing equipment and the controller in the above embodiments.
[0094] S10 and J750Ex provide 3.3V working power supply for STM32F103C8T6 and TMP100, so that STM32F103C8T6 and TMP100 are in working state;
[0095] S20, J750Ex digital channel CH00 sends a trigger signal to STM32F103C8T6, and at the same time starts the data acquisition function to collect signals from CH01, CH02 and CH03;
[0096] After receiving the trigger signal, PC10 of S30 and STM32F103C8T6 sends the test stimulus signal to TMP100 through PC12 and PC13; if PC12 is in the state of sending a signal to the bidirectional pin SDA of TMP100, STM32F103C8T6 sets the bidirectional pin indication signal PC11 to 1.
[0097] S40, after receiving the test stimulus from the controller, the device under test responds;
[0098] After S50 and STM32F103C8T6 receive the response from TMP100, they send out handshake signals or further test stimulus signals as needed; if PC12 is in the state of receiving the IO pin signal of DUT, STM32F103C8T6 sets the bidirectional pin indication signal PC11 to 0.
[0099] S6, J750Ex automatically generates test vectors based on the collected DUT pin signals CH02 and CH03 and the bidirectional pin indication signal CH01.
[0100] Optionally, determining the DUT bidirectional pin indication signal according to the current operation state by the controller includes:
[0101] When the controller is in the state of sending an excitation test signal to a pin of a device under test (DUT), setting the DUT bidirectional pin indication signal to 1;
[0102] When the controller is receiving a response signal fed back from the device under test (DUT), setting the DUT bidirectional pin indication signal to 0;
[0103] The response signal is a handshake signal or an advanced stimulus test signal generated based on the test requirements after the controller receives the response.
[0104] Specifically, in this embodiment, when the controller is ready to send an excitation test signal to the pin of the DUT, the controller sets the DUT bidirectional pin indication signal to 1. The state of this indication signal represents the current operation mode of the controller, that is, sending a signal. The controller sends the preset excitation test signal to the DUT through its output pin. These signals may be specific data patterns, clock pulses, or other digital signals, designed to stimulate the DUT to respond.
[0105] When the controller has finished sending the stimulus signal and is ready to receive the response signal fed back by the DUT, the DUT bidirectional pin indication signal is set to 0. The change of this indication signal informs the automatic test equipment and any other monitoring system that the current state is receiving. In this state, the controller receives the feedback signal from the DUT through the corresponding input pin. This signal can be the state feedback, data output or other response signal of the DUT.
[0106] Furthermore, in some communication protocols, handshake signals are used to confirm the reception and confirmation of signals. After the controller receives the handshake signal from the DUT, it indicates that the data has been successfully received and the next data exchange can continue. This signal is usually a short pulse that identifies the current state.
[0107] Depending on the test requirements, the controller can generate further stimulus test signals, which are usually determined based on the previous behavior or state of the DUT. For example, the controller may optimize the test signals sent based on the feedback signals of the DUT to ensure that further tests cover all possible working states and boundary conditions of the DUT. The generation of these advanced stimulus signals ensures that the functionality and reliability of the DUT can be fully evaluated.
[0108] The embodiment of the present application helps ensure the coordination between the controller and the DUT through clear status indication, reduces the possibility of signal conflict and misoperation, and thus improves the test efficiency. And according to different test requirements, the sending and receiving modes can be quickly switched to adapt to different types of test scenarios.
[0109] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method, which will not be repeated here.
[0110] Reference Figure 4Based on the method in the above embodiment, the embodiment of the present application provides an electronic device, which may include: a processor (processor) 410, a communication interface (CommunicationsInterface) 420, a memory (memory) 430 and a communication bus 440, wherein the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 can call the logic instructions in the memory 430 to execute the method in the above embodiment.
[0111] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.
[0112] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.
[0113] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.
[0114] It is understandable that the processor in the embodiment of the present application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.
[0115] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.
[0116] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.
[0117] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.
[0118] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.
Claims
1. An automatic test vector generation device, characterized in that: include: An automatic test device and a controller and a device under test connected to the automatic test device; the automatic test device provides working power to the controller and the device under test, and sends a trigger signal to the controller to start the test; The controller is used to provide a DUT bidirectional pin indication signal to the automatic test equipment through the interaction status with the device under test; The automatic test equipment is used to collect DUT pin signals of the device under test, and automatically generate test vectors for stimulating the DUT according to the DUT pin signals and the DUT bidirectional pin indication signals.
2. The automatic test vector generation device according to claim 1, characterized in that: The controller is specifically used for: In the case of sending a stimulus test signal to a pin of a device under test (DUT), setting the DUT bidirectional pin indication signal to 1; In the case of receiving a response signal fed back from the device under test (DUT), setting the DUT bidirectional pin indication signal to 0; The response signal is a handshake signal or an advanced stimulus test signal generated based on the test requirements after the controller receives the response.
3. The automatic test vector generation device according to claim 1, characterized in that: The automatic test equipment at least includes a first digital channel, a second digital channel, a third digital channel and a fourth digital channel; the controller at least includes a first pin, a second pin, a third pin and a fourth pin; The device under test includes at least a function pin SDA and a function pin SCL; the first digital channel is connected to any pin of the controller.
4. The automatic test vector generation device according to claim 3, characterized in that: The first pin is connected to the first digital channel, and the third pin and the fourth pin are connected to the function pin SDA and the function pin SCL respectively; The second pin is connected to the second digital channel and is used to indicate the signal direction of the function pin SDA of the device under test; the function pin SDA is connected to the third digital channel, and the function pin SCL is connected to the fourth digital channel; When the first digital channel sends a trigger signal, the controller executes the driver program of the device under test and automatically completes the interaction with the device under test.
5. The automatic test vector generation device according to claim 3, characterized in that: The first pin receives the trigger signal, and sends the test stimulus signal to the device under test through the third pin and the fourth pin; When the third pin is in a state of sending a signal to the device under test, the controller sets the second pin to 1; When the third pin is in a state of receiving a signal from the device under test, the controller sets the second pin to 0.
6. The automatic test vector generation device according to claim 1, characterized in that: The controller is a microcontroller unit MCU or a field programmable gate array FPGA.
7. A method for automatically generating test vectors, characterized in that: Applied to a test system, the test system includes an automatic test device, a controller and a device under test, and the method includes: The automatic test equipment sends a trigger signal to the controller, collects data on the pins of the device under test, and obtains the DUT pin signal; Receive a trigger signal through the controller and send a test stimulus signal to the device under test; Receiving the test stimulus signal through the device under test and responding; Determine a DUT bidirectional pin indication signal according to a current operating state through a controller, and provide the DUT bidirectional pin indication signal to the automatic test equipment; The test vector is automatically generated according to the DUT pin signal and the DUT bidirectional pin indication signal by automatic test equipment.
8. The automatic test vector generation method according to claim 7, characterized in that: The method of determining the DUT bidirectional pin indication signal according to the current operation state by the controller includes: When the controller is in the state of sending an excitation test signal to a pin of a device under test (DUT), setting the DUT bidirectional pin indication signal to 1; When the controller is receiving a response signal fed back from the device under test (DUT), the DUT bidirectional pin indication signal is set to 0; The response signal is a handshake signal or an advanced stimulus test signal generated based on the test requirements after the controller receives the response.
9. An electronic device, characterized in that: include: at least one memory for storing a computer program; At least one processor is used to execute the program stored in the memory, when the program stored in the memory is executed, the processor is used to execute the method according to claim 7 or 8.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed on a processor, the processor is caused to execute the method according to claim 7 or 8.