Control circuit, hard disk starting circuit, electronic equipment and peak shifting starting control method

Abstract

The invention provides a control circuit, a hard disk starting circuit, electronic equipment and an off-peak starting control method, and is applied to the technical field of off-peak power-on of hard disks. The control circuit comprises a backboard execution circuit and a backboard control circuit. The backboard execution circuit is connected with the backboard control circuit and used for controlling the backboard control circuit to be powered on and work. The backboard control circuit comprises at least two sets of signal transmission ends which are connected with the corresponding hard disks respectively, starting signals are sent to the corresponding hard disks through any set of signal transmission ends, and when hard disk signals fed back by the corresponding hard disks represent that the hard disks are started, starting signals are sent to the corresponding hard disks through any remaining set of signal transmission ends. And the hard disk is started. Therefore, in the process of controlling the hard disk to be powered on and started, the starting signal is sent to any hard disk firstly, after the hard disk is started, the starting signal is sent to any hard disk in the remaining hard disks, and the design cost of the peak shifting circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of hard disk peak-shifted power-on, and in particular to a control circuit, a hard disk startup circuit, an electronic device and a peak-shifted startup control method. Background Art

[0002] With the development of big data technology, electronic devices (such as storage servers) have developed rapidly and their performance has become increasingly higher. As the main configuration of storage models, the performance of hard disks is particularly important, and the reliability of hard disk power supply is the basic condition for the normal operation of hard disks. In storage servers, in order to prevent large inrush currents during the hard disk startup process, multiple hard disks in the storage server are usually required to start at different peaks.

[0003] In recent years, in order to achieve staggered startup of multiple hard disks in storage servers, a startup circuit is separately configured for each hard disk on the hard disk backplane, which greatly increases the cost of the storage server.

[0004] It can be seen that how to use a low-cost design method to achieve staggered startup of hard disks is a problem that technical personnel in this field need to solve. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a control circuit, a hard disk startup circuit, an electronic device and a staggered startup control method, which can solve the cost problem caused by configuring a startup circuit for each hard disk in the prior art to achieve staggered startup of the hard disk.

[0006] To solve the above technical problems, on the one hand, an embodiment of the present invention provides a control circuit, which is applied to a hard disk backplane, including: a backplane execution circuit and a backplane control circuit;

[0007] Wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit;

[0008] The backplane control circuit includes at least two groups of signal transmission ends, which are respectively connected to the corresponding hard disks. A startup signal is sent to the corresponding hard disk through any one group of signal transmission ends. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk is started, a startup signal is sent to the corresponding hard disk through any remaining group of signal transmission ends until all hard disks complete the startup process.

[0009] In some embodiments, the backplane execution circuit is a first programmable memory;

[0010] Wherein, the output end of the first programmable memory is connected to the first end of each hard disk;

[0011] The state signal terminal of the first programmable memory is connected to the first terminal of the backplane control circuit;

[0012] The enable signal terminal of the first programmable memory is connected to the second terminal of the backplane control circuit;

[0013] An input terminal of the first programmable memory is connected to a power supply.

[0014] In some embodiments, the backplane execution circuit further includes: a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0015] The first end of the first resistor is connected to the output end of the first programmable memory, and the second end of the first resistor is connected to the state signal end of the first programmable memory, the first end of the second resistor and the first end of the first capacitor;

[0016] The second end of the second resistor is connected to the first end of the first capacitor and is grounded;

[0017] A first end of the third resistor is connected to an enable signal end of the first programmable memory and a first end of the second capacitor;

[0018] A second end of the third resistor is connected to a second end of the second capacitor and is grounded.

[0019] In some embodiments, the backplane control circuit is a complex programmable logic device;

[0020] The state signal input terminal of the complex programmable logic device is connected to the state signal terminal of the first programmable memory as the first terminal of the backplane control circuit;

[0021] The enable signal input terminal of the complex programmable logic device is connected to the enable signal terminal of the first programmable memory as the second terminal of the backplane control circuit;

[0022] Each enable signal detection terminal of the complex programmable logic device is connected to the second terminal of the corresponding hard disk respectively;

[0023] Each in-place signal detection terminal of the complex programmable logic device is connected to the third terminal of the corresponding hard disk respectively;

[0024] Each status signal detection terminal of the complex programmable logic device is respectively connected to the fourth terminal of the corresponding hard disk; wherein, each enable signal detection terminal of the complex programmable logic device, each in-place signal detection terminal of the complex programmable logic device and each status signal detection terminal of the complex programmable logic device constitute each group of signal transmission terminals of the backplane control circuit.

[0025] On the other hand, the present invention also provides a hard disk startup circuit, which is applied to a hard disk, and includes: a hard disk execution circuit and a hard disk control circuit;

[0026] The hard disk control circuit is connected to the hard disk backplane, and is used to determine the start time according to the start signal sent by the hard disk backplane, and determine the drive signal based on the start signal;

[0027] The hard disk execution circuit is connected to the hard disk control circuit and the hard disk backplane respectively, and is used to determine the corresponding hard disk signal according to the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal represents hard disk startup, it sends a startup signal to the remaining hard disk startup circuits.

[0028] In some embodiments, the hard disk execution circuit is a second programmable memory;

[0029] Wherein, the input end of the second programmable memory is connected to the first end of the hard disk control circuit and the first end of the hard disk backplane;

[0030] The state signal end of the second programmable memory is connected to the second end of the hard disk backplane;

[0031] The enable signal terminal of the second programmable memory is connected to the second terminal of the hard disk control circuit.

[0032] In some embodiments, the hard disk execution circuit further includes: a fourth resistor, a fifth resistor, and a third capacitor;

[0033] Wherein, a first end of the fourth resistor is connected to an output end of the second programmable memory;

[0034] The second end of the fourth resistor is connected to the state signal end of the second programmable memory, the first end of the fifth resistor and the first end of the third capacitor;

[0035] The second end of the fifth resistor is connected to the second end of the third capacitor and is grounded.

[0036] In some embodiments, the hard disk control circuit includes: a comparator, an AND logic operation unit, a first MOS tube, a voltage regulator diode and a sixth resistor;

[0037] The non-inverting input terminal of the comparator is connected to the first terminal of the sixth resistor, and together they serve as the first terminal of the hard disk control circuit and are connected to the input terminal of the second programmable memory;

[0038] The inverting input terminal of the comparator is connected to the second terminal of the sixth resistor and the cathode of the voltage stabilizing diode;

[0039] The pin end of the comparator is connected to the clamp voltage source, and the output end of the comparator is connected to the first end of the logic operation unit;

[0040] The gate of the first MOS tube is connected to the third end of the hard disk backplane as the third end of the hard disk control circuit, and is connected to the fourth end of the hard disk backplane as the fourth end of the hard disk control circuit;

[0041] The drain of the first MOS tube is connected to the clamping voltage source and the second end of the logic operation unit;

[0042] The third terminal of the AND logic operation unit is connected to the enable signal terminal of the second programmable memory as the second terminal of the hard disk control circuit;

[0043] The source of the first MOS tube and the anode of the voltage regulator diode are grounded.

[0044] In some embodiments, the hard disk control circuit further includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor;

[0045] Wherein, the first end of the seventh resistor is connected to the first end of the sixth resistor, and the second end of the seventh resistor is connected to the first end of the eighth resistor and the non-inverting input end of the comparator;

[0046] The first end of the ninth resistor is connected to the second end of the sixth resistor and the cathode of the voltage stabilizing diode, and the second end of the ninth resistor is connected to the first end of the tenth resistor and the inverting input end of the comparator;

[0047] The second end of the tenth resistor is connected to the first end of the eleventh resistor;

[0048] The second end of the eleventh resistor is connected to the second end of the eighth resistor and is grounded.

[0049] In some embodiments, the hard disk control circuit further includes: a second MOS tube;

[0050] Wherein, the gate of the second MOS tube is connected to the output end of the comparator and to the first end of the logic operation unit;

[0051] The source of the second MOS tube is connected to the second end of the eighth resistor and the second end of the eleventh resistor, and is grounded;

[0052] The drain of the second MOS tube is connected to the second end of the tenth resistor and the first end of the eleventh resistor.

[0053] In some embodiments, the hard disk control circuit further includes: a twelfth resistor and a fourth capacitor;

[0054] Wherein, the first end of the twelfth resistor is connected to the output end of the comparator;

[0055] The second end of the twelfth resistor is connected to the first end of the fourth capacitor, the gate of the second MOS tube and the first end of the logic operation unit;

[0056] The second terminal of the fourth capacitor is grounded.

[0057] In some embodiments, the hard disk control circuit further includes: a thirteenth resistor, a fourteenth resistor and a fifth capacitor;

[0058] A first end of the thirteenth resistor is connected to the clamp voltage source;

[0059] The second end of the thirteenth resistor is connected to the drain of the first MOS tube;

[0060] The first end of the fourteenth resistor is connected to the first end of the fifth capacitor, the gate of the first MOS tube and the fourth end of the hard disk backplane;

[0061] The second end of the fifth capacitor is connected to the third end of the hard disk backplane;

[0062] A second terminal of the fourteenth resistor is grounded.

[0063] In some embodiments, the hard disk control circuit further includes: a fuse;

[0064] A first end of the fuse is connected to an input end of the second programmable memory;

[0065] The second end of the fuse is connected to the first end of the sixth resistor and the first end of the seventh resistor.

[0066] On the other hand, the present invention further provides an electronic device, comprising the above-mentioned control circuit and / or hard disk startup circuit.

[0067] On the other hand, the present invention further provides a peak-shift start control method, which is applied to the above-mentioned control circuit, comprising:

[0068] Sending a start signal to a corresponding hard disk start control circuit based on any group of signal transmission terminals;

[0069] Obtain the hard disk signal fed back by the hard disk according to the startup signal;

[0070] When the hard disk signal indicates that the hard disk is started, a start signal is sent to the corresponding hard disk through any remaining set of signal transmission ends until all the hard disks perform the start process.

[0071] In some embodiments, when the hard disk signal indicates that the hard disk is started, sending a start signal to the corresponding hard disk through any remaining group of signal transmission ends includes:

[0072] Determine whether the hard disk signal is a high level signal within a preset time;

[0073] If the hard disk signal is a high level signal within the preset time, the hard disk signal indicates that the hard disk is started, and a start signal is sent to the corresponding hard disk start control circuit through any remaining set of signal transmission ends;

[0074] If the hard disk signal is a low level signal within the preset time, and the hard disk signal indicates that the hard disk is not started, a shutdown signal is sent to the current corresponding hard disk, and a startup signal is sent to the corresponding hard disk through any remaining set of signal transmission ends.

[0075] In some embodiments, after the hard disk signal indicates that the hard disk is not started, the method further includes:

[0076] Trigger the alarm system corresponding to the current hard disk so that the operator can determine the startup status of the hard disk.

[0077] On the other hand, the present invention also provides a peak-shifting start control device, comprising:

[0078] Memory for storing computer programs;

[0079] A processor is used to execute a computer program to implement the steps of the above-mentioned peak-shifting start control method.

[0080] On the other hand, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned peak-shifting start control method are implemented.

[0081] On the other hand, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned peak-shifting start control method when executed by a processor.

[0082] It can be seen from the above technical scheme that the present invention provides a control circuit, which is applied to the hard disk backplane, including: a backplane execution circuit and a backplane control circuit; wherein the backplane execution circuit is connected to the backplane control circuit, and is used to control the power-on operation of the backplane control circuit; the backplane control circuit includes at least two groups of signal transmission terminals, which are respectively connected to the corresponding hard disks, and a start signal is sent to the corresponding hard disk through any one group of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk is started, a start signal is sent to the corresponding hard disk through any remaining group of signal transmission terminals until all the hard disks perform the startup process. It can be seen that the present invention uses a control circuit to control the staggered power-on startup of at least two or more hard disks. In the process of controlling the power-on startup of the hard disk, a start signal is first sent to any one hard disk, and after the hard disk is started, a start signal is sent to any one of the remaining hard disks, so that the hard disks are staggered in sequence according to the order of receiving the start signal. Since the control circuit provided by the present invention has only one backplane execution circuit and one backplane control circuit, the design cost is reduced compared with the staggered startup circuit for controlling the hard disk in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0084] Figure 1 A structural diagram of a control circuit provided by an embodiment of the present invention;

[0085] Figure 2 A circuit diagram for staggered hard disk startup provided by the prior art;

[0086] Figure 3 A circuit diagram of a backplane execution circuit and a backplane control circuit provided in an embodiment of the present invention;

[0087] Figure 4 A structural diagram of a hard disk startup circuit provided by an embodiment of the present invention;

[0088] Figure 5 A circuit diagram of a hard disk execution circuit and a hard disk control circuit provided in an embodiment of the present invention;

[0089] Figure 6 A structural diagram of an electronic device provided by an embodiment of the present invention;

[0090] Figure 7 A flowchart of a peak-shifting startup control method provided by an embodiment of the present invention;

[0091] Figure 8 A structural diagram of a peak-shifting startup control device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0092] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0093] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0094] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0095] Next, a control circuit provided by an embodiment of the present invention is described in detail. Figure 1 A structural diagram of a control circuit provided by an embodiment of the present invention, such as Figure 1 As shown, the control circuit is applied to the hard disk backplane 1, including: a backplane execution circuit 11 and a backplane control circuit 12. In addition, Figure 1 The backplane control circuit 12 includes at least two signal transmission terminals, which are connected to the corresponding hard disks 2.

[0096] In an embodiment, with the development of big data technology, electronic devices (such as storage servers) have developed rapidly, and their performance has become higher and higher. As the main configuration of storage-type models, the performance of the hard disk is particularly important, and the reliability of the hard disk power supply is the basic condition for the hard disk to work normally. In a storage server, in order to prevent a large inrush current during the startup of the hard disk, multiple hard disks in the storage server are usually required to start at different peaks. In recent years, in order to achieve staggered startup of multiple hard disks in a storage server, a backplane startup circuit (PU11-PU1N) is separately configured for each hard disk on the hard disk backplane, and a corresponding hard disk startup circuit (PU21-PU2N) is also configured in the hard disk. The enable signal of the backplane startup circuit on the hard disk backplane is controlled by the complex programmable logic device (CPLD) in the entire electronic device. The circuit diagram for implementing staggered startup of the hard disk in the current electronic device is shown as follows. Figure 2As shown, in the backplane startup circuit (PU11-PU1N), each backplane startup circuit includes a one-time programmable memory (EFUSE) and corresponding three resistors and two capacitors, while in the hard disk startup circuit (PU21-PU2N), each hard disk startup circuit includes a one-time programmable memory (EFUSE) and corresponding three four resistors and two capacitors. The hard disk enable signal EN is obtained by dividing its input voltage. When the input voltage is low, EFUSE will start working and supply power to its back-end load, which may easily cause the hard disk EUFSE to be protected and thus power off. In this design, the hard disk enable signals P12V_NVME1_EN-P12V_NVMEN_EN are obtained by dividing the corresponding input voltages P12V_NVME1_VIN-P12V_NVMEN_VIN. During the power-off process, the outputs P12V_NVME1-P12V_NVMEN will be output again. In the case of non-monotonic power-off, P12V_NVME1_PG-P12V_NVMEN_PG may even become high again, causing false detection. Among them, the one-time programmable memory (EFUSE) in the backplane startup circuit obtains the power signal P12V_STBY and the enable signal P12V_NVME1_VIN_EN-P12V_NVMEN_VIN_EN. It can be seen that a large number of backplane startup circuits are required in the current design, which causes tight board space and increases the cost of the hard disk backplane and server.

[0097] To this end, the present invention provides a control circuit. In the design of the control circuit provided by the present invention, only a backplane execution circuit 11 and a backplane control circuit 12 need to be designed on the hard disk backplane 1. Figure 1 In the circuit connection relationship of the control circuit shown, the backplane control circuit 12 includes at least two groups of signal transmission ends, which are respectively connected to the corresponding hard disks 2. The startup signal is mainly sent to the corresponding hard disk 2 through any one group of signal transmission ends. After receiving the startup signal, the hard disk 2 will generate a corresponding hard disk signal and resend the hard disk signal to the backplane control circuit 12. At this time, the backplane control circuit 12 will judge the hard disk signal. If the current hard disk signal indicates that the hard disk is started, the backplane control circuit 12 will send a startup signal to the corresponding hard disk 2 through any one of the remaining groups of signal transmission ends until the hard disk 2 performs the startup process.

[0098] It should be noted that if the backplane control circuit 12 determines that the hard disk signal indicates that the hard disk is not started, then the backplane control circuit 12 needs to resend the shutdown signal to the corresponding hard disk 2 through the current signal transmission end. The main reason is: if the backplane control circuit 12 determines that the hard disk signal indicates that the hard disk is not started, it means that the current hard disk 2 may be abnormal, which causes the hard disk 2 to be unable to start. In order to ensure that the hard disk 2 is not further damaged, it is necessary to send a shutdown signal to the hard disk 2 to prevent the hard disk 2 from continuing the startup process.

[0099] For example, if the control circuit controls three hard disks (the first hard disk, the second hard disk, and the third hard disk) to be powered on in sequence, the backplane control circuit 12 includes three groups of signal transmission terminals, namely the first group of signal transmission terminals, the second group of signal transmission terminals, and the third group of signal transmission terminals. At this time, the connection relationship of the circuit is: the first group of signal transmission terminals in the backplane control circuit 12 is connected to the first hard disk; the second group of signal transmission terminals in the backplane control circuit 12 is connected to the second hard disk; and the third group of signal transmission terminals in the backplane control circuit 12 is connected to the third hard disk.

[0100] The control circuit under the current design realizes the staggered startup of the hard disk, including the following steps:

[0101] Step 1: The backplane control circuit 12 sends a start signal to the first hard disk through the first group of signal transmission terminals, so that the first hard disk generates a first hard disk signal according to the start signal.

[0102] Step 2: The backplane control circuit 12 receives the first hard disk signal through the first group of signal transmission ends. If the first hard disk signal indicates that the first hard disk is started, the backplane control circuit 12 sends a start signal to the second hard disk through the second group of signal transmission ends, so that the second hard disk generates a second hard disk signal according to the start signal; if the first hard disk signal indicates that the first hard disk is not started, the backplane control circuit 12 sends a shutdown signal to the first hard disk through the first group of signal transmission ends, and then sends a start signal to the second hard disk through the second group of signal transmission ends, so that the second hard disk generates a second hard disk signal according to the start signal.

[0103] Step 3: The backplane control circuit 12 receives the second hard disk signal through the second group of signal transmission ends. If the second hard disk signal indicates that the second hard disk is started, the backplane control circuit 12 sends a start signal to the third hard disk through the third group of signal transmission ends, so that the third hard disk generates a third hard disk signal according to the start signal; if the second hard disk signal indicates that the second hard disk is not started, the backplane control circuit 12 sends a shutdown signal to the second through the second group of signal transmission ends, and then sends a start signal to the third hard disk through the third group of signal transmission ends, so that the third hard disk generates a third hard disk signal according to the start signal.

[0104] Step 4: The backplane control circuit 12 receives the third hard disk signal through the third group of signal transmission ends. If the third hard disk signal indicates that the third hard disk is started, the control circuit under the current design completes the staggered startup of the hard disk; if the third hard disk signal indicates that the third hard disk is not started, the backplane control circuit 12 sends a shutdown signal to the third hard disk through the third group of signal transmission ends, and then the control circuit under the current design completes the staggered startup of the hard disk.

[0105] Step 5: The backplane control circuit 12 summarizes the current signal or data indicating that the hard disk has not started, and displays it through a connected display device for the operator to view.

[0106] It should be noted that step 5 is an optional step, which may or may not exist in the staggered startup process of the hard disk, and can be set according to the needs of the user.

[0107] It should also be noted that the specific process in the example provided by the present invention is started in the order of the first hard disk, the second hard disk and the third hard disk. This is only one possible implementation method, but is not limited to only this implementation method and can be adjusted according to user needs.

[0108] It can be seen from the above technical scheme that the present invention provides a control circuit, which is applied to the hard disk backplane, including: a backplane execution circuit and a backplane control circuit; wherein the backplane execution circuit is connected to the backplane control circuit, and is used to control the power-on operation of the backplane control circuit; the backplane control circuit includes at least two groups of signal transmission terminals, which are respectively connected to the corresponding hard disks, and a start signal is sent to the corresponding hard disk through any one group of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk is started, a start signal is sent to the corresponding hard disk through any remaining group of signal transmission terminals until all the hard disks perform the startup process. It can be seen that the present invention uses a control circuit to control the staggered power-on startup of at least two or more hard disks. In the process of controlling the power-on startup of the hard disk, a start signal is first sent to any one hard disk, and after the hard disk is started, a start signal is sent to any one of the remaining hard disks, so that the hard disks are staggered in sequence according to the order of receiving the start signal. Since the control circuit provided by the present invention has only one backplane execution circuit and one backplane control circuit, the design cost is reduced compared with the staggered startup circuit for controlling the hard disk in the prior art.

[0109] In some embodiments, Figure 3As shown, the backplane execution circuit 11 is a first programmable memory EFUSE1, and the output end (VOUT) of the first programmable memory EFUSE1 is connected to the first end of each hard disk 2 as the first end of the backplane execution circuit 11, so as to realize the transmission of the power supply signal P12V_NVME; the state signal end (PG) of the first programmable memory EFUSE1 is connected to the first end of the backplane control circuit 12 as the second end of the backplane execution circuit 11, so as to realize the transmission of the backplane power state signal P12V_NVME_PG; the enable signal end (EN) of the first programmable memory EFUSE1 is connected to the second end of the backplane control circuit 12 as the third end of the backplane execution circuit 11, so as to realize the transmission of the backplane enable signal P12V_NVME_EN; the input end (VIN) of the first programmable memory EFUSE1 is connected to the power supply as the fourth end of the backplane execution circuit 11, so as to obtain the power supply signal P12V_STBY required by itself.

[0110] In addition, in order to ensure the normal transmission of signals and the voltage does not exceed the threshold of the electronic components, the backplane execution circuit 11 also includes: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a second capacitor C2. The circuit connection relationship at this time is: the first end of the first resistor R1 is connected to the output end (VOUT) of the first programmable memory EFUSE1, the second end of the first resistor R1 is connected to the state signal end (PG) of the first programmable memory EFUSE1, the first end of the second resistor R2 is connected to the first end of the first capacitor C1; the second end of the second resistor R2 is connected to the first end of the first capacitor C1 and is grounded; the first end of the third resistor R3 is connected to the enable signal end (EN) of the first programmable memory EFUSE1 and the first end of the second capacitor C2; the second end of the third resistor R3 is connected to the second end of the second capacitor C2 and is grounded.

[0111] In some embodiments, Figure 3As shown, the backplane control circuit 12 is a complex programmable logic device CPLD. When the backplane control circuit 12 is a complex programmable logic device CPLD, the connection relationship of the circuit is as follows: the state signal input end of the complex programmable logic device CPLD is connected to the state signal end (PG) of the first programmable memory EFUSE1 as the first end of the backplane control circuit 12, so as to realize the transmission of the backplane power state signal P12V_NVME_PG; the enable signal input end of the complex programmable logic device CPLD is connected to the enable signal end (EN) of the first programmable memory EFUSE1 as the second end of the backplane control circuit 12, and each enable signal detection end of the complex programmable logic device CPLD is respectively connected to the second end of the corresponding hard disk 2, so as to transmit the start signal (which can also be understood as the hard disk enable signal) P12V_NVME1 / 3 _EN_N, and at the same time, each enable signal detection end of the complex programmable logic device CPLD is also connected to the power supply to obtain the P3V3_STBY power supply signal; each in-position signal detection end of the complex programmable logic device CPLD is respectively connected to the third end of the corresponding hard disk 2, so as to obtain the disk position signal P12V_NVME1 / 3 representing the disk position sequence number in each current hard disk 2. _INDEF_R_N, and at the same time, each in-place signal detection terminal of the complex programmable logic device CPLD is also connected to the power supply to obtain the P3V3_STBY power signal; each status signal detection terminal of the complex programmable logic device CPLD is respectively connected to the fourth terminal of the corresponding hard disk, for obtaining the hard disk signal P12V_NVME1 / 3 _PG output by hard disk 2 (which can also be understood as the hard disk power status signal of the current hard disk 2).

[0112] In addition, in order to ensure the normal transmission of signals and the voltage does not exceed the threshold of electronic components, the circuit also includes resistors. The resistors are specifically set at each enable signal detection terminal and each in-position signal detection terminal of the complex programmable logic device CPLD. The resistors are respectively: R104, R105, R106, R107, R108 and R109.

[0113] Among them, it should be noted that Figure 3 In the embodiment shown, the complex programmable logic device CPLD includes three enable signal detection terminals, three in-position signal detection terminals and three status signal detection terminals. However, this is only one possible implementation method and can be set according to the needs of the user.

[0114] In the current embodiment, an enable signal detection terminal, a presence signal detection terminal and a status signal detection terminal constitute a group of signal transmission terminals of the backplane control circuit 12. It can be seen that, Figure 3 In the illustrated embodiment, the complex programmable logic device CPLD includes three groups of signal transmission terminals, which can be connected to three hard disks 2 to achieve staggered startup of the three hard disks.

[0115] It can be seen from the above technical solution that the present invention uses a control circuit to control the staggered power-on startup of at least two hard disks. In the process of controlling the power-on startup of the hard disks, a startup signal is first sent to any hard disk, and after the hard disk is started, a startup signal is sent to any hard disk among the remaining hard disks, so that the hard disks are staggered in sequence according to the order of receiving the startup signals. Since the control circuit provided by the present invention has only one backplane execution circuit and one backplane control circuit, the design cost is reduced compared with the staggered startup circuit for controlling the hard disks in the prior art.

[0116] On the other hand, the present invention provides a hard disk startup circuit, such as Figure 4 As shown, the hard disk startup circuit is applied to the hard disk 2, and the hard disk startup circuit includes: a hard disk execution circuit 22 and a hard disk control circuit 21. In addition, Figure 4 The circuit shown includes a hard disk backplane 1. The circuit connection relationship at this time is: the hard disk control circuit 21 is connected to the hard disk backplane 1; the hard disk execution circuit 22 is connected to the hard disk control circuit 21 and the hard disk backplane 1 respectively.

[0117] In the embodiment, the hard disk control circuit 21 is connected to the hard disk backplane 1 to obtain the startup signal sent by the hard disk backplane 1. It should be noted that the hard disk startup circuit can only realize the power-on process of the hard disk after the hard disk control circuit 21 receives the startup signal. After the hard disk control circuit 21 receives the startup signal, it processes the startup signal to obtain the corresponding drive signal. The hard disk execution circuit 22 obtains the drive signal by connecting with the hard disk control circuit 21. After the drive signal passes through the hard disk execution circuit 22, it outputs the hard disk signal, and the hard disk signal indicates whether the hard disk is successfully started. The hard disk backplane 1 obtains the hard disk signal generated by the hard disk execution circuit 22 at this time by connecting with the hard disk execution circuit 22. If the current hard disk signal indicates that the hard disk is started, then the hard disk backplane 1 sends a startup signal to the hard disk control circuit 21 in the remaining hard disks 2; if the hard disk backplane 1 determines that the hard disk signal indicates that the hard disk is not started, then the hard disk backplane 1 needs to re-send the shutdown signal to the hard disk control circuit 21 corresponding to the current hard disk 2, and send a startup signal to the hard disk control circuit 21 in the remaining hard disks 2.

[0118] It can be seen from the above technical scheme that the present invention provides a hard disk startup circuit, which is applied to a hard disk, including: a hard disk execution circuit and a hard disk control circuit; the hard disk control circuit is connected to the hard disk backplane, and is used to determine the startup time according to the startup signal sent by the hard disk backplane, and determine the drive signal based on the startup signal; the hard disk execution circuit is respectively connected to the hard disk control circuit and the hard disk backplane, and is used to determine the corresponding hard disk signal according to the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal represents the startup of the hard disk, the startup signal is sent to the remaining hard disk startup circuits. It can be seen that the present invention uses a hard disk backplane to control the startup time of the hard disk. During the process of powering on the hard disk, the startup of the hard disk is realized based on the startup signal sent by the hard disk backplane. The time when the hard disk backplane sends the startup signal is controllable, so when multiple hard disks exist, the staggered startup of the hard disk can be realized. Compared with the staggered startup circuit for controlling the hard disk in the prior art, the design cost is reduced.

[0119] In some embodiments, Figure 5 As shown, the hard disk execution circuit 22 is the second programmable memory EFUSE2. When the hard disk execution circuit 22 is the second programmable memory EFUSE2, the connection relationship of the circuit is: the input terminal (VIN) of the second programmable memory EFUSE2 is connected to the first terminal of the hard disk control circuit 21 and the first terminal of the hard disk backplane 1, so as to realize the transmission of the power supply signal P12V_NVME; the state signal terminal (PG) of the second programmable memory EFUSE2 is connected to the second terminal of the hard disk backplane 1, so as to realize the transmission of the hard disk signal P12V_NVME1 / N_PG; the enable signal terminal (EN) of the second programmable memory EFUSE2 is connected to the second terminal of the hard disk control circuit 21, so as to realize the transmission of the drive signal P12V_NVME1 / N_EN corresponding to the hard disk execution circuit 22; in addition, the output terminal (OUT) of the second programmable memory EFUSE2 outputs the power supply signal P12V_NVME1 / N.

[0120] In addition, to ensure normal transmission of signals and voltage does not exceed the threshold of electronic components, Figure 5 The hard disk execution circuit 22 shown also includes: a fourth resistor R4, a fifth resistor R5 and a third capacitor C3. Based on this, the connection relationship of the hard disk execution circuit 22 is: the first end of the fourth resistor R4 is connected to the output end (OUT) of the second programmable memory EFUSE2; the second end of the fourth resistor R4 is connected to the state signal end (PG) of the second programmable memory EFUSE2, the first end of the fifth resistor R5 and the first end of the third capacitor C3; the second end of the fifth resistor R5 is connected to the second end of the third capacitor C3 and is grounded.

[0121] In some embodiments, Figure 5As shown, the hard disk control circuit 21 includes: a comparator U1, an AND logic operation unit U2, a first MOS tube Q1, a voltage regulator diode D1 and a sixth resistor R6. At this time, the connection relationship of the circuit is: the in-phase input terminal of the comparator U1 is connected to the first end of the sixth resistor R6, and together as the first end of the hard disk control circuit 21 is connected to the input terminal (VIN) of the second programmable memory EFUSE2; the inverting input terminal of the comparator U1 is connected to the second end of the sixth resistor R6 and the cathode of the voltage regulator diode D1; the pin end of the comparator U1 is connected to the clamping voltage source, and the output end of the comparator U1 is connected to the first end of the AND logic operation unit U2; the gate of the first MOS tube Q1 is connected to the third end of the hard disk backplane 1 as the third end of the hard disk control circuit 21, for realizing the transmission of the start signal P12V_NVME1 / N _EN_N, and is connected to the fourth end of the hard disk backplane 1 as the fourth end of the hard disk control circuit 21, for realizing the disk position signal P12V_NVME1 / N _INDEF_R_N transmission; the drain of the first MOS tube Q1 is connected to the clamping voltage source and the second end of the logic operation unit U2; the third end of the logic operation unit U2 is connected to the enable signal end (EN) of the second programmable memory EFUSE2 as the second end of the hard disk control circuit 21, for realizing the transmission of the driving signal P12V_NVME1 / N_EN; the source of the first MOS tube Q1 and the positive electrode of the voltage regulator diode D1 are grounded.

[0122] besides, Figure 5In the illustrated embodiment, the hard disk control circuit 21 further includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second MOS tube Q2, a twelfth resistor R12, a fourth capacitor C4, a thirteenth resistor R13, a fourteenth resistor R14, a fifth capacitor C5 and a fuse F1. The connection relationship of the hard disk control circuit 21 at this time is as follows: the first end of the seventh resistor R7 is connected to the first end of the sixth resistor R6, the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the non-inverting input end of the comparator U1; the first end of the ninth resistor R9 is connected to the second end of the sixth resistor R6 and the cathode of the voltage stabilizing diode D1, the second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10 and the inverting input end of the comparator U1; the second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11; the second end of the eleventh resistor R11 is connected to the second end of the eighth resistor R8 and is grounded; the gate of the second MOS tube Q2 is connected to the output end of the comparator U1 and to the first end of the logic operation unit U2; the source of the second MOS tube Q2 is connected to the second end of the eighth resistor R8 and the second end of the eleventh resistor R11 and is grounded; the drain of the second MOS tube Q2 is connected to the second end of the tenth resistor R10 The first end of the twelfth resistor R12 is connected to the output end of the comparator U1; the second end of the twelfth resistor R12 is connected to the first end of the fourth capacitor C4, the gate of the second MOS tube Q2 and the first end of the logic operation unit U2; the second end of the fourth capacitor C4 is grounded; the first end of the thirteenth resistor R13 is connected to the clamping voltage source; the second end of the thirteenth resistor R13 is connected to the drain of the first MOS tube Q1; the first end of the fourteenth resistor R14 is connected to the first end of the fifth capacitor C5, the gate of the first MOS tube Q1 and the first four ends of the hard disk backplane 1; the second end of the fifth capacitor C5 is connected to the third end of the hard disk backplane 1; the second end of the fourteenth resistor R14 is grounded; the first end of the fuse F1 is connected to the input end (VIN) of the second programmable memory EFUSE2; the second end of the fuse F1 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7.

[0123] It should be noted that the supply voltage of the clamping voltage source is the voltage clamped by the voltage zener diode D1 , and at this time the voltage is VDD_D21 .

[0124] In an embodiment, the Figure 5The working principle of the complete hard disk control circuit 21 shown is as follows: its signal P12V_NVME passes through the fuse F1 to the sixth resistor R6, and when the back-end circuit is short-circuited, the fuse F1 quickly blows to protect it. The hard disk control circuit 21 can determine whether the output of P12V_NVME1 / N_EN_1 is high or low according to the size of the P12V_NVME input voltage. When P12V_NVME increases to the input threshold of the hard disk control circuit 21, the output P12V_NVME1 / N_EN_1 is high. When P12V_NVME1 / N_EN_1 is high, the conduction of the second MOS tube Q2 is controlled, so that the current hard disk control circuit 21 has a hysteresis function. Its hard disk control circuit 21 can determine whether the output of P12V_NVME1 / N_EN_2 is high or low according to the high and low level states of FM_NVME1 / N_IFDET_R_N. When FM_NVME1 / N_IFDET_R_N is low, P12V_NVME1 / N_EN_2 outputs high. When both P12V_NVME1 / N_EN_1 and P12V_NVME1 / N_EN_2 are high, P12V_NVME1 / N_EN outputs high.

[0125] In the hard disk control circuit 21, when P12V_NVME increases to 3.3V, the voltage zener diode D1 is turned on, and the voltage VDD_D21 is clamped at 3.3V.

[0126] At this time, the voltage at the inverting input terminal Vin- of the comparator U1 is:

[0127] Vin-=UR+=3.3*(R 10 +R 11 ) / (R9+R 10 +R 11 );

[0128] Among them, R 10 is the resistance value of the tenth resistor R10; R 11 is the resistance value of the eleventh resistor R11; R9 is the resistance value of the ninth resistor R9.

[0129] At this time, the voltage at the non-inverting input terminal Vin+ of the comparator U1 is:

[0130] Vin+=P12V_NVME*R8 / (R7+R8);

[0131] Wherein, R8 is the resistance value of the eighth resistor R8; R7 is the resistance value of the seventh resistor R7.

[0132] Based on this, Vin+ and P12V_NVME maintain a linear relationship and increase with the increase of P12V_NVME. When Vin+=Vin-=UR+, the output P12V_NVME1 / N_EN_1 of the comparator U1 is high. When P12V_NVME1 / N_EN_1 is high, the second MOS tube Q2 is driven to conduct and the eleventh resistor R11 is short-circuited.

[0133] At this time, the voltage at the inverting input terminal Vin- of the comparator U1 is:

[0134] Vin-=UR-=3.3*R 10 / (R9+R 10 );

[0135] Since UR- is less than UR+ and the comparator U1 has a hysteresis function, it prevents the output P12V_NVME1 / N_EN_1 from fluctuating back and forth between high and low levels due to fluctuations in the P12V_NVME input voltage.

[0136] It should be noted that the hard disk startup circuit in any hard disk 2 is the above Figure 5 The circuit structure shown.

[0137] In addition, since the specific structure of the hard disk startup circuit provided by the present invention is relatively complex, when any electronic component fails, the signal it finally outputs will fail, thereby causing problems in the hard disk power-on startup process. Therefore, three groups of detection circuits are added to the hard disk startup circuit provided by the present invention, namely, the first group of detection circuits, the second group of detection circuits, and the third group of detection circuits. The first detection circuit is used to connect the first end of the fuse F1 and the output end of the comparator U1, and is used to detect P12V_NVME and P12V_NVME1 / N_EN_1; the second detection circuit is used to connect the gate of the first MOS tube Q1 and the drain of the first MOS tube Q1, and is used to detect P12V_NVME1 / N_EN, FM_NVME1 / N_IFDET_R_N and P12V_NVME1 / N_EN_2; the third detection circuit is used to connect the first end of the logic operation unit U2, the second end of the logic operation unit U2 and the third end of the logic operation unit U2, and is used to detect P12V_NVME1 / N_EN_1, P12V_NVME1 / N_EN_2 and P12V_NVME1 / N_EN. When any one of the signals does not conform to the normal corresponding relationship, the corresponding detection circuit generates an alarm signal for the operator to check.

[0138] It can be seen that the present invention uses a hard disk backplane to control the startup time of the hard disk. During the process of the hard disk powering on and starting, the hard disk starts itself based on the startup signal sent by the hard disk backplane. The time when the hard disk backplane sends the startup signal is controllable. Therefore, when multiple hard disks exist, the hard disks can be started at different times. Compared with the circuit for controlling the staggered startup of the hard disk in the prior art, the design cost is reduced.

[0139] On the other hand, the present invention further provides an electronic device, comprising the above-mentioned control circuit and / or hard disk startup circuit, and having the same beneficial effects.

[0140] If the electronic device is to realize the staggered startup of the hard disk, the electronic device includes multiple hard disks 2. That is to say, in the electronic device currently designed, the hard disk backplane 1 includes a control circuit 13 composed of a backplane execution circuit 11 and a backplane control circuit 12, and the electronic device includes multiple hard disks 2, each of which includes a hard disk startup circuit 23 composed of a hard disk execution circuit 22 and a hard disk control circuit 21. Figure 6 shown.

[0141] In summary, combined with Figure 3 , Figure 5 and Figure 6 The circuit shown in the figure implements the steps of staggered startup of the hard disk 2 in the electronic device as follows:

[0142] Step 1: Build Figure 6 , Figure 3 and Figure 5 The structure shown.

[0143] Step 2: When the backplane control circuit 12 and the backplane execution circuit 11 operate normally, P12V_NVME_EN=1 (high level), its P12V_NMVE outputs normally, and P12V_NVME_PG=1.

[0144] Step 3: The backplane control circuit 12 detects the signal states of FM_NVME1 / N_IFDET_R_N and P12V_NVME1 / N_PG sent by all hard disks 2.

[0145] Step 4: Filter out the disk slots with FM_NVME1 / N_IFDET_R_N=0 and P12V_NVME1 / N_PG=0 (the label of hard disk 2 itself).

[0146] Step 5: Turn on the enable of disk slot 101 (first hard disk 2), and output P12V_NVME1_EN_N=0 (low level). When P12V_NVME1_EN_N=0, the first MOS tube Q1 is not turned on, and P12V_NVME1_EN_2 is high level. If P12V_NVME1_EN_1 and P12V_NVME1_EN_2 are both high level, the output P12V_NVME1_EN of the logic operation unit U2 is high level. At this time, the hard disk execution circuit 22 works normally, P12V_NMVE0 outputs normally, and P12V_NVME1_PG=1.

[0147] Step 6: If P12V_NVME1_PG = 1 within the preset time (for example: 1s), then enable the drive slot 102 (the second hard disk 2 is started), and output P12V_NVME2_EN_N = 0;

[0148] If P12V_NVME1_PG=0 within the preset time, the enable of disk slot 101 is turned off, and P12V_NVME1_EN_N=1 is output, and then the enable of disk slot 102 is turned on, and P12V_NVME2_EN_N=0 is output.

[0149] Step 7: If P12V_NVME2_PG=1 within the preset time, then enable the disk slot 103 and output P12V_NVME3_EN_N=0;

[0150] If P12V_NVME2_PG=0 within the preset time, the enable of the disk slot 102 is turned off, and P12V_NVME2_EN_N=1 is output, and then the enable of the disk slot 103 is turned on, and P12V_NVME3_EN_N=0 is output.

[0151] Step 8: If P12V_NVME3_PG=1 within the preset time, then enable the disk slot 104 and output P12V_NVME4_EN_N=0;

[0152] If P12V_NVME3_PG=0 within the preset time, the enable of the disk slot 103 is turned off, and P12V_NVME3_EN_N=1 is output, and then the enable of the disk slot 104 is turned on, and P12V_NVME4_EN_N=0 is output.

[0153] Step 9: Repeat the same steps for the next disk until all disks are finished.

[0154] It can be seen from the above technical scheme that the present invention provides an electronic device, including: a control circuit and multiple hard disk startup circuits; wherein the control circuit is arranged in the hard disk backplane, and the hard disk startup circuit is arranged in the corresponding hard disk. The hard disk backplane first sends a startup signal to any hard disk, and after the hard disk is started, it sends a startup signal to any hard disk among the remaining hard disks, so that the hard disks are started in a staggered manner in the order of receiving the startup signals. Since there is only one control circuit in the electronic device provided by the present invention, compared with the staggered startup circuit for controlling the hard disk in the prior art, the design cost is reduced, and the tension of the spatial layout of the hard disk backplane is alleviated. At the same time, in the specific control circuit and hard disk startup circuit structure, the hard disk execution circuit can be controlled to start at a higher input voltage to avoid the hard disk execution circuit being protected and powered off due to startup at a lower input voltage. And in the process of powering off the hard disk execution circuit, the output signal is monotonous when the power is off, and will not become a high level in a short time due to fluctuations, thereby affecting the service life of the hard disk.

[0155] On the other hand, the present invention also provides a peak-shift start control method, which is applied to the above control circuit, such as Figure 7 As shown, the peak-shifting start control method includes the following process:

[0156] S10: Sending a start signal to a corresponding hard disk based on any group of signal transmission ends.

[0157] S11: Acquire a hard disk signal fed back by the hard disk according to the startup signal.

[0158] S12: When the hard disk signal indicates that the hard disk is started, a start signal is sent to the corresponding hard disk through any remaining set of signal transmission ends until all the hard disks perform the start process.

[0159] The specific implementation method of step S12 is as follows:

[0160] Determine whether the hard disk signal is a high level signal within a preset time;

[0161] If the hard disk signal is a high level signal within the preset time, the hard disk signal indicates that the hard disk is started, and a start signal is sent to the corresponding hard disk start control circuit through any remaining set of signal transmission ends;

[0162] If the hard disk signal is a low-level signal within a preset time, which indicates that the hard disk is not started, a shutdown signal is sent to the currently corresponding hard disk, and a start signal is sent to the corresponding hard disk through any remaining set of signal transmission ends;

[0163] After the hard disk signal indicates that the hard disk is not started, it also includes:

[0164] Trigger the alarm system corresponding to the current hard disk so that the operator can determine the startup status of the hard disk.

[0165] In an embodiment, the present invention also provides a staggered start-up control method, which is applied to a control circuit, wherein the control circuit includes: a backplane execution circuit and a backplane control circuit; wherein the backplane execution circuit is connected to the backplane control circuit, and is used to control the power-on operation of the backplane control circuit; the backplane control circuit includes at least two groups of signal transmission terminals, which are respectively connected to corresponding hard disks, and a start-up signal is sent to the corresponding hard disk through any group of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk is started, a start-up signal is sent to the corresponding hard disk through any remaining group of signal transmission terminals until all hard disks perform the startup process. It can be seen that the present invention adopts a staggered start-up control method, and utilizes the specific structure of the control circuit to realize the staggered start-up of multiple hard disks. Since the principle provided by the present invention is: one control circuit controls multiple hard disks, compared with the staggered start-up circuit for controlling hard disks in the prior art, the design cost is reduced, and the tension of the space layout of the hard disk backplane is alleviated.

[0166] Figure 8 A structural diagram of a peak-shifting start control device provided by an embodiment of the present invention, such as Figure 8 As shown, the peak-shifting start control device includes: a memory 60 for storing a computer program;

[0167] The processor 61 is used to implement the steps of the peak-shifting start control method in the above embodiment when executing a computer program.

[0168] The staggered start control device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0169] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0170] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein, after the computer program is loaded and executed by the processor 61, it can implement the relevant steps of the staggered start control method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc.

[0171] In some embodiments, the off-peak start control device may also include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0172] Those skilled in the art will understand that Figure 8 The structure shown in does not constitute a limitation on the peak-shifting start control device, and may include more or fewer components than those shown in the figure.

[0173] It is understandable that if the peak-shifting start control method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the current technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program codes.

[0174] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned peak-shifting start control method are implemented.

[0175] Based on this, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned peak-shifting start control method when executed by a processor.

[0176] The above is a detailed introduction to a peak-shifting start control device provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0177] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0178] The above is a detailed introduction to a control circuit, a hard disk startup circuit, an electronic device and a staggered startup control method provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A control circuit, characterized in that: Applied to hard disk backplane, including: backplane execution circuit and backplane control circuit; Wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit; The backplane control circuit includes at least two groups of signal transmission ends, which are respectively connected to corresponding hard disks. A startup signal is sent to the corresponding hard disk through any group of the signal transmission ends. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk is started, a startup signal is sent to the corresponding hard disk through any remaining group of the signal transmission ends until all the hard disks perform the startup process.

2. The control circuit according to claim 1, characterized in that: The backplane execution circuit is a first programmable memory; Wherein, the output end of the first programmable memory is connected to the first end of each of the hard disks; The state signal terminal of the first programmable memory is connected to the first terminal of the backplane control circuit; The enable signal terminal of the first programmable memory is connected to the second terminal of the backplane control circuit; An input terminal of the first programmable memory is connected to a power supply.

3. The control circuit according to claim 2, characterized in that: The backplane execution circuit further includes: a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor; A first end of the first resistor is connected to an output end of the first programmable memory, and a second end of the first resistor is connected to a state signal end of the first programmable memory, a first end of the second resistor, and a first end of the first capacitor; The second end of the second resistor is connected to the first end of the first capacitor and is grounded; A first end of the third resistor is connected to an enable signal end of the first programmable memory and a first end of the second capacitor; The second end of the third resistor is connected to the second end of the second capacitor and is grounded.

4. The control circuit according to claim 2, characterized in that: The backplane control circuit is a complex programmable logic device; The state signal input terminal of the complex programmable logic device is connected to the state signal terminal of the first programmable memory as the first terminal of the backplane control circuit; The enable signal input terminal of the complex programmable logic device is connected to the enable signal terminal of the first programmable memory as the second terminal of the backplane control circuit; Each enable signal detection terminal of the complex programmable logic device is respectively connected to the second terminal of the corresponding hard disk; Each in-place signal detection terminal of the complex programmable logic device is respectively connected to the corresponding third terminal of the hard disk; Each status signal detection terminal of the complex programmable logic device is respectively connected to the corresponding fourth terminal of the hard disk, wherein each enable signal detection terminal of the complex programmable logic device, each in-place signal detection terminal of the complex programmable logic device and each status signal detection terminal of the complex programmable logic device constitute each group of signal transmission terminals of the backplane control circuit.

5. A hard disk startup circuit, characterized in that: Applied to hard disk, including: hard disk execution circuit and hard disk control circuit; The hard disk control circuit is connected to the hard disk backplane, and is used to determine the startup time according to the startup signal sent by the hard disk backplane, and determine the driving signal based on the startup signal; The hard disk execution circuit is respectively connected to the hard disk control circuit and the hard disk backplane, and is used to determine the corresponding hard disk signal according to the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal represents hard disk startup, the startup signal is sent to the remaining hard disk startup circuits.

6. The hard disk startup circuit according to claim 5, characterized in that: The hard disk execution circuit is a second programmable memory; Wherein, the input end of the second programmable memory is connected to the first end of the hard disk control circuit and the first end of the hard disk backplane; The state signal terminal of the second programmable memory is connected to the second terminal of the hard disk backplane; The enable signal terminal of the second programmable memory is connected to the second terminal of the hard disk control circuit.

7. The hard disk startup circuit according to claim 6, characterized in that: The hard disk execution circuit further includes: a fourth resistor, a fifth resistor and a third capacitor; Wherein, a first end of the fourth resistor is connected to an output end of the second programmable memory; The second end of the fourth resistor is connected to the state signal end of the second programmable memory, the first end of the fifth resistor and the first end of the third capacitor; The second end of the fifth resistor is connected to the second end of the third capacitor and is grounded.

8. The hard disk startup circuit according to claim 6, characterized in that: The hard disk control circuit includes: a comparator, an AND logic operation unit, a first MOS tube, a voltage regulator diode and a sixth resistor; Wherein, the non-inverting input terminal of the comparator is connected to the first terminal of the sixth resistor, and together they serve as the first terminal of the hard disk control circuit and are connected to the input terminal of the second programmable memory; The inverting input terminal of the comparator is connected to the second end of the sixth resistor and the cathode of the voltage stabilizing diode; The pin end of the comparator is connected to a clamp voltage source, and the output end of the comparator is connected to the first end of the AND logic operation unit; The gate of the first MOS tube is connected to the third end of the hard disk backplane as the third end of the hard disk control circuit, and is connected to the fourth end of the hard disk backplane as the fourth end of the hard disk control circuit; The drain of the first MOS tube is connected to the clamping voltage source and the second end of the AND logic operation unit; The third terminal of the AND logic operation unit is connected to the enable signal terminal of the second programmable memory as the second terminal of the hard disk control circuit; The source of the first MOS tube and the anode of the voltage regulator diode are grounded.

9. The hard disk startup circuit according to claim 8, characterized in that: The hard disk control circuit further includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; Wherein, the first end of the seventh resistor is connected to the first end of the sixth resistor, and the second end of the seventh resistor is connected to the first end of the eighth resistor and the non-inverting input end of the comparator; The first end of the ninth resistor is connected to the second end of the sixth resistor and the cathode of the voltage stabilizing diode, and the second end of the ninth resistor is connected to the first end of the tenth resistor and the inverting input end of the comparator; The second end of the tenth resistor is connected to the first end of the eleventh resistor; The second end of the eleventh resistor is connected to the second end of the eighth resistor and is grounded.

10. The hard disk startup circuit according to claim 9, characterized in that: The hard disk control circuit further includes: a second MOS tube; Wherein, the gate of the second MOS tube is connected to the output end of the comparator and the first end of the AND logic operation unit; The source of the second MOS tube is connected to the second end of the eighth resistor and the second end of the eleventh resistor, and is grounded; The drain of the second MOS tube is connected to the second end of the tenth resistor and the first end of the eleventh resistor.

11. The hard disk startup circuit according to claim 10, characterized in that: The hard disk control circuit further includes: a twelfth resistor and a fourth capacitor; Wherein, the first end of the twelfth resistor is connected to the output end of the comparator; The second end of the twelfth resistor is connected to the first end of the fourth capacitor, the gate of the second MOS tube and the first end of the AND logic operation unit; A second terminal of the fourth capacitor is grounded.

12. The hard disk startup circuit according to claim 11, characterized in that: The hard disk control circuit further includes: a thirteenth resistor, a fourteenth resistor and a fifth capacitor; The first end of the thirteenth resistor is connected to the clamping voltage source; The second end of the thirteenth resistor is connected to the drain of the first MOS tube; The first end of the fourteenth resistor is connected to the first end of the fifth capacitor, the gate of the first MOS tube and the fourth end of the hard disk backplane; The second end of the fifth capacitor is connected to the third end of the hard disk backplane; A second terminal of the fourteenth resistor is grounded.

13. The hard disk startup circuit according to claim 12, characterized in that: The hard disk control circuit further includes: a fuse; The first end of the fuse is connected to the input end of the second programmable memory; The second end of the fuse is connected to the first end of the sixth resistor and the first end of the seventh resistor.

14. An electronic device, characterized in that: It comprises the control circuit described in any one of claims 1 to 4 and / or the hard disk startup circuit described in any one of claims 5 to 13.

15. A peak-shift start control method, characterized in that: The control circuit as claimed in claim 1 comprises: Sending a start signal to a corresponding hard disk based on any set of signal transmission terminals; Acquire a hard disk signal fed back by the hard disk according to the start signal; When the hard disk signal indicates that the hard disk is started, a start signal is sent to the corresponding hard disk through any remaining group of the signal transmission ends until all the hard disks perform the start-up process.

16. The peak-shift start control method according to claim 15, characterized in that: When the hard disk signal indicates that the hard disk is started, sending a start signal to the corresponding hard disk through any remaining group of the signal transmission ends includes: Determining whether the hard disk signal is a high level signal within a preset time; If the hard disk signal is a high level signal within the preset time, the hard disk signal indicates that the hard disk is started, and a start signal is sent to the corresponding hard disk through any remaining group of the signal transmission ends; If the hard disk signal is a low-level signal within the preset time, and the hard disk signal indicates that the hard disk is not started, a shutdown signal is sent to the currently corresponding hard disk, and a start signal is sent to the corresponding hard disk through any remaining set of the signal transmission ends.

17. The peak-shift start control method according to claim 16, characterized in that: After the hard disk signal indicates that the hard disk is not started, the method further includes: The alarm system corresponding to the hard disk is triggered so that the operator can determine the startup status of the hard disk.

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