Controller for accelerated calculation and accelerated calculation system

Abstract

The embodiment of the invention provides a controller for accelerated calculation and an accelerated calculation system.The controller is characterized in that accelerated calculation units in the same accelerated calculation unit group are sequentially connected through an internal bus and are connected to the same shared memory through the internal bus, so that data sharing is achieved; the acceleration calculation units in the other group adjacent to the acceleration calculation units in different acceleration calculation unit groups are in communication connection, and the acceleration calculation units in the other group located on the opposite side are in communication connection. According to the method and the device, the problem that the calculation efficiency of the acceleration calculation task is reduced due to the fact that the on-chip interconnection technology is restricted by a network topology structure and delay is large in a part of transmission processes in the related technology is solved, and the effect of improving the calculation efficiency of the acceleration calculation system is further achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computers, and in particular, to a controller for accelerated computing, an accelerated computing system, a routing jump method within a controller, a routing jump method between controllers, and an accelerated computing unit scheduling method for accelerated computing tasks. Background Art

[0002] With the continuous development of technologies such as artificial intelligence, big data analysis, and cloud computing, the amount of system data has shown an exponential growth trend, which in turn has led to an increasing demand for data processing and analysis. Among the related technologies, traditional single-architecture database systems face huge challenges. Their ability to process massive amounts of data, ensure data real-time, and cope with diverse workloads is relatively insufficient.

[0003] Heterogeneous acceleration architectures usually combine controllers with other processors to achieve high-performance computing by leveraging the advantages of different processors. In heterogeneous acceleration architectures, the interconnection and communication of the acceleration computing units inside the controller has a key impact on the overall performance of the system. By improving the interconnection structure inside the controller, the data transmission path can be shortened and the bandwidth can be increased, which can effectively reduce the system transmission delay. This allows data to be scheduled and transmitted in an orderly and efficient manner between acceleration computing units, giving full play to the advantages of each acceleration computing unit and improving the overall performance of the system.

[0004] In the related art, bus-based interconnection and on-chip interconnection technology are generally used to realize the interconnection of accelerated computing units. However, when multiple computing units request azimuth memory at the same time, bus-based interconnection has bus competition, resulting in insufficient bandwidth allocation and increased latency. Therefore, this shortcoming of bus-based interconnection is inevitable in large-scale systems. On the other hand, on-chip interconnection technology depends on network topology and link length limitations. In some transmission processes, there are many jumps and obvious delays. In terms of hardware, on-chip interconnection technology requires a large number of routers and links to build the network, resulting in an increase in chip area and power consumption. In addition, when transmitting across devices, the link width has a greater impact on the transmission rate, which will affect the overall performance of the accelerated computing system.

[0005] In summary, the accelerated computing system in the related technology has the problem that the on-chip interconnection technology is restricted by the network topology structure, and there is a large delay in some transmission processes, which leads to a decrease in the computing efficiency of the accelerated computing tasks. Summary of the invention

[0006] Embodiments of the present invention provide a controller for accelerated computing, an accelerated computing system based on the controller, a routing jump method within the controller, a routing jump method between controllers, and an accelerated computing unit scheduling method for accelerated computing tasks, so as to at least solve the problem in the related art that since the on-chip interconnection technology is restricted by the network topology structure, there is a large delay in some transmission processes, resulting in a decrease in the computing efficiency of the accelerated computing tasks.

[0007] According to one embodiment of the present invention, a controller for accelerated computing is provided, comprising: a plurality of accelerated computing unit groups, wherein adjacent accelerated computing unit groups are connected to each other in communication with each other, and are arranged in a completely symmetrical ring shape, wherein the accelerated computing units in the same accelerated computing unit group are connected in sequence through an internal bus, and the accelerated computing units in different accelerated computing unit groups that are located at symmetrical positions of the same diameter of the ring shape are connected to each other in communication with each other;

[0008] Each accelerated computing unit group also includes a shared memory, and the shared memory is connected to each accelerated computing unit through an internal bus.

[0009] In an exemplary embodiment, the controller also includes: a device-side controller, which is used to receive data packets in CXL format, parse the data packets to obtain accelerated computing tasks and send them to the accelerated computing unit; a switching module, which is connected to the device-side controller via a CXL bus and communicates with the accelerated computing unit via an internal bus, and is used to receive accelerated computing tasks through direct memory access and send them to the accelerated computing unit.

[0010] In an exemplary embodiment, the switching module includes a multi-stage switching module, including a switching module connected to a device-side controller through a CXL bus and connected to other switching modules through multiple interfaces with output signals in a master mode, and a switching module connected to other switching modules, connected to a shared memory through an interface with an output signal in a slave mode, and connected to an accelerated computing unit through an interface with an output signal in a master mode.

[0011] In an exemplary embodiment, the controller also includes: an on-chip routing module, which is respectively connected to each accelerated computing unit group for implementing routing jumps within the same controller; and an inter-chip routing module, which is connected to the on-chip routing module for implementing routing jumps between different controllers.

[0012] In an exemplary embodiment, the on-chip routing module includes a first cross switch and a first cross switch control unit, wherein the first cross switch is used to connect each accelerated computing unit group and the inter-chip routing module, and the first cross switch control unit is used to control the on and off of the path connected by the first cross switch.

[0013] In an exemplary embodiment, the inter-chip routing module includes a second cross switch and a second cross switch control unit, wherein the second cross switch is used to connect the intra-chip routing module and the multiple-to-one selector, and the second cross switch control unit is used to control the on-off of the path connected to the second cross switch.

[0014] In an exemplary embodiment, the intra-chip routing module or the inter-chip routing module includes a virtual channel control unit, which is used to divide a physical channel into multiple virtual channels to prevent the channel closed loop from causing a deadlock phenomenon.

[0015] In an exemplary embodiment, the virtual channel control unit is specifically used to construct multiple independent micro-chip buffers in the output queue buffer corresponding to the physical channel to obtain multiple virtual channels; divide the virtual channels into a first channel group and a second channel group in a clockwise direction; when the routing coordinates of the source node are greater than the routing coordinates of the target node, the first channel group is used; when the routing coordinates of the source node are less than or equal to the routing coordinates of the target node, the second channel group is used.

[0016] In an exemplary embodiment, when the accelerated computing unit group is in the first operating mode, the accelerated computing units in the group are allowed to be configured to perform different computing functions.

[0017] In an exemplary embodiment, when the accelerated computing unit group is in the second working mode, the accelerated computing units in the group are configured to perform the same computing function so that if any accelerated computing unit in the group fails, other accelerated computing units in the group can be used to replace it.

[0018] In an exemplary embodiment, in one implementation of the present invention, the controller is one of FPGA, ARM and AVR.

[0019] According to another embodiment of the present invention, an accelerated computing system is provided, which includes: a host; multiple controller clusters, used to execute accelerated computing tasks issued by the host, each controller cluster includes multiple controllers; a switching chip, connected to the host and the controller clusters through a bus, and used to realize data interaction between the host and the controller clusters.

[0020] In an exemplary embodiment, the controllers in the controller cluster are configured as a fully connected structure.

[0021] In an exemplary embodiment, the switch chip supports at least the CXL communication protocol.

[0022] In an exemplary embodiment, the controller cluster further includes a multiple-to-one selector for receiving signals generated inside the controller and transmitting the signals to other controllers or a host.

[0023] According to another embodiment of the present invention, a routing jump method inside a controller is provided, including: configuring the routing coordinates of an accelerated computing unit inside the controller, the routing coordinates including a controller ID, an accelerated computing unit group ID, and an accelerated computing unit ID; determining the routing coordinates of a source node and a target node based on a routing jump request, and calculating the number of intra-chip jump steps based on the routing coordinates of the source node and the routing coordinates of the target node; determining a routing jump direction based on the number of intra-chip jump steps, and performing routing jump based on the routing jump direction.

[0024] In an exemplary embodiment, performing route jumping based on the route jumping direction includes: acquiring the output buffer length of the controller port; and performing reverse routing when the output buffer length is greater than a fifth threshold.

[0025] In an exemplary embodiment, determining the route jump direction based on the number of intra-chip jump steps includes: determining the route jump direction based on a preset range of the number of intra-chip jump steps, the route jump direction including clockwise, counterclockwise, opposite direction or a combination of clockwise, counterclockwise and opposite direction.

[0026] In an exemplary embodiment, a controller includes a plurality of accelerated computing unit groups, wherein the accelerated computing units in the same accelerated computing unit group are connected in sequence through an internal bus and connected to the same shared memory through the internal bus, and the accelerated computing units in another group adjacent to the accelerated computing units in different accelerated computing unit groups are communicated and connected, and the accelerated computing units in another group opposite to the accelerated computing units are communicated, and the route jump direction is determined based on a preset range of the number of jump steps within the chip, and the method includes: when the number of jump steps within the chip is equal to a first threshold, determining the clockwise direction as the route jump direction; when the number of jump steps within the chip is equal to a second threshold, determining the clockwise direction as the route jump direction. The face direction is determined as the routing jump direction; when the number of jump steps within the chip is equal to the third threshold, the counterclockwise direction is determined as the routing jump direction; when the number of jump steps within the chip is less than the first threshold, the counterclockwise direction is determined as the routing jump direction; when the number of jump steps within the chip is greater than the first threshold and less than the second threshold, the face direction is first determined as the routing jump direction, and then the clockwise direction; when the number of jump steps within the chip is greater than the second threshold and less than the third threshold, the face direction is first determined as the routing jump direction, and then the counterclockwise direction; when the number of jump steps within the chip is greater than the third threshold and less than the fourth threshold, the clockwise direction is determined as the routing jump direction.

[0027] According to another embodiment of the present invention, a method for routing jump between controllers is provided.

[0028] The controller includes an intra-chip routing module and an inter-chip routing module, wherein the intra-chip routing module is respectively connected to each acceleration computing unit group in communication, and the inter-chip routing module is connected to the intra-chip routing module in communication. The method includes: configuring the routing coordinates of the acceleration computing unit inside the controller, the routing coordinates include the controller ID, the acceleration computing unit group ID and the acceleration computing unit ID; determining the routing coordinates of the source node and the routing coordinates of the target node based on the routing jump request; jumping from the intra-chip routing module corresponding to the source node to the inter-chip routing module corresponding to the source node based on the routing coordinates of the source node, jumping from the inter-chip routing module corresponding to the source node to the inter-chip routing module corresponding to the target node according to the routing coordinates corresponding to the target node, and jumping from the inter-chip routing module corresponding to the target node to the intra-chip routing module corresponding to the target node according to the routing coordinates corresponding to the target node, and transmitting to the target node.

[0029] According to another embodiment of the present invention, there is provided an accelerated computing unit scheduling method for accelerated computing tasks, the accelerated computing unit scheduling method being applied to an accelerated computing system, the method comprising: obtaining an accelerated computing unit status table and a memory access delay table, the computing unit status table being used to at least include the routing coordinates, unit functions, unit status and storage occupancy of the accelerated computing unit, the memory access delay table including the delay of each accelerated computing unit accessing each shared cache; obtaining a computing task to be assigned, and determining a scheduling strategy based on the computing unit status table and the memory access delay table, wherein in the process of determining the scheduling strategy, accelerated computing units with different storage occupancy can run in parallel, and each accelerated computing unit in the scheduling strategy corresponds to a computing task to be assigned with the smallest delay.

[0030] Through the present invention, since the controller of the present invention adopts an improved on-chip interconnect structure based on a packet bus, the accelerated computing units inside the controller are grouped, each group shares a memory, and routing jumps within the group can be directly completed through the shared memory. The accelerated computing units of different groups are diagonally connected through the on-chip interconnect technology, and the groups are connected in sequence. There is no need to jump one by one in sequence, which reduces the jump steps in the jump process, and the shared memory reduces global bus competition. Therefore, it can solve the problem in the related technology that due to the restriction of the on-chip interconnect technology by the network topology structure, there is a large delay in part of the transmission process, resulting in a decrease in the computing efficiency of the accelerated computing task, so as to improve the communication efficiency within the controller and between controllers, reduce communication delays, and improve the overall performance of the accelerated computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of a topological structure of a controller for accelerating computing according to an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of a connection structure of a controller for accelerated computing according to an embodiment of the present invention;

[0033] Figure 3 is a schematic diagram of the structure of an on-chip routing module according to an embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of an inter-chip routing module according to an embodiment of the present invention;

[0035] Figure 5 is a logic schematic diagram of a crossbar switch according to an embodiment of the present invention;

[0036] Figure 6 is a schematic structural diagram of a controller-based accelerated computing system according to an embodiment of the present invention;

[0037] Figure 7 is a schematic diagram of a fully connected structure of a controller cluster according to an embodiment of the present invention;

[0038] Figure 8 is a flow chart of a routing jump method inside a controller according to an embodiment of the present invention;

[0039] Fig. 9 is a flow chart of a method for routing jumps between controllers according to an embodiment of the present invention;

[0040] Fig.10 It is a flowchart of a method for scheduling an accelerated computing unit for an accelerated computing task according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0043] For the convenience of description, some nouns or terms involved in the embodiments of the present invention are explained below:

[0044] Field Programmable Gate Array: Field Programmable Gate Array, abbreviated as FPGA, is a programmable semiconductor device that allows users to configure its hardware according to their needs. FPGA contains programmable logic blocks and configurable interconnections. Users can implement different hardware logic by loading different configuration files.

[0045] Direct Memory Access technology: Direct Memory Access, referred to as DMA, is a technology that allows hardware subsystems to exchange data directly with system memory without the direct control of the CPU. The DMA controller can directly transfer data from input devices to memory, or from memory to output devices without the intervention of the CPU, thereby reducing the burden on the CPU and improving data transfer efficiency.

[0046] Peripheral Component Interconnect Express, referred to as PCIe, is a universal serial expansion bus standard used to connect hardware components inside a computer. It is widely used in high-speed data communications and peripheral device connections for its high data transfer rate and flexibility.

[0047] Compute Express Link: Compute Express Link, or CXL, is an open, high-speed interconnect technology standard designed to provide higher data throughput and lower communication latency for modern data centers, high-performance computing systems and other compute-intensive applications.

[0048] In some solutions, the controller using on-chip interconnect technology is restricted by the network topology structure, and there is a large delay in some transmission processes, resulting in a decrease in the computing efficiency of accelerated computing tasks. In order to solve the above technical problems, in this embodiment, a controller for accelerated computing, an accelerated computing system, a routing jump method inside the controller, a routing jump method between controllers, and an accelerated computing unit scheduling method for accelerated computing tasks are provided.

[0049] In an embodiment of the present invention, a controller for accelerating computing is provided, and its topology diagram is as follows: Figure 1 The controller includes: a plurality of accelerated computing unit groups, adjacent accelerated computing unit groups are connected to each other in communication, and are arranged in a completely symmetrical ring. Accelerated computing units in the same accelerated computing unit group are connected in sequence through an internal bus, and accelerated computing units in different accelerated computing unit groups located at symmetrical positions of the same diameter of the ring are connected to each other in communication; each accelerated computing unit group also includes a shared memory, and the shared memory is connected to each accelerated computing unit through an internal bus.

[0050] In the accelerated computing system in the related art, the accelerated computing unit and memory in the controller used for accelerated computing usually use a single bus or a complex on-chip interconnection network. The above interconnection method has the problem of increased delay and bandwidth bottleneck caused by bus competition and excessive hopping when multiple units perform parallel computing and data access. Taking FPGA as an example, if multiple accelerated computing units access DDR / HBM memory at the same time, the traditional bus interconnection will lead to uneven bandwidth distribution and data transmission delay caused by hopping between accelerated computing units.

[0051] In the above embodiments of the present invention, Figure 1 As shown, the overall topology of the controller is ring-shaped and completely symmetrical. Within each accelerated computing unit group, the accelerated computing units are connected through an internal bus and share the same memory resources to ensure efficient data transmission and access within the group. The accelerated computing units between different groups are connected in a specific way. Specifically, adjacent accelerated computing unit groups are connected in sequence, and each accelerated computing unit communicates with the accelerated computing unit located opposite to it to minimize the jumps and delays in cross-group communication and optimize the overall interconnection performance.

[0052] In a specific embodiment, Figure 1 As shown, taking the FPGA chip as an example, in the topology structure, in a clockwise direction, every four nodes are divided into a group (group 0, group 1, group 2 and group 3). Taking group 0 as an example, the accelerated computing unit 0, accelerated computing unit 1, accelerated computing unit 2 and accelerated computing unit 3 in group 0 are all connected to the same shared memory DDR / HSM_0 through an internal bus. The above structural design enables the computing units in the group to efficiently access the local memory. It can be understood that the accelerated computing unit 0 and the accelerated computing unit 3 can jump through the shared memory DDR / HSM_0 using the above structure. Compared with the prior art of jumping from accelerated computing unit 0 to accelerated computing unit 3 one by one, the access delay caused by the jump step within the group is reduced.

[0053] In a specific embodiment, Figure 1 As shown, taking the FPGA chip as an example, in the topology structure, taking group 0 and group 1 as an example, the adjacent accelerated computing unit 3 and accelerated computing unit 4 are directly connected to communicate with each other, and taking group 0 and group 2 as an example, the accelerated computing unit 2 and accelerated computing unit 10 located opposite to each other are directly connected to communicate with each other. Through the above structure, the accelerated computing unit 0 and the accelerated computing unit 7 can jump through the path of 0-8-7, and the accelerated computing unit 1 and the accelerated computing unit 5 can jump through the path of 1-3-4-5, which greatly reduces the access delay caused by the jump in the group compared to the clockwise or counterclockwise routing jump in the prior art.

[0054] In summary, the present invention can significantly reduce the delay of data transmission and improve the efficiency of data exchange between accelerated computing units by setting specific intra-group and inter-group communication paths. In addition, an internal bus is used within the group to implement shared memory, ensuring that the accelerated computing unit can efficiently utilize local resources and avoid the decrease in resource utilization efficiency caused by insufficient bandwidth allocation. And grouping the accelerated computing units can better support large-scale parallel computing. In addition, a ring-shaped and completely symmetrical topological structure is set up so that the accelerated computing unit is placed in any position in the above-mentioned architecture, and its routing rules and effects are completely consistent, ensuring that the performance deviation caused by the distribution position of accelerated computing units with different functions does not need to be considered in the process involved, and the above-mentioned topological structure has a lower node degree and network diameter, which is conducive to optimizing transmission delay. The use of the above-mentioned controller for accelerated computing can provide more powerful heterogeneous computing capabilities for database acceleration, deep learning and other fields.

[0055] In an embodiment of the present invention, the interconnection logic block diagram of the above controller is as follows: Figure 2 The controller includes: a device-side controller, which is used to receive a data packet in CXL format, parse the data packet to obtain an accelerated computing task, and send it to the accelerated computing unit.

[0056] In the related art, heterogeneous computing systems use CXL buses to connect components. It is understandable that CXL, as an open high-speed interconnection technology standard, is widely used to connect devices such as CPUs, GPUs, accelerators, and memory to achieve low-latency, high-bandwidth data transmission. Therefore, in order to ensure data transmission in CXL format, the present invention configures a device-side controller in the controller to receive and parse CXL format data packets. Figure 2 As shown, the device-side controller (CXL device-side controller) in the chip is connected to the host through the CXL bus in the controller architecture of the present invention, and is responsible for receiving data packets and task parsing through the CXL bus. Specifically, when the host sends an accelerated computing task in a CXL format data packet through the CXL bus, the device-side controller receives the data packet, parses it, extracts the specific accelerated computing task and related parameters required for the accelerated computing, and then sends the accelerated computing task to the corresponding specific accelerated computing unit.

[0057] In a specific embodiment, it is assumed that the host needs to perform an accelerated computing task for database query, which includes steps such as data packet decompression, full table scanning, and expression filtering. In the process of sending the accelerated computing task, the host encapsulates these tasks into CXL format data packets and sends them to the device-side controller through the CXL bus. After receiving the data packet, the device-side controller parses it according to the CXL protocol and extracts information such as the task type, data element location, and target memory address. Then, the device-side controller selects an accelerated computing unit with corresponding functions according to the operating status of the accelerated computing unit, and sends the relevant information to the accelerated computing unit through the internal bus.

[0058] The device-side controller is directly connected to the CXL bus and the internal bus, so that the relevant data and control information of the accelerated computing task can be received and processed by the accelerated computing unit with minimal delay. In addition, the device-side controller can dynamically schedule tasks according to the function and status of the computing unit, thereby achieving parallel execution of tasks and optimal allocation of accelerated computing unit resources, ensuring that the delay of the accelerated computing task is minimized.

[0059] The switching module is connected to the device-side controller via a CXL bus, and communicates with the accelerated computing unit via an internal bus. It is used to receive accelerated computing tasks through direct memory access and send them to the accelerated computing unit.

[0060] The function of the switching module is to serve as a bridge between the device-side controller and the accelerated computing unit. The present invention connects the device-side controller and the switching module through a CXL bus, so that the device-side controller transmits data to the switching module in the form of direct memory access (DMA) without the need for CPU access, thereby greatly improving data transmission efficiency, reducing computing delays, and ensuring high-speed data transmission and protocol compatibility; the accelerated computing unit and the switching module communicate through an internal bus, thereby achieving efficient scheduling of accelerated computing tasks between accelerated computing units.

[0061] The introduction of DMA technology between the switching module and the device-side controller ensures high-speed, low-power transmission of data between the device-side controller and the accelerated computing unit, thereby improving overall computing efficiency.

[0062] In summary, the combined use of the device-side controller and the switching module enables efficient reception, parsing and execution of accelerated computing tasks in the controller accelerated computing system, as well as fast and low-latency transmission of data between the accelerated computing unit and the memory, significantly improving the performance and response speed of the controller in database accelerated computing tasks.

[0063] In the embodiment of the present invention, Figure 2As shown, the switching module includes a multi-stage switching module, including a switching module connected to the device side controller through a CXL bus and connected to other switching modules through multiple interfaces with output signals in the main mode, and a switching module connected to other switching modules, connected to a shared memory through an interface with an output signal in the slave mode, and connected to an accelerated computing unit through an interface with an output signal in the main mode.

[0064] In order to optimize the data transmission path and reduce the number of ports, the present invention proposes an interconnection mechanism based on a multi-stage switching module, in which master mode and slave mode interfaces are used to distinguish links with different functions. The multi-stage switching module includes at least two levels of switching modules, namely the top-level switching module and the bottom-level switching module, wherein the top-level switching module is directly connected to the device-side controller and receives CXL format data packets from the device-side controller through the CXL bus. The output signal interface of the top-level switching module is set to the master mode, and it is connected to the switching module in the next level group through these interfaces to distribute the data packets to different groups. The bottom-level switching module is respectively connected to the shared memory (slave mode interface) and the accelerated computing unit in the accelerated computing unit group (master mode interface), and is responsible for sending them to the specified accelerated computing unit according to task requirements.

[0065] In a specific embodiment, Figure 2 As shown in the figure, in a 16-node controller, the accelerated computing units are divided into four groups, each with 4 accelerated computing units, and each group includes a shared memory. The switching module includes only two layers, including the top-level switching module (Crossebar) and the bottom-level switching modules (Crossebar_0 to Crossebar_3). Each bottom-level switching module is connected to a group of accelerated computing units, and all bottom-level switching modules are directly connected to the top-level switching module. In the specific workflow, the host sends accelerated computing tasks to the device-side controller through the CXL bus. These tasks may include data reading, page parsing, expression filtering, multi-table connection, etc. After the device-side controller parses the received CXL data packet, it decomposes the task and forwards it to the top-level switching module through the CXL bus using DMA technology. After receiving the instruction, the top-level switching module distributes the data packet to the corresponding intra-group switching module through the master mode interface according to the task requirements and the distribution of computing units. After receiving the task data assigned to its group, the intra-group switching module uses the slave mode interface to exchange data with the shared memory and load the required data into the memory. At the same time, the master mode interface of the intra-group switching module sends the data packet to the accelerated computing unit in the group to perform specific tasks. After completing the task, the accelerated computing unit stores the result in the shared memory, and then the intra-group switching module sends the result data to the top-level switching module through the slave mode interface, or directly transmits it inside the chip. Finally, the data can be accessed by other computing units or the host.

[0066] By setting up multi-level switching and DMA data transmission, the controller of the present invention avoids the bottleneck problem in bus interconnection in the related technology and improves the output transmission efficiency. The underlying switching module and the accelerated computing unit in the multi-level switching mechanism are grouped and connected, which facilitates the transmission of data packets along the optimal path. At the same time, the design of the master mode and slave mode interface simplifies the data scheduling between the computing unit and the shared memory, thereby realizing efficient allocation of computing resources.

[0067] In the embodiment of the present invention, Figure 3 As shown, the controller also includes: an on-chip routing module, which is respectively connected to each acceleration computing unit group for communicating and realizing routing jumps within the same controller.

[0068] In the related art, in order to achieve high-performance and low-latency data transmission in a controller-based heterogeneous acceleration system, the routing module plays an indispensable role. It is responsible for correctly transmitting data packets from the source node to the target node. This process is very important in a complex system architecture. In order to ensure the correct transmission of data packets within the chip, the present invention is configured to use an on-chip routing module to be responsible for routing data packets between computing unit groups within a single controller. The on-chip routing module is closely connected to the acceleration computing unit and the switching module of each group, and realizes rapid data transmission through a low-latency interconnection structure. When a computing unit needs to access the memory of other groups or exchange data with the computing unit of another group, the on-chip routing module efficiently completes the jump routing of the data packet according to the deterministic routing algorithm, ensuring that the data transmission path is the shortest and the latency is the lowest.

[0069] In a specific embodiment, Figure 3 As shown in the figure, in the 16-node controller architecture, the on-chip routing module is involved as a router with 5 ports, including a clockwise port, a counterclockwise port, an opposite port, a local port (connected to the local accelerated computing unit) and an inter-chip port for connecting the inter-chip routing module. When a data packet needs to be transmitted between different groups inside the chip, the on-chip routing module first parses the routing ID of the data packet, determines the location of the target node, and then transmits the data through the most appropriate port (such as a clockwise or counterclockwise port) to achieve the shortest path jump. For example, if the destination of the data packet is another group located in the clockwise direction, the on-chip routing module will perform a routing jump through the clockwise port, which can avoid unnecessary detours and improve data transmission efficiency.

[0070] The on-chip routing module ensures that data packets are transmitted within the controller architecture with the shortest path and lowest latency, improving the overall response speed of the system. The on-chip routing module is connected to the accelerated computing unit in the form of a group. During the jump process, deterministic and adaptive routing algorithms can be used to optimize the data transmission path, avoid resource waste and path bottlenecks, and ensure that the computing unit can efficiently utilize local and remote resources.

[0071] In the embodiment of the present invention, Figure 4 As shown, the controller also includes: an inter-chip routing module, which is in communication connection with the intra-chip routing module and is used to implement routing jumps between different controllers.

[0072] The inter-chip routing module is mainly used to process the output transmission between different controllers. In complex accelerated computing tasks, multiple controllers configured to work together may be required. At this time, the inter-chip routing module acts as a communication bridge between different controllers, responsible for cross-chip data packet routing jumps, and realizes efficient data transmission and routing selection.

[0073] In a specific embodiment, Figure 4 As shown in FIG. 1 , in a 16-node controller architecture, the inter-chip routing module is involved as a router with 5 ports, four of which are connected to different on-chip routing modules inside the controller, and one port is connected to the inter-chip routing module inside other controllers. The inter-chip routing module is used to receive data packets sent by the on-chip routing module, decode them according to the controller ID and the accelerated computing unit group ID in the routing ID, and select the corresponding controller node for data transmission. For example, if the source node of the data packet is located in group 1 of controller 0, and the destination node is located in group 3 of controller 2, the inter-chip routing module 0 first sends the data packet to the inter-chip routing module 2 of controller 2 through the inter-chip fully connected port, and then the on-chip routing module of controller 2 performs the final routing jump of the data packet according to the group ID and the ID of the target node in the group through the shortest path principle to ensure that the data reaches the destination directly.

[0074] The involvement of the on-chip routing module ensures that data packets are transmitted between controller architectures with the shortest path and lowest latency, improving the overall response speed of the system. The inter-chip routing module is connected to the on-chip routing module in the form of a group. During the jump process, deterministic and adaptive routing algorithms can be used to optimize the data transmission path, avoid resource waste and path bottlenecks, and ensure that the computing unit can efficiently utilize local and remote resources. The existence of the inter-chip routing module supports efficient communication between multiple controllers, making it possible to expand the heterogeneous acceleration system, so that the system can support a larger number of accelerated computing units to meet more complex and larger-scale accelerated computing needs.

[0075] In an embodiment of the present invention, the on-chip routing module includes a first cross switch and a first cross switch control unit, wherein the first cross switch is used to connect each accelerated computing unit group and the inter-chip routing module, and the first cross switch control unit is used to control the on and off of the path connected by the first cross switch.

[0076] In the accelerated computing system of the related art, the on-chip communication efficiency has a key impact on the overall performance of the accelerated computing system, and the cross switch is a key component for data transmission routing selection, which can effectively connect different nodes and realize the rapid forwarding of data packets. The present invention sets a first cross switch to be responsible for establishing connections between different accelerated computing unit groups inside the chip and with the routing modules between chips, and the first cross switch control unit ensures the correctness and efficiency of these connections.

[0077] In a specific embodiment, Figure 5 As shown, the first cross switch in the on-chip routing module is designed as a 5×5 switching matrix, which can be connected to the clockwise direction, counterclockwise direction, opposite direction, local accelerated computing unit group and inter-chip routing module. This design allows data packets to flow freely in different directions. For example, the four accelerated computing unit groups in the 16-node controller are connected through the first cross switch, and the inter-chip routing module also establishes connections with these groups through the first cross switch. The first cross switch control unit is responsible for parsing the routing information of the data packet, and controls the on and off of the first cross switch connection path based on this information to achieve accurate data routing. Specifically, when a data packet needs to be transmitted from a certain accelerated computing unit group to another group or an inter-chip routing module, the first cross switch control unit will decide whether the data packet should be transmitted through a clockwise port, a counterclockwise port, an opposite direction port or a local port based on the routing ID of the data packet and the current link load. If there is link congestion, the control unit will automatically select a path with a lighter load to achieve adaptive load balancing. For example, in Figure 4 In the logic diagram, the first cross switch control unit needs to monitor the load conditions of all inputs [0-4] and outputs [0-4]. When a data packet enters from input [0] (clockwise), if the buffer of output [1] (counterclockwise) is not full, the first cross switch is controlled to allow the data packet to flow directly from input [0] to output [1], thereby completing the data transmission in the clockwise direction.

[0078] Through the on-chip routing module including the first cross switch and the first cross switch control unit, the present invention realizes efficient data transmission and adaptive routing selection, which not only optimizes the communication between computing units, but also improves the interaction efficiency with the inter-chip routing module, and provides powerful hardware support for high data-intensive tasks such as database accelerated computing and deep learning.

[0079] In an embodiment of the present invention, the inter-chip routing module includes a second cross switch and a second cross switch control unit, wherein the second cross switch is used to connect the intra-chip routing module with other controllers, and the second cross switch control unit is used to control the on-off of the path connected by the second cross switch.

[0080] The second cross switch is a high-performance switching matrix that is the same as the first cross switch. In the inter-chip routing module, the second cross switch is configured to connect the intra-chip routing module and the multiple-choice selector to achieve cross-chip data packet routing. Figure 4 As shown, there are 5 ports, which correspond to: the inter-chip port of the FPGA on-chip routing module and the input end of the multiple-choice selector. This design allows data packets to flow freely between different FPGA chips. The second cross switch control unit is responsible for parsing the routing information of the data packet, and controls the path selection of the second cross switch based on this information to achieve fast transmission of the data packet from the source chip to the target chip, that is, under the deterministic routing strategy, the control unit needs to determine the transmission path of the data packet based on the controller ID, the accelerated computing unit group ID and the accelerated computing unit ID, and ensure that other paths can be intelligently selected when encountering link congestion. Specifically, when the data packet enters the second cross switch from the inter-chip port of the on-chip routing module, the control unit checks the ID information of the controller corresponding to the target node, as well as the current network status. If the link load in the direction corresponding to the target controller is low, the control unit will guide the data packet to be transmitted through the output port in that direction.

[0081] By including the inter-chip routing module of the second cross switch and the second cross switch control unit, the present invention ensures that the path selection for cross-chip data transmission is both fast and efficient, and significantly reduces the delay of data packets when transmitting between chips. When encountering link failure or congestion, the second cross switch control unit can intelligently select an alternative path, improve the overall robustness and reliability of the network, ensure that data transmission can still be carried out even under unfavorable network conditions, and realize efficient data transmission and adaptive routing selection across chips, which not only optimizes the communication between chips and improves the data transmission speed, but also enhances the network robustness and reliability of the accelerated computing system when processing tasks such as database accelerated computing and large-scale data processing.

[0082] In an embodiment of the present invention, Figure 5 As shown, the intra-chip routing module or the inter-chip routing module includes a virtual channel control unit, which is used to divide a physical channel into multiple virtual channels to prevent the channel closed loop from causing deadlock.

[0083] In the accelerated computing system of the related art, the complexity and high concurrency of data communication will lead to network congestion and deadlock, especially in the interconnection structure based on bus and ring network. The present invention uses virtual channel technology to divide the physical channel into multiple logically independent virtual channels to avoid deadlock and improve network efficiency.

[0084] In a specific embodiment, Figure 5 As shown in the figure, both the intra-chip routing module and the inter-chip routing module integrate a virtual channel control unit, which divides each physical channel into four independent virtual channels (VC), namely VC0, VC1, VC2 and VC3. In this way, different virtual channels can be used when data packets are transmitted in different directions, thereby avoiding the channel closed loop problem common in ring networks and effectively preventing the occurrence of deadlock. Specifically, the virtual channel control unit is located at the front end of each input and output port to manage the channel allocation of incoming and outgoing data packets. By dividing the physical channel into four independent virtual channels, when a data packet enters from a certain direction, the control unit selects a virtual channel for transmission according to predefined rules or the current network status, ensuring that the data packet will not generate a closed loop in the channel under any circumstances, avoiding deadlock.

[0085] The virtual channel control unit can improve the transmission efficiency of the on-chip network by preventing deadlock and realizing adaptive load balancing, ensuring that the data packet can reach the destination in the shortest time. The deadlock avoidance mechanism ensures the continuity of data transmission and the stability of system operation, especially in high concurrency or network congestion environments, and can effectively prevent the degradation of system performance. In summary, the present invention introduces a virtual channel control unit in the intra-chip routing module and the inter-chip routing module. The present invention realizes the efficiency, stability and resource optimization of data transmission in the accelerated computing system, provides powerful hardware support for high-demand tasks such as database accelerated computing and large-scale data processing, and ensures the high performance and reliability of the system when processing complex interconnected communications.

[0086] In an embodiment of the present invention, the virtual channel control unit is specifically used to: construct multiple independent micro-chip buffers in the output queue buffer corresponding to the physical channel to obtain multiple virtual channels; divide the virtual channels into a first channel group and a second channel group in a clockwise direction; when the routing coordinates of the source node are greater than the routing coordinates of the target node, use the first channel group; when the routing coordinates of the source node are less than or equal to the routing coordinates of the target node, use the second channel group.

[0087] The virtual channel control unit converts a single physical channel into multiple logically independent virtual channels by creating multiple independent micro-slice buffers in the output queue buffer of the physical channel to improve the communication efficiency and stability of the network.

[0088] In a specific embodiment, the virtual channel control unit creates four independent micro-slice buffers, namely VC0, VC1, VC2 and VC3, in the output queue buffer of each physical channel, which together constitute four virtual channels. Each micro-slice buffer is responsible for processing data packets in a specific direction to ensure that the transmission of data packets does not form a closed loop and avoid the occurrence of deadlock. Specifically, when a data packet needs to be transmitted from one computing unit group to another, it will be assigned by the virtual channel control unit to a specific virtual channel for transmission instead of through a single physical channel. The virtual channel is divided into a first channel group (including VC0 and VC1) and a second channel group (including VC2 and VC3) in a clockwise direction. This division method is associated with the transmission direction of the data packet, making the data transmission in a specific direction more orderly and efficient. For example, in the on-chip routing module, data packets transmitted in the clockwise direction will use the first channel group (VC0 and VC1), while data packets transmitted in the counterclockwise direction will use the second channel group (VC2 and VC3). In the actual transmission process, the first channel accelerated computing unit group or the second channel accelerated computing unit group is selected according to the routing coordinates of the source node and the target node (controller ID, accelerated computing unit group ID, accelerated computing unit ID). When the routing coordinates of the source node are greater than the routing coordinates of the target node, the first channel accelerated computing unit group is used for transmission; when the routing coordinates of the source node are less than or equal to the routing coordinates of the target node, the second channel accelerated computing unit group is used. Specifically, in the controller cluster architecture, if a data packet is transmitted from the node of accelerated computing unit group 0 (for example, controller ID=0, accelerated computing unit group ID=0, accelerated computing unit ID=0) to the node of accelerated computing unit group 3 (controller ID=0, accelerated computing unit group ID=3, accelerated computing unit ID=0), since the accelerated computing unit group ID of the source node is less than the accelerated computing unit group ID of the target node, the second channel accelerated computing unit group (VC2 and VC3) should be used for transmission at this time. On the contrary, if the data packet is transmitted from the node of accelerated computing unit group 3 to the node of accelerated computing unit group 0, since the accelerated computing unit group ID of the source node is greater than the accelerated computing unit group ID of the target node, the first channel accelerated computing unit group (VC0 and VC1) will be used for transmission.

[0089] By dividing the physical channel into multiple virtual channels and selecting the appropriate channel group for data transmission based on the direction and routing coordinates, the present invention effectively avoids the common deadlock problem in the ring network and ensures the transmission continuity of the data packet and the stability of the system. The division of the channel group and the channel selection strategy based on the routing coordinates simplify the routing algorithm of the on-chip communication network, making the system design simpler, while reducing the delay during data transmission, improving the data transmission speed and the overall performance of the system.

[0090] In an embodiment of the present invention, when the accelerated computing unit group is in the first operating mode, the accelerated computing units in the group are allowed to be configured to have different computing functions.

[0091] The first working mode allows the accelerated computing units in the same group to be configured to perform different computing functions, which means that different types of accelerated computing units can be flexibly allocated and combined according to specific application requirements to achieve the best performance optimization. This is crucial for system flexibility and task execution efficiency. Specifically, each accelerated computing unit can be dynamically configured to perform different computing tasks, such as data decompression, full table scans, expression filtering, sorting, hashing, etc. This configuration method provides great flexibility, allowing the system to select the most suitable accelerated computing unit for acceleration according to the characteristics of different tasks.

[0092] The above-mentioned first working mode allows the accelerated computing units to work together to complete a series of complex database accelerated computing tasks without requiring each accelerated computing unit to have all the functions, which greatly improves the resource utilization efficiency of the system. In addition, since the accelerated computing units in the accelerated computing unit group share memory, in the first working mode, although the computing units in the group can be configured to perform different functions, the computing units with different functions directly access the shared memory in the group when performing tasks, reducing the delay and energy consumption of data transmission. For example, when the expression filtering computing unit completes its task, it can write the result directly to the shared memory in the group without transmitting data through the on-chip network. In this way, the sorting computing units in the same group can immediately access these results for the next step of calculation, reducing the overhead of data transmission and improving the work efficiency of the entire system. In addition, the design of shared group memory reduces unnecessary data transmission, can also reduce energy consumption during data transmission, and also reduces communication delays between computing units, providing strong technical support for building low-power, high-performance computing systems.

[0093] In an embodiment of the present invention, when the accelerated computing unit group is in the second working mode, the accelerated computing units in the group are configured to have the same computing function so that if any accelerated computing unit in the group fails, other accelerated computing units in the group can be used to replace it.

[0094] In large-scale parallel computing scenarios, hardware failures are inevitable. In order to improve the stability and fault tolerance of the system, the present invention proposes a second working mode in addition to the first working mode. The second working mode is designed to run when all accelerated computing units in the group are configured to perform the same computing function. In this way, even if a computing unit fails, the system can still replace the function through other computing units in the group, ensuring the continuity of the task and the stability of the system performance.

[0095] In a specific embodiment, in the second working mode, all computing units in the same accelerated computing unit group will be configured to perform the same computing function. For example, all computing units in a group can be set to perform tasks such as data decompression or full table scanning to ensure that when any computing unit fails, other computing units can immediately take over its work without reconfiguration or scheduling. Specifically, assuming that (0,0,0), (0,0,1), (0,0,2) and (0,0,3) in group 0 are configured as the second working mode and set to perform the same function, such as data decompression, then when any computing unit (such as (0,0,1)) has a hardware failure, other computing units (such as (0,0,0), (0,0,2) and (0,0,3)) can immediately take over the task and continue to perform the data decompression task using the shared memory resources in the group to ensure uninterrupted execution of the task.

[0096] In the second working mode, since all computing units in the group are configured to perform the same function, they can share data and resources in the group more effectively, reducing the steps of retransmitting data during the fault replacement process, and further improving computing efficiency and resource utilization efficiency. The instant task reallocation and data sharing mechanism provided by the shared memory can ensure that the real-time execution of tasks and the overall stability of the system are not affected when hardware fails, which is particularly important for tasks such as database acceleration calculation and large-scale data processing with high real-time requirements.

[0097] In an embodiment of the present invention, the controller is one of FPGA, ARM and AVR.

[0098] FPGA, ARM microprocessor and AVR microprocessor have their own characteristics and are suitable for different scenarios and needs. When FPGA plays the role of controller, it can provide highly customized control logic, which is suitable for system design that requires high flexibility and programmability. As a controller, ARM microprocessor can provide powerful processing power and rich peripheral interfaces, which is suitable for tasks that require high-performance computing and complex system management. AVR microprocessor is an ideal choice in some cost-sensitive and power-constrained application scenarios, and the low cost and low power consumption characteristics of AVR microprocessor make it possible to deploy sensor networks on a large scale while ensuring the stability and efficiency of the system.

[0099] According to the design requirements and application scenarios of the accelerated computing system, selecting FPGA, ARM microprocessor or AVR microprocessor as the controller can achieve functional optimization and performance improvement at different levels, providing a variety of hardware platform options for building efficient, stable and economical electronic devices and accelerated computing systems.

[0100] In an embodiment of the present invention, an accelerated computing system is provided, such as Figure 6 As shown, the accelerated computing system includes: a host, multiple controller clusters and a switching chip (which can be a CXL Switch). The host is responsible for task scheduling and data management, the controller cluster is responsible for executing accelerated computing tasks, and the switching chip is responsible for efficient data exchange between the host and the controller cluster.

[0101] In a specific embodiment, assuming that the host has a large-scale data processing task, such as database acceleration calculation, it will decompose the task into multiple subtasks and distribute them to different controller clusters according to the computing requirements of the subtasks. The controller in each controller cluster will efficiently execute the corresponding subtasks according to its configured computing function, such as a controller in a cluster may be configured to specifically perform data decompression, while a controller in another cluster may be responsible for full table scanning. The switching chip, as a data bridge between the host and the controller cluster, is responsible for achieving efficient bus connection and data exchange. It can handle a large amount of data streams, ensure fast data transmission speed and low latency between the host and the controller cluster, and improve the overall performance of the system. For example, the host is connected to the switching chip through a high-speed bus such as PCIe or CXL, and then the switching chip is connected to each controller cluster through the CXL bus. When the host needs to send data to a controller cluster for calculation, the data will first be sent to the switching chip through the bus on the host side. The switching chip repackages the data according to the destination controller cluster and group information and sends it to the corresponding controller cluster. Inside the controller cluster, the data will be transmitted to the target accelerated computing unit through the on-chip network or packet bus to perform the corresponding computing task. The above-mentioned switching chip is a heterogeneous cache consistency switching chip, which solves the problem of insufficient cache consistency support in on-chip interconnection in related technologies.

[0102] Through the accelerated computing system architecture, the present invention can allocate computing resources according to task requirements, realize data processing acceleration, and improve the overall system performance and data processing speed. The design of the controller cluster allows the system to be dynamically adjusted and expanded according to application requirements, increasing the system flexibility and scalability, so that the system can adapt to various computing tasks and data volumes. Through the configuration of multiple controller clusters and the internal interconnection improvement structure, even if the controller or accelerated computing unit fails, the system can still continue to complete the task through other available resources, improving the reliability and fault tolerance of the system.

[0103] In an embodiment of the present invention, Figure 7 As shown, the controllers in the controller cluster are configured as a fully connected structure.

[0104] The fully connected structure means that all controllers in the controller cluster are directly connected to each other, that is, each controller can communicate directly with other controllers without complex routing strategies. Figure 7 As shown in the figure, each controller includes 16 nodes, and the controllers are fully connected through routing. This structure improves the efficiency of data transmission, reduces communication delay, and enhances the coordination ability between system resources.

[0105] In a specific embodiment, within a controller cluster, a fully connected structure can be implemented through a CXL interface. Through the CXL interface, each controller can directly access the main memory and memory resources of other controller clusters, thereby reducing data transmission delays and improving bandwidth. In addition, the system-wide unified addressing feature of the CXL protocol enables the accelerated computing units of different controller clusters to access remote memory like accessing local memory, thereby realizing data flow within the fully connected structure.

[0106] The controller cluster under the fully connected structure can realize data sharing with dynamic task allocation, which is particularly important in tasks such as database acceleration computing. The host side can allocate data and tasks to any controller as needed, and these controllers only need a single hop to access other controllers without additional routing control. In summary, the controller cluster under the fully connected structure can significantly improve the efficiency of data transmission and reduce communication delays. The fully connected structure simplifies the complexity of task scheduling and data management, allowing the host to allocate tasks more flexibly. At the same time, the accelerated computing unit can directly access the required data, improving the utilization of computing resources and the parallelism of task execution. Efficient and convenient mutual access also improves the collaborative ability of the system where the controller cluster is located, providing key technical support for building a low-latency, high-bandwidth high-performance computing system.

[0107] In the embodiment of the present invention, the switch chip at least supports the CXL communication protocol.

[0108] The CXL communication protocol is a high-speed, low-latency interconnect technology standard designed to meet the needs of modern data centers and high-performance computing systems for high-speed data transmission and cache consistency support. The CXL protocol supports three main modes: CXL.io, CXL.cache, and CXL.memory, which are used for input and output communication, cache consistency communication, and shared memory access between devices, respectively. In the present invention, the switching chip is designed to support the CXL communication protocol, thereby enabling efficient data transmission and cache consistency management within the controller cluster architecture. This means that data can flow efficiently between components in the system without increasing latency and reducing bandwidth. Figure 6As shown in the figure, the host communicates with the switch chip through the CXL bus, and the switch chip is connected to the CXL device-side controller in each FPGA cluster through the CXL bus. This design allows the host to directly access the DDR / HBM memory in the controller cluster without going through complex routing and conversion processes, thereby greatly improving data access speed and overall system performance. CXL communication between controller clusters can omit additional conversion or intermediate nodes. For example, in Figure 6 In the schematic diagram of the interconnection of the FPGA routing modules shown, it can be seen that different FPGAs are fully connected through the switching chips supported by the CXL protocol, which means that data transmission between any two FPGA clusters can be completed directly through the CXL bus without complex routing judgment and data packet redirection. The switching chips supporting the CXL protocol can achieve cache consistency between different FPGA clusters, ensure data consistency and integrity, and avoid data conflicts and inconsistency problems.

[0109] In summary, switch chips that support the CXL communication protocol can provide high-speed, low-latency data transmission capabilities, which is essential for high-performance computing and data acceleration tasks in the controller cluster architecture. With the support of the CXL protocol, switch chips can achieve inter-chip cache consistency, ensure the integrity and consistency of data in the multi-controller cluster architecture, and improve the reliability of the system. The switch chip under the CXL protocol simplifies the communication architecture in the system, reduces the intermediate links in data transmission, makes the data flow more direct and efficient, reduces system latency, and improves the overall processing speed.

[0110] In an embodiment of the present invention, Figure 4 As shown, the controller cluster also includes a multiple-to-one selector for receiving signals generated inside the controller and transmitting them to other controllers or a host.

[0111] A multi-selector is a circuit component that can select one signal from multiple input signals for transmission. In a controller with a multi-controller architecture, a multi-selector is used to select the correct output path in inter-chip communication to send a data packet or signal to a specific target chip.

[0112] In a specific embodiment, Figure 4 As shown, the multi-choice selector is connected to the inter-chip routing module and then to multiple controllers. Each controller has a corresponding input terminal. By decoding the controller ID, the multi-choice selector can select the correct output path and send the data packet or signal to the specified target controller. Figure 6As shown in Figure 1, assume that there is a cluster of 4 FPGAs, each of which has a port connected to a multi-select selector. When a data packet needs to be transmitted from the current controller to other controllers, the on-chip routing module sends the data packet to the inter-chip fully connected port, which transmits the data packet to the multi-select selector. After the selector receives the signal from the inter-chip fully connected port, it decodes it according to the target controller ID in the data packet and transmits the signal to the output port that matches the target controller ID.

[0113] The introduction of a multi-choice selector provides direct and efficient path selection and data transmission capabilities, greatly simplifies the data transmission process between different controllers, reduces the delay in path selection of data packets during routing jumps, and avoids unnecessary detours of data packets in the Internet of multiple controllers, thereby significantly improving the overall data transmission efficiency and speed of the accelerated computing system.

[0114] In an embodiment of the present invention, a method for routing jumps within a controller is proposed, which can be run as follows: Figure 6 On the accelerated computing system shown. Figure 8 FIG. 1 is a flow chart of the routing jump method within the controller. Figure 8 As shown, the above process includes:

[0115] Step S201, configuring the routing coordinates of the accelerated computing unit inside the controller, the routing coordinates including the controller ID, the accelerated computing unit group ID and the accelerated computing unit ID;

[0116] In some embodiments of the present invention, each accelerated computing unit is assigned a corresponding routing coordinate, which includes three dimensions, namely the controller ID, the accelerated computing unit group ID and the accelerated computing unit ID. For example, the accelerated computing unit (0, 0, 0) represents the first accelerated computing unit of the first group located on controller 0. This coordinate configuration makes the position and connection relationship of each computing unit in the system clear and identifiable, providing a basis for subsequent routing jumps.

[0117] Step S202, determining the routing coordinates of the source node and the routing coordinates of the target node based on the routing jump request, and calculating the number of intra-chip jump steps according to the routing coordinates of the source node and the routing coordinates of the target node;

[0118] Specifically, when an accelerated computing unit needs to transfer data to another accelerated computing unit, the accelerated computing system first determines the routing coordinates of the source node and the target node, and then calculates the number of on-chip jump steps based on the routing coordinates of the two. The formula is as follows:

[0119] The number of intra-chip jump steps = ((accelerated computing unit group ID of the destination node * number of accelerated computing units in the group + accelerated computing unit ID of the destination node) - (accelerated computing unit group ID of the source node * number of accelerated computing units in the group + accelerated computing unit ID of the source node) + number of accelerated computing nodes) mod number of accelerated computing nodes.

[0120] Step S203, determining the route jump direction based on the number of jump steps within the chip, and performing route jump based on the route jump direction.

[0121] Based on the calculated number of on-chip jump steps, the accelerated computing system determines the routing jump direction according to the shortest path principle, and then controls the transmission of data packets according to the routing jump direction to complete the routing jump process.

[0122] In a specific embodiment, the source node coordinates are set to (0, 0, 0) and the target node coordinates are set to (0, 3, 0). In a 16-node FPGA cluster, the number of on-chip jump steps is calculated to be 12. According to the routing strategy, the system determines that the number of steps falls within the interval (3 / 4, 1), so it chooses to jump in the clockwise direction. This means that the data packet will go through the path of (0, 0, 0) → (0, 1, 0) → (0, 2, 0) → (0, 3, 0) and directly reach the target node without passing through unnecessary intermediate nodes, thus reducing delay.

[0123] Through the above steps, the jump step number calculation based on the routing coordinates and the routing jump direction determination, the present invention can optimize the transmission path of the data packet inside the FPGA, ensuring that the data packet reaches the target node with the shortest path and the lowest delay, thereby significantly improving the data transmission efficiency. The deterministic routing strategy and shortest path selection reduce the delay in the data transmission process, while reducing unnecessary data rerouting, thereby reducing power consumption and improving the overall performance and energy efficiency of the system. The routing jump method based on the coordinate system enables the system to flexibly adapt to FPGA cluster architectures of different sizes, and when expanding the system, it is easy to maintain and adjust the routing strategy, ensuring that the newly added computing unit can be smoothly integrated into the existing network, and improving the flexibility and scalability of the system.

[0124] The execution subject of the above steps may be a host, a controller, etc., but is not limited thereto.

[0125] In order to avoid insufficient bandwidth and data congestion and reduce the computing efficiency of the accelerated computing system, in an embodiment of the present invention, based on the route jump direction, route jump is performed, including:

[0126] Step S2031, obtaining the output buffer length of the controller port;

[0127] Step S2032: When the output buffer length is greater than the fifth threshold, reverse routing is performed.

[0128] The communication between accelerated computing units needs to be carried out through a complex routing network. However, the congestion level of the routing network is closely related to communication delay and data packet loss. In order to avoid performance degradation caused by network congestion, the present invention proposes the routing strategy of the above-mentioned technical buffer length, and performs reverse routing when the buffer length is long.

[0129] In a specific embodiment, Figure 4 As shown, the first crossbar switch control unit needs to monitor the load conditions of all inputs [0-4] and outputs [0-4]. When a data packet enters from input [0] (clockwise), the control unit will check the load in the output direction. If the buffer of output [1] is full (i.e., greater than the fifth threshold as mentioned above), the control unit will guide the data packet to be reversely routed through output [2] (opposite direction) or output [3] (clockwise) to avoid congestion during transmission.

[0130] Through the above steps, the present invention monitors the output buffer length of the port, and adopts a reverse routing strategy when the port buffer is full, effectively balancing the communication load in the network, avoiding local network congestion, and ensuring smooth and efficient data transmission in the accelerated computing system. Therefore, the reverse routing strategy avoids data transmission through high-load ports, thereby reducing communication delays and maintaining high performance and response speed of the system. In addition, dynamic routing adjustment reduces the queuing time of data packets on congested links, reduces the risk of data packet loss, and improves the reliability of communication.

[0131] In an embodiment of the present invention, determining a routing jump direction based on the number of jump steps within a chip includes:

[0132] Step S2033, based on the preset range of the number of intra-chip jump steps, determine the route jump direction, the route jump direction includes clockwise direction, counterclockwise direction, opposite direction or a combination of clockwise direction, counterclockwise direction and opposite direction.

[0133] In order to meet the shortest path principle, the present invention provides a method for determining the route jump direction based on the number of intra-chip jump steps. Specifically, by analyzing the preset range of the number of intra-chip jump steps, the most appropriate route jump direction is intelligently selected, thereby reducing communication delay and improving data transmission efficiency.

[0134] Based on the pre-configured routing strategy of the present invention, the accelerated computing system can intelligently select the shortest path for data packets in the internal network of the controller, significantly reducing communication delay and improving data transmission efficiency. The strategy of pre-setting the jump step range and route jump direction enables the system to be flexibly adjusted under different communication requirements and network conditions, improving the stability and reliability of communication.

[0135] The execution order of step S2033, step S2031 and step S2032 is interchangeable, that is, step S2033 may be executed first, and then step S2031 and step S2032, or step S2033, step S2031 and step S2032 may be executed simultaneously.

[0136] In an embodiment of the present invention, determining a routing jump direction based on a preset range of the number of jump steps within a chip includes:

[0137] Step S20331, when the number of jump steps within the chip is equal to a first threshold, determining the clockwise direction as the routing jump direction;

[0138] Step S20332: when the number of jump steps within the slice is equal to a second threshold, determining the opposite side direction as the routing jump direction;

[0139] Step S20333: when the number of intra-chip jump steps is equal to a third threshold, determining the counterclockwise direction as the routing jump direction;

[0140] Step S20334: when the number of jump steps within the chip is less than the first threshold, determine the counterclockwise direction as the routing jump direction;

[0141] Step S20335: when the number of jump steps within the slice is greater than the first threshold and less than the second threshold, first the opposite direction and then the clockwise direction are determined as the routing jump directions;

[0142] Step S20336, when the number of jump steps within the slice is greater than the second threshold and less than the third threshold, first determining the lateral direction and then the counterclockwise direction as the routing jump direction;

[0143] Step S20337: when the number of intra-chip jump steps is greater than the third threshold and less than the fourth threshold, the clockwise direction is determined as the routing jump direction.

[0144] Based on Figure 1The controller architecture shown takes a 16-node controller as an example. The first threshold of the present invention is set to 4 (i.e., 1 / 4 of the number of computing nodes), the second threshold is set to 8 (i.e., 1 / 2 of the number of computing nodes), the third threshold is set to 12 (i.e., 3 / 4 of the number of computing nodes), and the fourth threshold is set to 16 (i.e., the number of computing nodes). When the number of jump steps within the chip is equal to the first threshold (4), the system determines the clockwise direction as the routing jump direction; when the number of jump steps within the chip is equal to the second threshold (8), the system determines the opposite direction as the routing jump direction; when the number of jump steps within the chip is equal to the third threshold (12), the system determines the counterclockwise direction as the routing jump direction; when the number of jump steps within the chip is less than the first threshold (i.e., 0 to 3), the system determines the counterclockwise direction as the routing jump direction; when the number of jump steps within the chip is greater than the first threshold (i.e., 4 to 7) and less than the second threshold (i.e., 8), the system first determines the opposite direction and then the clockwise direction as the routing jump direction; when the number of jump steps within the chip is greater than the second threshold (i.e., 8 to 11) and less than the third threshold (i.e., 12), the system first determines the opposite direction and then the counterclockwise direction as the routing jump direction; when the number of jump steps within the chip is greater than the third threshold (i.e., 12 to 15) and less than the fourth threshold (i.e., 16), the system determines the clockwise direction as the routing jump direction. Specifically, assuming that a data packet needs to be transmitted from (0, 0, 0) of group 0 to (0, 3, 0) of group 3, in a 16-node controller, the number of intra-chip jump steps is calculated to be 12. According to the strategy of the present invention, the direction is determined to be counterclockwise, that is, the data packet will be transmitted in the counterclockwise direction from (0, 0, 0) through the path of (0, 3, 3) → (0, 2, 3) → (0, 1, 3) → (0, 3, 0), ensuring efficient data scheduling.

[0145] Through the routing jump direction strategy based on the number of jump steps in the chip and the preset threshold range, the present invention can ensure that the data packet is transmitted along the shortest path in the internal network of the controller, significantly reducing the communication delay and improving the data transmission efficiency. The strategy of the preset threshold range and the routing jump direction can dynamically adapt to different communication needs, realize intelligent and efficient data scheduling, and improve the overall performance and reliability of the system. In summary, the above steps design the bus connection inside the accelerated computing unit group and the communication connection between the groups to achieve low-latency and high-bandwidth data transmission. At the same time, by setting the first to fourth thresholds, according to the range of the number of jump steps in the chip, the routing jump in the clockwise, counterclockwise or opposite direction, as well as the combination of the above directions, is intelligently determined, thereby optimizing the transmission path of the data packet in the internal network of the controller. Through this flexible routing strategy, the system can effectively cope with network congestion, ensure fast and reliable transmission of data, and thus improve the overall computing performance and efficiency of the system.

[0146] In an embodiment of the present invention, a method for routing jumps between controllers is proposed. The method can be run as follows: Figure 6On the accelerated computing system shown. Fig. 9 FIG. 1 is a flow chart of the routing jump method between the above controllers. Fig. 9 As shown, the above process includes:

[0147] Step S301, configuring the routing coordinates of the accelerated computing unit in the controller, the routing coordinates including the controller ID, the accelerated computing unit group ID and the accelerated computing unit ID;

[0148] Step S302, determining the routing coordinates of the source node and the routing coordinates of the target node based on the routing jump request;

[0149] Step S303, based on the routing coordinates of the source node, jump from the intra-chip routing module corresponding to the source node to the inter-chip routing module corresponding to the source node, jump from the inter-chip routing module corresponding to the source node to the inter-chip routing module corresponding to the target node according to the routing coordinates corresponding to the target node, and jump from the inter-chip routing module corresponding to the target node to the intra-chip routing module corresponding to the target node according to the routing coordinates corresponding to the target node, and transmit to the target node.

[0150] When data needs to be transmitted between the accelerated computing units of different controllers, the on-chip routing jump is not enough to complete the data transmission. At this time, the system will use the inter-chip routing module to perform cross-controller routing jumps. For example, if the source node coordinates are (0, 0, 0) and the target node coordinates are (1, 0, 0), the data packet will jump from the on-chip routing module of the source node to the inter-chip routing module of controller 0, then jump to the inter-chip routing module of controller 1, and finally reach the on-chip routing module of the target node, and then be transmitted to the above target node.

[0151] In the above steps, by configuring the routing coordinates of the accelerated computing unit, the system can accurately calculate the number of jump steps within the chip, provide clear path guidance for data transmission, and reduce routing errors and communication delays. The combined use of the intra-chip routing module and the inter-chip routing module enables the present invention to support communication within the same controller and communication across controllers, meeting the requirements for efficient data exchange between heterogeneous accelerated computing units under the controller cluster architecture.

[0152] In an embodiment of the present invention, a method for scheduling an accelerated computing unit for an accelerated computing task is proposed. The method can be run as follows: Figure 6 On the accelerated computing system shown. Fig.10 FIG. 1 is a flow chart of the routing jump method between the above controllers. Fig.10 As shown, the above process includes:

[0153] Step S401, obtaining an accelerated computing unit state table and a memory access delay table, wherein the computing unit state table is used to include at least the routing coordinates, unit functions, unit states, and storage occupancy of the accelerated computing unit, and the memory access delay table includes the delay of each accelerated computing unit accessing each shared cache;

[0154] The accelerated computing unit status table records the detailed information of the existing accelerated computing units (as shown in Table 1), including but not limited to routing coordinates, unit functions, unit status (such as idle or occupied), and storage occupancy (i.e., whether the current unit is using its shared cache space). The memory access latency table records the latency information when each accelerated computing unit accesses different shared caches, which is used to analyze data transmission efficiency and optimize scheduling strategies (as shown in Table 2).

[0155] Table 1

[0156]

[0157] Table 2

[0158]

[0159] Step S402, obtain the computing tasks to be assigned, and determine the scheduling strategy according to the computing unit status table and the memory access delay table. In the process of determining the scheduling strategy, the accelerated computing units with different storage occupancy can run in parallel, and each accelerated computing unit in the scheduling strategy corresponds to the computing tasks to be assigned with the smallest delay.

[0160] The system obtains the accelerated computing tasks to be executed, which may include database acceleration operations such as data decompression, full table scan, expression filtering, and sorting. For example, in an accelerated computing system, the order of computing tasks to be assigned is data decompression, full table scan, expression filtering, and sorting. The accelerated computing system will intelligently assign tasks to the most appropriate accelerated computing unit based on the status of the accelerated computing unit and the requirements of the accelerated computing tasks to be assigned, combined with the information in the memory access delay table. This process takes into account the following factors:

[0161] Unit function matching: The system will assign tasks to accelerated computing units that match their functions. Unit status: The system gives priority to idle accelerated computing units to avoid overlapping execution of tasks. Storage occupancy: The system considers the storage occupancy of different computing units to achieve efficient execution of parallel tasks. Memory access latency: Based on the memory access latency table, the system will select the computing unit and memory pair with the smallest latency to reduce data transmission time.

[0162] In a specific embodiment, assuming that the system needs to perform a data decompression task, first, according to the computing unit status table, the system finds that the computing unit with coordinates (0, 1, 2) is in an idle state and has a decompression function. Next, the system checks the memory access delay table and determines that the delay of the computing unit accessing the memory of group 1 is the shortest. Therefore, the system selects the accelerated computing unit with coordinates (0, 1, 2) to perform the data decompression task. After the unit completes the task and stores the calculation results in the memory, the system continues to check the status table and delay table, and selects the accelerated computing unit with the smallest delay and matching function for the subsequent full table scan task, and repeats this cycle until all tasks are completed.

[0163] Through the accelerated computing unit status table, the accelerated computing system can accurately identify the function and status of each unit, thereby assigning tasks to the most suitable computing unit, improving the efficiency of task execution. The memory access delay table provides the system with delay information, allowing the system to intelligently select the path with the least delay for data transmission, reducing communication delays and increasing data transmission speeds. In addition, during the task scheduling process, the accelerated computing system takes into account the possibility of parallel operation of accelerated computing units with different storage occupancy, and through reasonable task allocation, realizes the parallel and efficient execution of multiple tasks, further improving the overall computing performance of the system.

[0164] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0165] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0166] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0167] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A controller for accelerating computing, characterized in that: include: A plurality of accelerated computing unit groups, wherein adjacent accelerated computing unit groups are connected to each other in communication with each other, and are arranged in a completely symmetrical ring. Accelerated computing units in the same accelerated computing unit group are connected in sequence through an internal bus, and accelerated computing units in different accelerated computing unit groups that are located at symmetrical positions of the same ring diameter are connected to each other in communication with each other; Each accelerated computing unit group further includes a shared memory, and the shared memory is connected to each of the accelerated computing units via the internal bus.

2. The controller according to claim 1, characterized in that: The controller further includes: A device-side controller, configured to receive a data packet in a CXL format, parse the data packet to obtain an accelerated computing task, and send the task to the accelerated computing unit; The switching module is connected to the device-side controller via a CXL bus, and communicates with the accelerated computing unit via an internal bus, and is used to receive the accelerated computing task by direct memory access and send it to the accelerated computing unit.

3. The controller according to claim 2, characterized in that: The switching module includes a multi-stage switching module, including the switching module connected to the device-side controller through the CXL bus and connected to other switching modules through multiple interfaces with output signals in the main mode, and the switching module connected to other switching modules, connected to the shared memory through an interface with output signals in the slave mode, and connected to the accelerated computing unit through an interface with output signals in the main mode.

4. The controller according to claim 1, characterized in that: The controller further comprises: An on-chip routing module, respectively connected to the accelerated computing unit groups for implementing routing jumps within the same controller; The inter-chip routing module is communicatively connected with the intra-chip routing module and is used to implement routing jumps between different controllers.

5. The controller according to claim 4, characterized in that: The on-chip routing module includes a first cross switch and a first cross switch control unit, wherein the first cross switch is used to connect each of the accelerated computing unit groups and the inter-chip routing module, and the first cross switch control unit is used to control the on-off of the path connected by the first cross switch.

6. The controller according to claim 4, characterized in that: The inter-chip routing module includes a second cross switch and a second cross switch control unit, wherein the second cross switch is used to connect the intra-chip routing module with other controllers, and the second cross switch control unit is used to control the on-off of the path connected by the second cross switch.

7. The controller according to claim 4, characterized in that: The intra-chip routing module or the inter-chip routing module includes a virtual channel control unit, which is used to divide a physical channel into multiple virtual channels to prevent deadlock caused by channel closed loop.

8. The controller according to claim 7, characterized in that: The virtual channel control unit is specifically used for: Constructing a plurality of mutually independent micro-slice buffers in the output queue buffer corresponding to the physical channel to obtain a plurality of the virtual channels; Divide the virtual channels into a first channel group and a second channel group in a clockwise direction; In the case where the routing coordinates of the source node are greater than the routing coordinates of the target node, using the first channel group; In a case where the routing coordinates of the source node are less than or equal to the routing coordinates of the target node, the second channel group is used.

9. The controller according to claim 1, characterized in that: When the accelerated computing unit group is in the first operating mode, the accelerated computing units in the group are allowed to be configured to perform different computing functions.

10. The controller according to claim 1, characterized in that: When the accelerated computing unit group is in the second working mode, the accelerated computing units in the group are configured to perform the same computing function so that if any accelerated computing unit in the group fails, other accelerated computing units in the group can be used to replace it.

11. The controller according to claim 1, characterized in that: The controller is one of FPGA, ARM and AVR.

12. An accelerated computing system, characterized in that: The accelerated computing system comprises: Host; A plurality of controller clusters, for executing the accelerated computing tasks issued by the host, each of the controller clusters comprising a plurality of controllers as described in any one of claims 1 to 11; The switching chip is connected to the host and the controller cluster via a bus, and is used to implement data interaction between the host and the controller cluster.

13. The accelerated computing system according to claim 12, wherein: The controllers in the controller cluster are configured as a fully connected structure.

14. The accelerated computing system according to claim 12, wherein: The switching chip at least supports the CXL communication protocol.

15. The accelerated computing system according to claim 12, wherein: The controller cluster further includes a multiple-to-one selector for receiving a signal generated inside the controller and transmitting the signal to other controllers or the host.

16. A routing jump method inside a controller, characterized in that: include: Configure the routing coordinates of the accelerated computing unit in the controller, wherein the routing coordinates include the controller ID, the accelerated computing unit group ID, and the accelerated computing unit ID; Determine the routing coordinates of the source node and the routing coordinates of the target node based on the routing jump request, and calculate the number of intra-chip jump steps according to the routing coordinates of the source node and the routing coordinates of the target node; A route jump direction is determined based on the number of intra-chip jump steps, and a route jump is performed based on the route jump direction.

17. The method according to claim 16, characterized in that Based on the route jump direction, route jump is performed, including: Obtaining the output buffer length of the controller port; When the output buffer length is greater than a fifth threshold, reverse routing is performed.

18. The method according to claim 16, characterized in that Determining a routing jump direction based on the number of jump steps within the chip includes: The routing jump direction is determined based on a preset range of the number of jump steps within the chip, and the routing jump direction includes a clockwise direction, a counterclockwise direction, an opposite direction, or a combination of the clockwise direction, the counterclockwise direction, and the opposite direction.

19. The method according to claim 18, characterized in that The controller includes a plurality of accelerated computing unit groups, wherein the accelerated computing units in the same accelerated computing unit group are sequentially connected through an internal bus and connected to the same shared memory through the internal bus, the accelerated computing units in another adjacent group of the accelerated computing units between different accelerated computing unit groups are communicated and connected to each other, and the accelerated computing units in another opposite group are communicated, and the routing jump direction is determined based on a preset range of the number of jump steps within the chip, and the method includes: When the number of jump steps within the chip is equal to the first threshold, determining the clockwise direction as the routing jump direction; When the number of jump steps within the slice is equal to the second threshold, determining the opposite direction as the routing jump direction; When the number of jump steps within the chip is equal to a third threshold, determining a counterclockwise direction as the routing jump direction; When the number of jump steps within the chip is less than the first threshold, determining the counterclockwise direction as the routing jump direction; When the number of jump steps within the chip is greater than the first threshold and less than the second threshold, firstly determining the opposite direction and then the clockwise direction as the routing jump direction; When the number of jump steps within the chip is greater than the second threshold and less than the third threshold, firstly facing the direction and then the counterclockwise direction are determined as the routing jump direction; When the number of intra-chip jump steps is greater than the third threshold and less than the fourth threshold, the clockwise direction is determined as the routing jump direction.

20. A method for routing jumps between controllers, characterized in that: The controller includes an on-chip routing module and an inter-chip routing module, wherein the on-chip routing module is respectively connected to each accelerated computing unit group in communication, and the inter-chip routing module is connected to the on-chip routing module in communication. The method includes: Configure the routing coordinates of the accelerated computing unit in the controller, wherein the routing coordinates include the controller ID, the accelerated computing unit group ID, and the accelerated computing unit ID; Determining the routing coordinates of the source node and the routing coordinates of the target node based on the routing jump request; Based on the routing coordinates of the source node, the intra-chip routing module corresponding to the source node is jumped to the inter-chip routing module corresponding to the source node; according to the routing coordinates corresponding to the target node, the inter-chip routing module corresponding to the source node is jumped to the inter-chip routing module corresponding to the target node; and according to the routing coordinates corresponding to the target node, the inter-chip routing module corresponding to the target node is jumped to the intra-chip routing module corresponding to the target node, and transmitted to the target node.

21. A method for scheduling accelerated computing units for accelerated computing tasks, characterized in that: The accelerated computing unit scheduling method is applied to the accelerated computing system according to claim 12, and the method comprises: Obtain an accelerated computing unit state table and a memory access delay table, wherein the computing unit state table is used to include at least the routing coordinates, unit functions, unit states, and storage occupancy of the accelerated computing unit, and the memory access delay table includes the delay of each of the accelerated computing units accessing each shared cache; Obtain the computing task to be assigned, and determine the scheduling strategy according to the computing unit status table and the memory access delay table, wherein, in the process of determining the scheduling strategy, the accelerated computing units with different storage occupancy can run in parallel, and each of the accelerated computing units in the scheduling strategy corresponds to the computing task to be assigned with the smallest delay.

Images