Physical verification system and method of integrated circuit
By defining simplified rule verification syntax and using user-defined variables, physical verification of integrated circuits is solved, and a more efficient and easy-to-use physical verification method is achieved.
Patent Information
- Application Number
- CN202411593642.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-28
AI Technical Summary
When SVRF is used in the prior art to write physical verification scripts on increasingly large integrated circuits, the code is becoming increasingly complex, resulting in extended verification cycles and increased development costs, and complexity affects the learning curve of new engineers and the productivity of teams.
A physical verification system and method of integrated circuit is proposed. By defining rule verification syntax, including input statements, command statements and output statements, user-defined variables and assignment symbols are used to declare and generate layers of integrated circuits, simplifying the writing and parsing of physical verification scripts.
It realizes a more concise and easy-to-use rule verification format language, shortens the length of physical verification scripts, improves processing speed and storage efficiency, reduces error rate and learning curve, and improves design efficiency and accuracy.
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Figure CN119538859A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic design automation, and in particular to a simpler integrated circuit physical verification system and method. Background Art
[0002] At present, in the process of integrated circuit design, physical verification is a key step to ensure that the integrated circuit design meets the manufacturing specifications. Tools such as Calibre use SVRF (Standard Verification Rule Format) as their rule definition language. However, with the increasing complexity of integrated circuit design, the writing and maintenance of SVRF rules have become increasingly cumbersome, resulting in longer verification cycles and higher development costs.
[0003] In addition, the complexity of SVRF also affects the learning curve of new engineers and limits the productivity of the team. Therefore, it is particularly important to develop a more concise, easy-to-use and efficient rule verification format language.
[0004] Therefore, providing a simpler and easier-to-operate physical verification method for integrated circuits is a technical problem to be solved. Summary of the invention
[0005] In order to solve the technical problem of increasingly complex codes when using SVRF to write physical verification scripts for integrated circuits of increasingly larger scales in the prior art, the present invention proposes a physical verification system and method for integrated circuits.
[0006] The physical verification method of the integrated circuit proposed by the present invention comprises:
[0007] Define the rule verification syntax, which includes: define input statements, command statements and output statements; when defining command statements, if the command statements are used to operate the layers, the input layers, options and values or switches of the options are marked with marking symbols;
[0008] For the integrated circuit to be verified, the physical verification script of the integrated circuit to be verified is edited using the rule verification syntax;
[0009] The physical verification script is physically verified based on the rule verification grammar, and a parsing result is output.
[0010] Furthermore, when defining command statements, user-defined variables and assignment symbols are used to declare and generate operations on the layers of the integrated circuit.
[0011] Furthermore, the assignment symbol is: =, == or: ≈.
[0012] Furthermore, when declaring and generating the layers of the integrated circuit, the layers are represented in the form of MN or MN, where M is the value of the layer map and N is the value of the Datatype.
[0013] Furthermore, when multiple layer variables to be assigned are annotated using annotation symbols, the analysis is performed by assigning values to multiple elements of a data set respectively.
[0014] Furthermore, the marking symbol is [], {} or ().
[0015] Furthermore, the layer marked by the second symbol is one or more layers corresponding to the operation.
[0016] Furthermore, when multiple annotation symbols are nested and there is no direct assignment object for the operation result of the operation command corresponding to the internal annotation symbol, a corresponding number of temporary layers are used to receive the result during compilation.
[0017] Further, physically verifying the physical verification script based on the rule verification grammar, and outputting the parsing result includes:
[0018] Performing lexical analysis and grammatical analysis based on the rule verification grammar;
[0019] Build an abstract syntax tree;
[0020] Convert an abstract syntax tree into an understandable format.
[0021] The physical verification system of the integrated circuit proposed by the present invention adopts the physical verification method of the integrated circuit of the above technical solution to perform physical verification on the layout file to be verified. The physical verification system of the integrated circuit comprises:
[0022] Verification language module, receiving user-defined rule verification grammar files;
[0023] The script module receives the physical verification script file corresponding to the layout file to be verified input by the user;
[0024] A compiling module performs physical verification on the physical verification script file based on the rule verification grammar file and outputs a parsing result.
[0025] Compared with existing technologies, RVRF has significant advantages while achieving the same functions. First, RVRF's recipes are shorter and more concise, which not only saves storage space but also improves processing speed. Second, RVRF's command syntax is more standardized and intuitive, making it easier for engineers to learn, master and maintain. Finally, RVRF supports the function of simultaneous output of multiple computing layers, making it more efficient and convenient in scenarios where multiple results need to be processed. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The present invention is described in detail below with reference to the embodiments and accompanying drawings, wherein:
[0027] Figure 1 It is a schematic diagram of components and keywords of the RVRF syntax according to an embodiment of the present invention.
[0028] Figure 2 It is a script schematic diagram of an embodiment of the present invention.
[0029] Figure 3 It is a flow chart of the use of the verification system of the present invention.
[0030] Figure 4 It is a schematic diagram of a comparative embodiment of the present invention and the prior art. DETAILED DESCRIPTION
[0031] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0032] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.
[0033] like Figure 1 As shown, the physical verification method of integrated circuit proposed by the present invention includes the following steps.
[0034] Define the rule verification syntax, which includes: define input statements, command statements and output statements; when defining command statements, if the command statements are used to operate the layers, the input layers, options and values or switches of the options are marked with marking symbols;
[0035] For the integrated circuit to be verified, a physical verification script of the integrated circuit to be verified is edited using a defined rule verification syntax;
[0036] Physical verification is performed on the physical verification script based on the rule verification syntax, and the parsing results are output.
[0037] The focus of the present invention is on the corresponding rule verification syntax. The rule verification syntax format can be called RVRF (Reduced Verification Rule Format), which is a new type of rule verification format for efficiently and flexibly defining and executing physical verification rules for integrated circuit design. It aims to simplify the physical verification rule definition process in integrated circuit design, improve design efficiency and accuracy, and reduce error rates while maintaining compatibility with existing verification tools.
[0038] The RVRF of the present invention has a wide range of application scenarios, and can demonstrate its unique value whether it is fine-tuning a single design rule or deploying a rule set for a large-scale design project. Design engineers can use RVRF to define a set of rules to check whether the minimum spacing between metal layers in an integrated circuit meets the requirements of a specific process. When faced with complex design requirements, such as connectivity verification of multi-layer wiring, the flexibility of RVRF allows designers to combine rules in a modular way to easily meet various verification challenges. This not only saves time in rule writing, but also significantly reduces the error rate, ensuring the accuracy and reliability of design verification.
[0039] like Figure 1 As shown, the rule definition process of RVRF includes the following basic types: input statements, command statements and output statements.
[0040] Input statements are used to input and define the basic information of the layout and related parameter settings. For example, INPUT defines the path and name of the input layout; INPUT FORMAT specifies the format of the input layout; PRECISION specifies the processing accuracy when performing calculation tasks, etc.
[0041] Command statements are used to declare, generate, and calculate layer units, as well as configure complex functions. Layer command operations are the core of RVRF. Command statements are mainly divided into two categories: shape-based and edge-based.
[0042] Output statements are used to output layers and calculation results. For example, OUTPUT defines the path and name of the output layout; OUTPUT FORMAT specifies the format of the output layout, etc.
[0043] The present invention uses user-defined variables and assignment symbols to declare and generate operations on the layers of the integrated circuit when defining command statements. In one embodiment, the assignment symbol can be:=, == or:≈, etc.
[0044] For example, when the SVRF syntax is used in the prior art to declare and generate the layers of the integrated circuit, there is a lack of assignment symbols, such as LAYER MAP 1DTATYPE1 10001, which means that the layer LAYER MAP 1DTATYPE1 is defined as 10001. If it needs to be represented by letters, it needs to be further defined, such as LAYER M1 10001, which means that the layer 10001 is defined as M1, and then M1 can be used to refer to the layer LAYER MAP 1DTATYPE1. It can be seen that the syntax specified by SVRF is difficult to understand and complicated. The present invention uses assignment symbols to define, which can become M1:=LAYER MAP1DTATYPE1.
[0045] In a further embodiment, when the present invention declares and generates the layers of the integrated circuit, the layers are represented in the form of MN or MN, where M is the value of the layer map and N is the value of the Datatype.
[0046] That is to say, in order to further simplify the code, the present invention further simplifies M1:=LAYER MAP 1DTATYPE1 to M1:=LAYER DBi 1.1, where DBi refers to a specific integrated circuit layout defined by the user, but the present invention is not limited to using DB (Data Base) to refer to the integrated circuit layout, and those skilled in the art may also use other variable names. The value of i can be any natural number, so that when the user defines the rule, the code is more simplified and easier to understand.
[0047] When defining command statements in the present invention, if the command statement is used to operate a layer, the input layer, option, and value or option switch are marked with a marking symbol. Those skilled in the art can use a simple moving marking symbol to mark it so as to distinguish it from the operation command symbol.
[0048] In one embodiment, when multiple layer variables to be assigned are annotated with annotation symbols, the analysis is performed by assigning values to multiple elements of a data set separately. For example, [M1 M2]:=..., represents assigning the operation results to layers M1 and M2 respectively.
[0049] In one embodiment, the marking symbol may be [], {} or (). For example, M4:=EDGE_EXPAND[M1]IN[0.8]EXTEND[0.5]. This means that layer M4 is first shortened by 0.8 units inward (in the vertical direction) and then extended inward (in the left direction) by 0.5 units. By using marking symbols, the user's variables and values can be distinguished from the operation symbols, making it easier to read.
[0050] In one embodiment, the layer marked by the second symbol is one or more layers corresponding to the operation. For example, a command statement is to select the part of the two input layers L1 and L2 that have an intersection and output it to L3, which can be written as L3:=AND[L1L2]. The code is not only concise but also very easy to understand.
[0051] In one embodiment, physical verification is performed on the physical verification script based on the rule verification grammar, and the output parsing result includes:
[0052] Lexical and syntax analysis based on rule-based validation grammar;
[0053] Construct an abstract syntax tree; (How to construct an abstract syntax tree based on the structure of syntax analysis and lexical analysis? Is it different from the existing technology? If so, please introduce the construction process in detail)
[0054] Convert the abstract syntax tree into an easy-to-understand format. (What is the final output? What is the easy-to-understand format defined in this patent? Please introduce it.)
[0055] In the grammar of the RVRF of the present invention, ":=" can be used as a symbol for defining and assigning values to declare and generate operations on layers. All keywords and commands must be capitalized, and user-defined names should avoid conflicts with keywords, otherwise double quotes should be used to enclose the customized names to distinguish them; in a command for operating a layer, the input layer, option-related value or option switch can be marked with "[]"; the operands in the recipe (script) are sensitive to the context, and operating on non-existent or undefined operands will interrupt execution and prompt an error, but they are not sensitive to spaces, and multiple spaces have the same meaning as a single space, that is, when compiling, if multiple spaces are encountered in lexical analysis or syntax analysis, they are parsed and processed as a single space; in addition, multiple commands can be nested in loops to achieve continuous writing of commands, thereby further streamlining and shortening the syntax.
[0056] Figure 2 It is a complete recipe instance (script instance). RVRF uses recipe as a function implementation carrier. Recipe instances follow the RVRF syntax and are named with the suffix ".rx".
[0057] Lines 1-2 are input layout files. Multiple input layouts can be specified in the same recipe.
[0058] Lines 3-4 specify the format of the input layout file, including but not limited to common file formats in the electronic design automation field such as OASIS and GDSII.
[0059] Lines 5-6 input the basic cells to be processed in the layout file. When this statement is omitted, the top-level cells are processed by default.
[0060] Line 8 defines the processing precision when performing calculation tasks, ensuring that the values used in the physical verification process have sufficient precision, thereby avoiding verification errors or inaccurate results caused by insufficient precision. By setting the precision appropriately, performance can be optimized while ensuring verification accuracy.
[0061] Lines 9-10 limit the specific layers on which the validation rules take effect, which helps avoid validation on unnecessary layers, thereby improving the speed and efficiency of validation.
[0062] Line 12, the command statement, selects the intersection of the two input layers L1 and L2 and outputs them to layer L3.
[0063] Line 13, the command statement, selects the part of the union of the input layers of L1 (one or two) and outputs it to layer L4.
[0064] Line 14, the command statement, in layer L1, selects all parts that do not overlap with layer L2 and outputs them to layer L5.
[0065] Line 15, the command statement, selects different parts of the L1 and L2 input layers and outputs the areas that meet the conditions to layer L6.
[0066] Line 16, the command statement, enlarges or reduces the L1 input layer according to the specified value (0.02).
[0067] Line 17, the command statement, performs smoothing on the L1 input layer according to the input value (0.02). The size of the value affects the degree of processing, and the area that meets the conditions is output to layer L9.
[0068] Line 18, the command statement, selects the L2 graphics that overlap with part or all of the L3 input layer, or that are outside the L3 input layer and have overlapping edges with the L3 input layer, and outputs the areas that meet the conditions to layer L10.
[0069] Line 19, the command statement, selects the polygons in the L2 input layer that meet the perimeter constraint and outputs the area that meets the condition to layer L12.
[0070] Line 20, the command statement, selects all L1 input layer graphics outside the L2 input layer and outputs the areas that meet the conditions to L14.
[0071] Line 21, the command statement, has a measurement function, checks the edges of the L1 input layer from inside to inside, and outputs the area that meets the conditions to L16.
[0072] Line 22, command statement, shows the command writing function of RVRF, which is achieved by nesting multiple command loops. Taking this command statement as an example, the intersection of L1 and L2 input layers is first output to a temporary layer (received by an implicit temporary layer TEMP, TEMP:=AND[L1 L2]); then the union of the temporary layer and the L3 command layer is output to L22 (L22:=OR[TMP L3]). The loop nesting function is achieved by surrounding a command statement with parentheses and replacing the input layer in other command statements.
[0073] Line 23, command statement. Similarly, this statement also shows the command chaining function. First, select all L3 input layer graphics outside the L4 input layer, and output the areas that meet the conditions to the temporary layer TEMP (TEMP:=OUTSIDE[L3L4]); then output the polygons that meet the perimeter conditions in the temporary layer as L23 (L23:=PERIMETER[TEMP]>3<4).
[0074] Lines 25-26, output layout files. Multiple output layouts can be specified in the same recipe.
[0075] Lines 27-28 specify the format of the output layout file, which has the same common electronic design automation file format as the command specifying the input layout format.
[0076] Lines 29-30 output the basic cell specified in the layout file. When this statement is not used, it defaults to the top cell of the input layout.
[0077] Lines 32-33 specify the output layer in the output result and support outputting multiple calculation layers in the same result.
[0078] The present invention also protects a physical verification system of an integrated circuit, which uses the physical verification method of an integrated circuit of the above technical solution to perform physical verification on a layout file to be verified, and the physical verification system of the integrated circuit includes:
[0079] Verification language module, receiving user-defined rule verification grammar files;
[0080] The script module receives the physical verification script file corresponding to the layout file to be verified input by the user;
[0081] A compiling module performs physical verification on the physical verification script file based on the rule verification grammar file and outputs a parsing result.
[0082] Figure 3The flowchart of the physical verification system for integrated circuits of the present invention is as follows. The flowchart discloses the parsing process of RVRF in electronic design automation, which mainly includes the following steps:
[0083] Step 1, input verification language. Users submit RVRF rule language files through the command line interface or other interfaces. These files contain specific format languages used to verify electronic design rules, aiming to ensure that electronic designs meet predetermined standards and specifications.
[0084] Step 2, receiving input data. The system receives and loads the RVRF rule language file content submitted by the user into memory, ready to start the parsing process. This is the first step in the parsing process, ensuring that all necessary input data is ready.
[0085] Step 3: Lexical analysis. Use the lexical analyzer to scan the input data, identify and extract basic vocabulary units, such as keywords, identifiers, operators, etc. If unrecognizable characters or patterns are encountered during the lexical analysis process, the system will report an error message and stop the parsing process.
[0086] Step 4: Syntax analysis. The grammar analyzer is used to further analyze the vocabulary units according to the predefined grammar rules. The grammar analyzer checks whether these vocabulary units can form a legal RVRF sentence. If the grammar analysis fails, the system will also report an error message and interrupt the parsing process.
[0087] Step 5: Build an abstract syntax tree. When the syntax analysis is successfully completed, the system will build an abstract syntax tree based on the parsing results. An abstract syntax tree is a tree structure that represents the syntax structure of the source code in a way that is easier to understand and process. This stage is crucial for the subsequent parsing result processing because it provides a clear input format for the subsequent processing logic.
[0088] Step 6: Output the parsing results. Finally, the system converts the parsed abstract syntax tree into an easy-to-understand output format, such as text, graphical interface, etc., so that users can intuitively view the parsing results. In addition, the output results can also be used for further rule verification or integrated with electronic design automation software to complete complex design tasks.
[0089] Figure 4 This is a schematic diagram comparing the syntax of RVRF and SVRF, showing the parts of the two languages intercepted from a complete recipe. The two languages express the same meaning and achieve the same function, which facilitates syntax comparison.
[0090] Lines 1 to 6 define the path and format of the input layout file. It can be seen that SVRF only describes the path, while this application not only describes the path, but also defines variables for the input layout file, which are defined as DB1 to DB3. Based on this definition, the subsequent description can be made more concise, and since SVRF only specifies the path, it is necessary to describe the specific layers of the specific layout file in detail later.
[0091] In lines 3 and 6, RVRF inputs the third layout file, using "DB3" as an alias, and specifies the type of the input layout file as OASIS for easy reference later. In contrast, SVRF's syntax rules limit it to supporting only two layout files in the same example. RVRF supports the input of more layout files, which can better meet the needs of processing multiple layout files in the same project.
[0092] Comparing lines 8-13, the statements of SVRF and RVRF both indicate that the validation rules are limited to specific layers, and they specify the layer data type pairs 1.1, 2.2, and 3.3 of the layout respectively, and use aliases M1, M2, and M3 to replace these three pairs of layer data type pairs. In this group of statements, RVRF shows a shorter statement feature than RVRF.
[0093] From line 8 to line 13, it can be seen that since SVRF did not define the layout file before, it needs to specify the specific layer in detail, such as LAYER MAP 1DATATYPE 1 10001, and then define layer 10001 as layer M1, and the code is very cumbersome. However, since DB1 and the like are defined at the beginning, the present invention can simply assign values and define the variable layer M1 as layer 1.1 of the layout file DB1, that is, LAYER MAP 1DATATYPE 1.
[0094] Compared with line 15, SVRF and RVRF both perform the same operation, that is, to expand the edge of M1 in the normal direction to obtain a new graph. INSIDE BY / IN[0.8] means that the graph is expanded inward, and 0.8 indicates the distance of expansion; EXTEND BY / EXTEND[0.5] means that the edges of M1 are adjusted before expansion. In this command, it can be clearly seen that the command syntax of RVRF is more intuitive. RVRF uses square brackets "[]" in the command to enclose the layer name and the parameters related to the command. This syntax structure not only enhances the readability of the command, but also reduces the parsing problems caused by syntax errors. The lack of this rule in SVRF makes its commands more obscure in complex situations.
[0095] Comparing lines 16-19, SVRF and RVRF express the same meaning and function, that is, by specifying rules, M1 in the layout is split and output to the corresponding output layer. RVRF supports multi-output functions and can output the calculation layer results of MASK0, MASK1 and MASK2 in the same command at the same time. Among them, M1 is the input layer of the command, MASK0, MASK1 and MASK2 are output layers, and OUTPUT_TYPE[COLOR1 COLOR2COLOR3] in RVRF is an option for all graphics that represent the output split to three different output layers, which is the same as the default selection of SVRF, and M4 (opposite 0) / DIFF0[M4] expresses the same function, that is, a strict splitting instruction based on the M4 layer. In other words, the present invention uses [] to define a data set, which can be used to receive the results of the operation command. This multi-output function not only simplifies the writing of commands, but also improves work efficiency and avoids repeating the same command. In contrast, SVRF needs to write two commands separately to achieve the same effect, which increases the redundancy and maintenance difficulty of the code.
[0096] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A physical verification method for an integrated circuit, characterized in that: include: Define the rule verification syntax, which includes: define input statements, command statements and output statements; when defining command statements, if the command statements are used to operate the layers, the input layers, options and values or switches of the options are marked with marking symbols; For the integrated circuit to be verified, the physical verification script of the integrated circuit to be verified is edited using the rule verification syntax; The physical verification script is physically verified based on the rule verification grammar, and a parsing result is output.
2. The physical verification method of an integrated circuit as claimed in claim 1, characterized in that: When defining command statements, user-defined variables and assignment symbols are used to declare and generate operations on the layers of the integrated circuit.
3. The physical verification method of an integrated circuit as claimed in claim 2, characterized in that: The assignment symbol is: =, == or: ≈.
4. The physical verification method of an integrated circuit as claimed in claim 2, characterized in that: When declaring and generating layers of an integrated circuit, the layers are represented in the form of MN or MN, where M is the value of the layer map and N is the value of the Datatype.
5. The physical verification method of an integrated circuit as claimed in claim 1, characterized in that: When multiple layer variables to be assigned are annotated using annotation symbols, the analysis is performed by assigning values to multiple elements of a data set separately.
6. The physical verification method of an integrated circuit as claimed in claim 1 or 5, characterized in that: The marking symbols are [], {} or ().
7. The physical verification method of an integrated circuit as claimed in claim 5, characterized in that: The layer marked by the second symbol is one or more layers corresponding to the operation.
8. The physical verification method of an integrated circuit as claimed in claim 5, characterized in that: When multiple annotation symbols are nested and there is no direct assignment object for the operation result of the operation command corresponding to the internal annotation symbol, a corresponding number of temporary layers are used to receive the result during compilation.
9. The physical verification method of an integrated circuit as claimed in claim 1, characterized in that: Performing physical verification on the physical verification script based on the rule verification grammar and outputting the parsing result includes: Performing lexical analysis and grammatical analysis based on the rule verification grammar; Build an abstract syntax tree; Convert an abstract syntax tree into an understandable format.
10. A physical verification system for an integrated circuit, characterized in that: A physical verification method for an integrated circuit according to any one of claims 1 to 9 is used to physically verify a layout file to be verified, wherein the physical verification system for the integrated circuit comprises: Verification language module, receiving user-defined rule verification grammar files; The script module receives the physical verification script file corresponding to the layout file to be verified input by the user; A compiling module performs physical verification on the physical verification script file based on the rule verification grammar file and outputs a parsing result.