Gate drive circuit and display device

Abstract

The invention provides a gate driving circuit and a display device, the gate driving circuit comprises multiple levels of gate driving units, and each level of gate driving unit comprises a pre-charging module, a pull-down module, a stabilizing module and an output module; the output module and the pre-charging module are connected to a first node; the output module comprises a first switch element, a pre-output unit and a first pull-down stabilizing unit; a first control end of the first switch element is connected with a first node, a first access end is connected with a third node, and a second access end is connected with an output end; the pre-output unit charges a third node according to a pre-stage grid output signal and a current-stage first clock signal; the first pull-down stabilization unit is used for pulling down the third node to a low level according to the second clock signal of the level in the stabilization stage, and the high level time period of the second clock signal of the level is not overlapped with the high level time period of the first clock signal of the level. The circuit noise can be effectively reduced, the high temperature resistance is improved, and the display device can be used in more use scenes.

Description

Technical Field

[0001] The present invention relates to the field of display driving technology, and in particular to a gate driving circuit and a display device. Background Art

[0002] Display devices, such as liquid crystal displays (LCDs), have gradually replaced traditional cathode ray tube displays due to their many advantages such as being light, thin, energy-efficient, and radiation-free. They are widely used in electronic devices such as high-definition digital televisions, desktop computers, personal digital assistants, laptops, mobile phones, digital cameras, and so on.

[0003] The display device can be provided with a gate driving circuit to provide a gate output signal for the gate line. The high and low level changes of the gate output signal can be used to activate or close the thin film transistor connected to the gate line, thereby controlling the switching of the pixel to realize the display of the image. Figure 1 As shown, each level of the gate drive unit of the gate drive circuit of the prior art includes a pre-charging module, a pull-down module, a stabilization module and an output module. A switch element T is provided in the output module, and the control end of the switch element T is connected to the node. One channel end of the switch element receives the clock signal CLK, and the other channel end of the switch element is connected to the output terminal V to connect the corresponding gate line, which is used to output the gate clock signal of this level according to the high level on the node and the high level of the clock signal CLK in the output stage. However, in the stable stage, the clock signal CLK will maintain the periodic switching of high and low levels, resulting in periodic noise generated at both the node and the output terminal V through the switch element. The circuit noise reduces the high temperature resistance of the circuit and may even make the display device unable to cope with high temperature and other usage scenarios. Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0004] In view of this, the present invention provides a gate driving circuit and a display device, which can effectively reduce circuit noise, improve high temperature resistance, and enable the display device to be used in more usage scenarios.

[0005] An embodiment of the present invention provides a gate driving circuit, which includes a multi-stage gate driving unit, each stage of the gate driving unit includes a pre-charging module, a pull-down module, a stabilization module and an output module; the output module is connected to the pre-charging module at a first node, and the output module includes a first switch element, a pre-output unit and a first pull-down stabilization unit; the first switch element includes a first control end, a first path end and a second path end, the first control end of the first switch element is connected to the first node, the first path end of the first switch element is connected to a third node, the second path end of the first switch element is connected to an output end, and is used to output a gate output signal of this stage; the pre-output unit is connected to the third node, and charges the third node according to the previous gate output signal and the first clock signal of this stage; the first pull-down stabilization unit is connected to the third node, and is used to pull the third node down to a low level according to the second clock signal of this stage in a stable stage, and the high level time period of the second clock signal of this stage does not overlap with the high level time period of the first clock signal of this stage.

[0006] Specifically, the pre-output unit includes a second switch element and a third switch element, the second switch element includes a second control end, a third path end and a fourth path end, the second control end of the second switch element is connected to the fourth node, the third path end of the second switch element receives the first clock signal of the current stage, and the fourth path end of the second switch element is connected to the third node; the third switch element includes a third control end, a fifth path end and a sixth path end, the third control end of the third switch element receives the previous gate output signal, the fifth path end of the third switch element receives the first high level signal, and the sixth path end of the third switch element is connected to the fourth node.

[0007] Specifically, the first pull-down stabilization unit includes a fourth switch element and a fifth switch element; the fourth switch element includes a fourth control end, a seventh path end and an eighth path end, the fourth control end of the fourth switch element receives the second clock signal of the current stage, the seventh path end of the fourth switch element is connected to the third node, and the eighth path end of the fourth switch element receives a low-level signal; the fifth switch element includes a fifth control end, a ninth path end and a tenth path end, the fifth control end of the fifth switch element receives the second clock signal of the current stage, the ninth path end of the fifth switch element is connected to the fourth node, and the tenth path end of the fifth switch element receives a low-level signal.

[0008] Specifically, the output module further includes a first capacitor, a first end of the first capacitor is connected to the fourth node, and a second end of the first capacitor is connected to the third node.

[0009] Specifically, the pre-charging module includes a sixth switch element, the sixth switch element includes a sixth control terminal, an eleventh path terminal and a twelfth path terminal, the sixth control terminal of the sixth switch element receives the previous gate output signal, the eleventh path terminal of the sixth switch element receives the third clock signal of the current stage, and the twelfth path terminal of the sixth switch element is connected to the first node; And / or, the pull-down module includes a seventh switch element, the seventh switch element includes a seventh control terminal, a thirteenth channel terminal and a fourteenth channel terminal, the seventh control terminal of the seventh switch element receives the subsequent gate output signal, the thirteenth channel terminal of the seventh switch element is connected to the first node, and the fourteenth channel terminal of the seventh switch element receives the fourth clock signal of the current stage; And / or, the stabilization module includes an eighth switch element, a ninth switch element, a tenth switch element, an eleventh switch element and a twelfth switch element; the eighth switch element includes an eighth control terminal, a fifteenth channel terminal and a sixteenth channel terminal, the eighth control terminal of the eighth switch element receives the second clock signal of the current stage, the fifteenth channel terminal of the eighth switch element is connected to the output terminal, and the sixteenth channel terminal of the eighth switch element receives a low-level signal; the ninth switch element includes a ninth control terminal, a seventeenth channel terminal and an eighteenth channel terminal, the ninth control terminal of the ninth switch element is connected to the second node, the seventeenth channel terminal of the ninth switch element is connected to the first node, and the eighteenth channel terminal of the ninth switch element receives the low-level signal; the tenth switch element includes a tenth control terminal, a nineteenth channel terminal and a twentieth channel terminal, the tenth control terminal of the tenth switch element The end is connected to the first node, the nineteenth path end of the tenth switch element is connected to the second node, and the twentieth path end of the tenth switch element receives the low level signal; the eleventh switch element includes an eleventh control end, a twenty-first path end and a twenty-second path end, the eleventh control end of the eleventh switch element is connected to the second node, the twenty-first path end of the eleventh switch element is connected to the output end, and the twenty-second path end of the eleventh switch element receives the low level signal; the twelfth switch element includes a twelfth control end, a twenty-third path end and a twenty-fourth path end, the twelfth control end of the twelfth switch element receives the second high level signal, the twenty-third path end of the twelfth switch element is connected to the twelfth control end of the twelfth switch element, and the twenty-fourth path end of the twelfth switch element is connected to the second node.

[0010] Specifically, the duty cycle of the third clock signal of this level, the first clock signal of this level, the fourth clock signal of this level and the second clock signal of this level are all 50%, the clock periods are all equal, and are sequentially spaced by a quarter of the clock period.

[0011] Specifically, the first high level signal received by the fifth path end of the third switch element is replaced by the second clock signal of this stage.

[0012] Specifically, the output module further includes a second pull-down stabilizing unit, which is connected to the output end and pulls the output end down to a low level according to a subsequent gate output signal.

[0013] Specifically, the second pull-down stabilization unit includes a thirteenth switch element; the thirteenth switch element includes a thirteenth control terminal, a twenty-fifth channel terminal and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switch element receives the rear-stage gate output signal, the twenty-fifth channel terminal of the thirteenth switch element is connected to the output terminal, and the twenty-sixth channel terminal of the thirteenth switch element receives a low-level signal.

[0014] An embodiment of the present invention further provides a display device, comprising the above-mentioned gate driving circuit.

[0015] The gate drive circuit and display device provided by the present invention, the gate drive circuit includes a multi-stage gate drive unit, each stage of the gate drive unit includes a pre-charging module, a pull-down module, a stabilization module and an output module; the output module is connected to the pre-charging module at the first node, and the output module includes a first switch element, a pre-output unit and a first pull-down stabilization unit; the first control end of the first switch element is connected to the first node, the first path end is connected to the third node, and the second path end is connected to the output end; the pre-output unit charges the third node according to the previous stage gate output signal and the first clock signal of this stage; the first pull-down stabilization unit is used to pull the third node down to a low level according to the second clock signal of this stage in the stable stage, and the high level time period of the second clock signal of this stage does not overlap with the high level time period of the first clock signal of this stage. Thus, the gate drive circuit can be used to generate a gate drive signal, can effectively reduce circuit noise in the stable stage, improve high temperature resistance, and enable the display device to be used in more usage scenarios.

[0016] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a partial connection diagram of the gate drive circuit in the prior art.

[0018] Figure 2 4 is a circuit connection diagram of a gate driving circuit according to an embodiment of the present invention.

[0019] Figure 3 4 is a timing diagram of a group of clock signals received by a gate driving circuit according to an embodiment of the present invention.

[0020] Figure 4 is a circuit connection diagram of a gate driving circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to further explain the technical means and effects adopted by the present invention to achieve the intended purpose, the specific implementation methods, methods, steps, structures, features and effects of the gate drive circuit and display device proposed in the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments.

[0022] Figure 2 is a circuit connection diagram of a gate drive circuit according to an embodiment of the present invention. Figure 2 The gate driving circuit of this embodiment includes a multi-stage gate driving unit, and each stage of the gate driving unit includes: a pre-charging module 10, a pull-down module 20, a stabilizing module 30 and an output module 40. The output module 40 is connected to the pre-charging module 10 at the first node Q1, and the output module 40 includes a first switch element T1, a pre-output unit 41 and a first pull-down stabilizing unit 42. The first switch element T1 includes a first control terminal, a first path terminal and a second path terminal. The first control terminal of the first switch element T1 is connected to the first node Q1, the first path terminal of the first switch element T1 is connected to the third node Q3, and the second path terminal of the first switch element T1 is connected to the output terminal V and is used to output the gate output signal Gn of this stage. The pre-output unit 41 is connected to the third node Q3, and charges the third node Q3 according to the previous gate output signal Gn-4 and the first clock signal CLK3 of this stage. The first pull-down stabilizing unit 42 is connected to the third node Q3, and is used to pull the third node Q3 down to a low level according to the second clock signal CLK7 of this stage in the stabilizing stage. The high level time period of the second clock signal CLK7 of this stage does not overlap with the high level time period of the first clock signal CLK3 of this stage.

[0023] The pre-charging module 10 is connected to the first node Q1, and charges the first node Q1 according to the previous gate output signal Gn-4 and the third clock signal CLK1 of this stage. The pull-down module 20 is connected to the pre-charging module 10 at the first node Q1, and pulls the first node Q1 down to a low level according to the subsequent gate output signal Gn+4 and the fourth clock signal CLK5 of this stage. The stabilizing module 30 is connected to the first node Q1 and the output terminal V. The stabilizing module 30 is used to maintain the first node Q1 and the output terminal V at a low level when the first node Q1 is pulled down to a low level.

[0024] In the embodiment of the present invention, the gate driving units may be connected in sequence in a continuous manner or in a sequentially spaced manner. Figure 2The gate driving units in the example are connected in sequence at intervals. For example, the n-th gate driving unit is respectively connected to the n-4-th gate driving unit and the n+4-th gate driving unit. The current-stage gate output signal Gn output by the n-th gate driving unit can be represented by Gn, the previous-stage gate output signal Gn-4 received by the n-th gate driving unit can be represented by Gn-4, and the subsequent-stage gate output signal received by the n-th gate driving unit can be represented by Gn+4.

[0025] It is worth noting that if the n-th gate driving unit at the beginning of the circuit is not connected to the previous gate driving unit, then the external signal circuit needs to provide the previous gate output signal Gn-4, and the previous gate output signal Gn-4 is provided directly by the timing control circuit or through the source driving circuit to provide the corresponding start signal STV1. If the n-th gate driving unit at the end of the circuit is not connected to the subsequent gate driving unit, then the external signal circuit needs to provide the subsequent gate output signal Gn+4, and the subsequent gate output signal Gn+4 is provided directly by the timing control circuit or through the source driving circuit to provide the corresponding pull-down signal STV2.

[0026] In one embodiment of the present invention, Figure 2 As shown, the pre-output unit 41 includes a second switch element T2 and a third switch element T3, the second switch element T2 includes a second control terminal, a third path terminal and a fourth path terminal, the second control terminal of the second switch element T2 is connected to the fourth node Q4, the third path terminal of the second switch element T2 receives the first clock signal CLK3 of the current stage, and the fourth path terminal of the second switch element T2 is connected to the third node Q3; the third switch element T3 includes a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switch element T3 receives the previous gate output signal Gn-4, the fifth path terminal of the third switch element T3 receives the first high level signal DCH, and the sixth path terminal of the third switch element T3 is connected to the fourth node Q4. However, the present invention is not limited to this, for example, in another embodiment, only the second switch element T2 may be provided, the second control terminal of the second switch element T2 receives the previous gate output signal Gn-4, the third path terminal of the second switch element T2 receives the first clock signal CLK3 of the current stage, and the fourth path terminal of the second switch element T2 is connected to the third node Q3.

[0027] In one embodiment of the present invention, Figure 2As shown, the first pull-down stabilizing unit 42 includes a fourth switch element T4 and a fifth switch element T5; the fourth switch element T4 includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switch element T4 receives the second clock signal CLK7 of the current stage, the seventh path terminal of the fourth switch element T4 is connected to the third node Q3, and the eighth path terminal of the fourth switch element T4 receives the low level signal VGL; the fifth switch element T5 includes a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switch element T5 receives the second clock signal CLK7 of the current stage, the ninth path terminal of the fifth switch element T5 is connected to the fourth node Q4, and the tenth path terminal of the fifth switch element T5 receives the low level signal VGL. However, the present invention is not limited to this, for example, in another embodiment, only the fourth switch element T4 may be provided to pull down the third node Q3 to a low level according to the second clock signal CLK7 of the current stage.

[0028] In one embodiment of the present invention, Figure 2 As shown, the output module 40 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the fourth node Q4, and a second end of the first capacitor C1 is connected to the third node Q3. In one embodiment, the first capacitor C1 can be, but is not limited to, an external capacitor between the fourth node Q4 and the third node Q3, and the coupling effect of the capacitor can be used to improve the effect of pulling up the voltage of the fourth node Q4.

[0029] In one embodiment of the present invention, Figure 2 As shown, the output module 40 further includes a second capacitor C2, a first end of the second capacitor C2 is connected to the first node Q1, and a second end of the first capacitor C1 is connected to the output terminal V. In one embodiment, the second capacitor C2 may be, but is not limited to, an external capacitor between the first node Q1 and the output terminal V, and the coupling effect of the capacitor may be utilized to improve the effect of pulling up the voltage of the first node Q1.

[0030] In one embodiment of the present invention, Figure 2 As shown, the pre-charging module 10 includes a sixth switch element T6, which includes a sixth control terminal, an eleventh channel terminal and a twelfth channel terminal. The sixth control terminal of the sixth switch element T6 receives the previous gate output signal Gn-4, the eleventh channel terminal of the sixth switch element T6 receives the third clock signal CLK1 of this stage, and the twelfth channel terminal of the sixth switch element T6 is connected to the first node Q1.

[0031] In one embodiment of the present invention, Figure 2As shown, the pull-down module 20 includes a seventh switch element T7, which includes a seventh control terminal, a thirteenth channel terminal and a fourteenth channel terminal. The seventh control terminal of the seventh switch element T7 receives the subsequent gate output signal Gn+4, the thirteenth channel terminal of the seventh switch element T7 is connected to the first node Q1, and the fourteenth channel terminal of the seventh switch element T7 receives the fourth clock signal CLK5 of this stage.

[0032] In one embodiment of the present invention, Figure 2 As shown, the stabilization module 30 includes an eighth switch element T8, a ninth switch element T9, a tenth switch element T10, an eleventh switch element T11 and a twelfth switch element T12; the eighth switch element T8 includes an eighth control terminal, a fifteenth channel terminal and a sixteenth channel terminal, the eighth control terminal of the eighth switch element T8 receives the second clock signal CLK7 of the current stage, the fifteenth channel terminal of the eighth switch element T8 is connected to the output terminal V, and the sixteenth channel terminal of the eighth switch element T8 receives the low level signal VGL; the ninth switch element T9 includes a ninth control terminal, a seventeenth channel terminal and an eighteenth channel terminal, the ninth control terminal of the ninth switch element T9 is connected to the second node Q2, the seventeenth channel terminal of the ninth switch element T9 is connected to the first node Q1, and the eighteenth channel terminal of the ninth switch element T9 receives the low level signal VGL; the tenth switch element T10 includes a tenth control terminal, a nineteenth channel terminal and a twentieth channel terminal, the tenth switch element T10 The tenth control terminal is connected to the first node Q1, the nineteenth channel terminal of the tenth switch element T10 is connected to the second node Q2, and the twentieth channel terminal of the tenth switch element T10 receives the low level signal VGL; the eleventh switch element T11 includes an eleventh control terminal, a twenty-first channel terminal and a twenty-second channel terminal, the eleventh control terminal of the eleventh switch element T11 is connected to the second node Q2, the twenty-first channel terminal of the eleventh switch element T11 is connected to the output terminal V, and the twenty-second channel terminal of the eleventh switch element T11 receives the low level signal VGL; the twelfth switch element T12 includes a twelfth control terminal, a twenty-third channel terminal and a twenty-fourth channel terminal, the twelfth control terminal of the twelfth switch element T12 receives the second high level signal DC, the twenty-third channel terminal of the twelfth switch element T12 is connected to the twelfth control terminal of the twelfth switch element T12, and the twenty-fourth channel terminal of the twelfth switch element T12 is connected to the second node Q2.

[0033] In one embodiment of the present invention, the first switch element T1 to the twelfth switch element T12 may be, but not limited to, an N-type TFT, an NMOS tube or an N-type triode, etc. The corresponding first control terminal to the twelfth control terminal of the first switch element T1 to the twelfth switch element T12 are all gate electrodes. The corresponding channel terminals of the first switch element T1 to the twelfth switch element T12 are drain electrodes or source electrodes.

[0034] Figure 3 It is a timing diagram of a group of clock signals received by the gate driving circuit of an embodiment of the present invention. A group of clock signals received by the gate driving circuit is N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a cycle, N can be 8, etc., and the first clock signal CLK3 of this stage, the second clock signal CLK7 of this stage, the third clock signal CLK1 of this stage, and the fourth clock signal CLK5 of this stage received by any gate driving unit can be provided by this group of clock signals. Figure 3 In the example, the group of clock signals is eight phase difference clocks, namely CLK1~CLK8, and the phase difference between two adjacent phase difference clocks is one eighth of a cycle. The first clock signal CLK3, the second clock signal CLK7, the third clock signal CLK1 and the fourth clock signal CLK5 received by any gate driving unit can be provided by the group of clock signals; the phase difference between the first clock signal CLK3 of the current level received by any gate driving unit and the first clock signal CLK3 of the current level received by the adjacent gate driving unit is one eighth of a cycle. The phase difference between the second clock signal CLK7 of the same level received by any gate driving unit and the second clock signal CLK7 of the same level received by the adjacent gate driving unit is one eighth of a cycle, the phase difference between the third clock signal CLK1 of the same level received by any gate driving unit and the third clock signal CLK1 of the same level received by the adjacent gate driving unit is one eighth of a cycle, and the phase difference between the fourth clock signal CLK5 of the same level received by any gate driving unit and the fourth clock signal CLK5 of the same level received by the adjacent gate driving unit is one eighth of a cycle.

[0035] In one embodiment of the present invention, the duty cycle of the third clock signal CLK1 of this stage, the first clock signal CLK3 of this stage, the fourth clock signal CLK5 of this stage, and the second clock signal CLK7 of this stage are all 50%, the clock cycles are all equal, and are sequentially spaced by a quarter of the clock cycle. However, the present invention does not limit the duty cycle of each clock signal in this way, and the duty cycle can be, for example, 37.5% to 50%, etc., which all belong to the protection scope of the present invention.

[0036] Specifically, Figure 2 and Figure 3 For example, the working process of the gate driving unit of the gate driving circuit includes four stages, namely the pre-charging stage, the output stage, the pull-down stage and the stabilization stage: Pre-charge stage: The front-stage gate output signal Gn-4 changes from a low level to a high level, and the pre-charging module 10 controls the first node Q1 to receive the high-level front-stage gate output signal Gn-4, and the first node Q1 is charged.

[0037] In one embodiment, the previous gate output signal Gn-4 jumps from a low level to a high level, and the sixth switch element T6 receives the previous gate output signal Gn-4 at a high level through the sixth control terminal and becomes conductive, and the first node Q1 receives the third clock signal CLK1 of this stage through the conductive sixth switch element T6. When the third clock signal CLK1 of this stage jumps from a low level to a high level, the first node Q1 is charged. Thus, the pre-charging module 10 realizes charging of the first node Q1.

[0038] In one embodiment, when the front-stage gate output signal Gn-4 changes from a low level to a high level, the rear-stage gate output signal Gn+4 is at a low level, and the seventh switch element T7 receives the rear-stage gate output signal Gn+4 at a low level through the seventh control terminal and is in a disconnected state. Thus, the pull-down module 20 does not enter the working state.

[0039] In one embodiment, when the first node Q1 is charged and pulled up to a high level, the first switch element T1 receives a high level through the first control terminal connected to the first node Q1 and becomes conductive. At the same time, the previous gate output signal Gn-4 jumps from a low level to a high level, and the third switch element T3 receives the previous gate output signal Gn-4 at a high level through the third control terminal and becomes conductive; the fourth node Q4 receives the first high level signal DCH through the turned-on third switch element T3, and the fourth node Q4 is charged. When the fourth node Q4 is charged to a high level, the second switch receives a high level through the second control terminal connected to the fourth node Q4 and becomes conductive. Then, the third node Q3 receives the first clock signal CLK3 of the current stage at a low level through the turned-on second switch element T2, and the third node Q3 is not charged. Therefore, the output module 40 does not enter the working state, the third node Q3 is not charged, and the output terminal V does not output the current gate output signal Gn.

[0040] In one embodiment, when the first node Q1 is charged and pulled up to a high level, the tenth control terminal of the tenth switch element T10 connected to the first node Q1 becomes a high level, and the tenth switch element T10 becomes a conductive state, so that the second node Q2 connected to the nineteenth path terminal of the tenth switch element T10 receives the low level signal VGL through the conductive tenth switch element T10, and the second node Q2 is a low level. Then the ninth switch element T9 receives the low level through the ninth control terminal connected to the second node Q2 and becomes a disconnected state, and the tenth switch element T10 receives the low level through the tenth control terminal connected to the second node Q2 and becomes a disconnected state. Therefore, the stabilization module 30 does not pull down the first node Q1, but pulls down the second node Q2 to a low level.

[0041] Output stage: The first node Q1 has been pulled up to a high level, and the first clock signal CLK3 of this stage jumps from a low level to a high level. The output module 40 outputs a high level gate output signal Gn of this stage at the output terminal V according to the high level of the first node Q1 and the high level of the first clock signal CLK3 of this stage.

[0042] In one embodiment, the fourth node Q4 has been pulled up to a high level, the second switch element T2 is in a conducting state, and at the same time, the first clock signal CLK3 of this stage jumps from a low level to a high level, then the third node Q3 receives the first clock signal CLK3 of this stage at a high level through the second switch element T2 that is turned on, and the third node Q3 is charged to a high level. At the same time, the first node Q1 has been pulled up to a high level, the first switch element T1 is in a conducting state, the output terminal V is connected to the third node Q3 through the first switch element T1 that is turned on, and the output terminal V is at a high level. Thus, the output module 40 works, the third node Q3 is pulled up to a high level, and the output terminal V outputs a high level of the gate output signal Gn of this stage. In one embodiment, the fourth node Q4 is also self-charged and pulled up (charge pump) through the first capacitor C1, so that the level of the fourth node Q4 is further increased, and the second switch element T2 is fully turned on. In one embodiment, the first node Q1 is charge pumped by the second capacitor C2 to further increase the level of the first node Q1 and fully turn on the first switch element T1.

[0043] Pull-down phase: When the subsequent gate output signal Gn+4 changes from low level to high level, the pull-down module 20 controls the first node Q1 to receive the fourth clock signal CLK5 of this stage. Then, when the fourth clock signal CLK5 of this stage changes from high level to low level, the first node Q1 is stably pulled down to a low level.

[0044] In one embodiment, when the post-stage gate output signal Gn+4 changes from a low level to a high level, the seventh switch element T7 receives the post-stage gate output signal Gn+4 at a high level through the seventh control terminal and becomes conductive. Thus, the first node Q1 connected to the thirteenth path terminal of the seventh switch element T7 receives the fourth clock signal CLK5 of this stage through the conductive seventh switch element T7. When the fourth clock signal CLK5 of this stage changes from a high level to a low level, the first node Q1 is stably pulled down to a low level. Thus, the pull-down module 20 realizes pulling down the first node Q1 to a low level.

[0045] In one embodiment, when the rear-stage gate output signal Gn+4 changes from a low level to a high level, the front-stage gate output signal Gn-4 is at a low level, and the sixth switch element T6 receives the front-stage gate output signal Gn-4 at a low level through the sixth control terminal and is in a disconnected state. Thus, the pre-charging module 10 does not enter the working state.

[0046] In one embodiment, when the first node Q1 is pulled down to a low level, the first control terminal of the first switch element T1 connected to the first node Q1 becomes a low level, and the first switch element T1 becomes a disconnected state. At the same time, the second clock signal CLK7 of this stage jumps from a low level to a high level, and the fifth switch element T5 receives the second clock signal CLK7 of this stage at a high level through the fifth control terminal and becomes a conductive state, then the fourth node Q4 receives the low level signal VGL through the conductive fifth switch element T5, and the fourth node Q4 is pulled down to a low level, and the fourth node Q4 is connected to the second control terminal of the second switch element T2, and the second switch element T2 is in a disconnected state; and the fourth switch element T4 receives the second clock signal CLK7 of this stage at a high level through the fourth control terminal and becomes a conductive state, then the third node Q3 receives the low level signal VGL through the conductive fourth switch element T4, and the third node Q3 is pulled down to a low level. Thus, the output module 40 can be used to pull down the third node Q3 to a low level in the pull-down stage, and the output terminal V stops outputting the gate output signal Gn of this stage.

[0047] In one embodiment, when the first node Q1 is pulled down to a low level, the tenth control terminal of the tenth switch element T10 connected to the first node Q1 becomes a low level, and the tenth switch element T10 becomes a disconnected state, so that the second node Q2 receives the second high level signal DC through the turned-on twelfth switch, that is, the second node Q2 becomes a high level, wherein the twelfth switch element T12 receives the second high level signal DC through the twelfth control terminal and is always in a turned-on state. Then the ninth switch element T9 receives a high level through the ninth control terminal connected to the second node Q2 and becomes a turned-on state, the first node Q1 receives a low level signal VGL through the turned-on ninth switch element T9, and the first node Q1 is pulled down to a low level; at the same time, the tenth switch element T10 receives a high level through the tenth control terminal connected to the second node Q2 and becomes a turned-on state, the output terminal V receives a low level signal VGL through the turned-on tenth switch element T10, and the output terminal V is pulled down to a low level. At the same time, the eighth switch element T8 can receive the second clock signal CLK7 of the same stage at a high level through the eighth control terminal and become a conductive state, and the output terminal V can receive the low level signal VGL through the conductive eighth switch element T8, and the output terminal V is pulled down to a low level. Therefore, the stabilization module 30 can be used for the first node Q1 and the output terminal V to achieve a stable low level effect.

[0048] Stabilization phase: That is, in the time period not including the first three stages, the front-stage gate output signal Gn-4 received by the pre-charging module 10 is at a low level, and the pre-charging module 10 does not enter the working state. At the same time, the rear-stage gate output signal Gn+4 received by the pull-down module 20 is at a low level, and the pull-down module 20 does not enter the working state. Therefore, the pre-charging module 10 and the pull-down module 20 have no effect on the first node Q1, the stabilizing module 30 can be used to maintain the first node Q1 and the output terminal V at a low level, and the first pull-down stabilizing unit 42 in the output module 40 can be used to maintain the third node Q3 at a low level.

[0049] In one embodiment, in the stable stage, the front gate output signal Gn-4 is at a low level, and the sixth switch element T6 receives the front gate output signal Gn-4 at a low level through the sixth control terminal and is in a disconnected state. Therefore, the pre-charging module 10 does not enter the working state.

[0050] In one embodiment, in the stable stage, the rear gate output signal Gn+4 is at a low level, and the seventh switch element T7 receives the rear gate output signal Gn+4 at a low level through the seventh control terminal and is in a disconnected state. Therefore, the pull-down module 20 does not enter the working state.

[0051] In one embodiment, in the stable stage, the first node Q1 has been pulled down to a low level, and the tenth control terminal of the tenth switch element T10 connected to the first node Q1 becomes a low level, and the tenth switch element T10 becomes a disconnected state, so that the second node Q2 receives the second high level signal DC through the turned-on twelfth switch, that is, the second node Q2 becomes a high level, wherein the twelfth switch element T12 receives the second high level signal DC through the twelfth control terminal and is always in a turned-on state. Then the ninth switch element T9 receives the high level through the ninth control terminal connected to the second node Q2 and becomes a turned-on state, the first node Q1 receives the low level signal VGL through the turned-on ninth switch element T9, and the first node Q1 is pulled down to a low level; at the same time, the tenth switch element T10 receives the high level through the tenth control terminal connected to the second node Q2 and becomes a turned-on state, the output terminal V receives the low level signal VGL through the turned-on tenth switch element T10, and the output terminal V is pulled down to a low level. At the same time, the eighth switch element T8 can receive the second clock signal CLK7 of the same stage at a high level through the eighth control terminal and become a conductive state, and the output terminal V can receive the low level signal VGL through the conductive eighth switch element T8, and the output terminal V is pulled down to a low level. Therefore, the stabilization module 30 can be used for the first node Q1 and the output terminal V to achieve a stable low level effect.

[0052] In one embodiment, in the stable stage, the first node Q1 has been pulled down to a low level, and the second control terminal of the second switch element T2 connected to the first node Q1 is at a low level, and the second switch element T2 is in a disconnected state. At the same time, whenever the second clock signal CLK7 of the current stage jumps from a low level to a high level, the fifth switch element T5 receives the second clock signal CLK7 of the current stage at a high level through the fifth control terminal and becomes a conductive state, and the fourth node Q4 receives the low level signal VGL through the conductive fifth switch element T5, and the fourth node Q4 is pulled down to a low level, and the fourth node Q4 is connected to the second control terminal of the second switch element T2, and the second switch element T2 is in a disconnected state; and the fourth switch element T4 receives the second clock signal CLK7 of the current stage at a high level through the fourth control terminal and becomes a conductive state, and the third node Q3 receives the low level signal VGL through the conductive fourth switch element T4, and the third node Q3 is pulled down to a low level. Thus, the output module 40 can be used to periodically pull down the third node Q3 to a low level in the stable stage, and the first clock signal CLK3 of this stage will periodically switch between high and low levels, which will generate noise at the third node Q3, effectively reducing the noise of the first node Q1 and the output terminal V, and the third node Q3 is periodically pulled down to a low level, which can prevent the third node Q3 from accumulating to a high level under the noise of the first clock signal CLK3 of this stage, and can maintain the low level state of the third node Q3, effectively reducing the noise of the first node Q1 and the output terminal V, and improving high temperature resistance, which can be used in more usage scenarios such as high temperature.

[0053] Figure 4 FIG. 1 is a circuit connection diagram of a gate drive circuit according to another embodiment of the present invention. Figure 4 This embodiment provides a gate driving circuit, whose basic structure, principle and technical effects are the same as those of the previous embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the previous embodiment.

[0054] In one embodiment of the present invention, Figure 4As shown, the first high-level signal DCH received by the fifth channel end of the third switch element T3 is replaced by the second clock signal CLK7 of this stage. That is, the third control end of the third switch element T3 receives the previous gate output signal Gn-4, the fifth channel end of the third switch element T3 receives the second clock signal CLK7 of this stage, and the sixth channel end of the third switch element T3 is connected to the fourth node Q4. Specifically, if the first high-level signal DCH is replaced by the second clock signal CLK7 of this stage, the fourth node Q4 can still be charged by receiving the second clock signal CLK7 of this stage at a high level through the third switch element T3 that is turned on in the pre-charging stage, and in other stages, the third switch element T3 is in a disconnected state, which has no effect on what signal is on the fifth channel end. Therefore, on the fifth channel of the third switch element T3, the first high-level signal DCH can be replaced by the second clock signal CLK7 of this stage, which can avoid the leakage current always existing at the fifth channel end of the third switch element T3, and the energy loss and heat caused by it.

[0055] In one embodiment of the present invention, Figure 4 As shown, the output module 40 further includes a second pull-down stabilizing unit, which is connected to the output terminal V and pulls the output terminal V down to a low level according to the subsequent gate output signal Gn+4.

[0056] In one embodiment of the present invention, Figure 4 As shown, the second pull-down stabilizing unit includes a thirteenth switch element T13; the thirteenth switch element T13 includes a thirteenth control terminal, a twenty-fifth channel terminal and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switch element T13 receives the rear-stage gate output signal Gn+4, the twenty-fifth channel terminal of the thirteenth switch element T13 is connected to the output terminal V, and the twenty-sixth channel terminal of the thirteenth switch element T13 receives the low-level signal VGL.

[0057] Specifically, when the post-stage gate output signal Gn+4 jumps from a low level to a high level, the thirteenth switch element T13 is in an on state, and the output terminal V can be quickly pulled down to a low level through the turned-on thirteenth switch element T13, which can effectively reduce the falling edge time of the gate output signal without increasing the clock load, thereby improving the product image quality.

[0058] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes a gate driving circuit as provided in the above embodiment, for providing a gate output signal to a gate line of a display panel. The implementation of the display device can refer to the above embodiment of the gate driving circuit, and the repeated parts will not be repeated.

[0059] The multi-level output gate drive circuit and display device of the present invention, the gate drive circuit includes a multi-level gate drive unit, each level of the gate drive unit includes a pre-charging module, a pull-down module, a stabilization module and an output module; the output module is connected to the pre-charging module at the first node, and the output module includes a first switch element, a pre-output unit and a first pull-down stabilization unit; the first control end of the first switch element is connected to the first node, the first path end is connected to the third node, and the second path end is connected to the output end; the pre-output unit charges the third node according to the previous gate output signal and the first clock signal of this level; the first pull-down stabilization unit is used to pull the third node down to a low level according to the second clock signal of this level in the stable stage, and the high level time period of the second clock signal of this level does not overlap with the high level time period of the first clock signal of this level. Thus, the gate drive circuit can be used to generate a gate drive signal, can effectively reduce circuit noise in the stable stage, improve high temperature resistance, and enable the display device to be used in more usage scenarios.

[0060] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the invention. However, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the invention without departing from the content of the technical solution of the invention are still within the scope of the technical solution of the present invention.

Claims

1. A gate drive circuit, characterized in that: include: A multi-stage gate drive unit, each stage of the gate drive unit comprising a pre-charging module (10), a pull-down module (20), a stabilization module (30) and an output module (40); the output module (40) is connected to the pre-charging module (10) at a first node (Q1), and the output module (40) comprises a first switch element (T1), a pre-output unit (41) and a first pull-down stabilization unit (42); The first switch element (T1) comprises a first control end, a first path end and a second path end, the first control end of the first switch element (T1) is connected to the first node (Q1), the first path end of the first switch element (T1) is connected to the third node (Q3), and the second path end of the first switch element (T1) is connected to the output end (V) and is used to output the gate output signal (Gn) of this stage; The pre-output unit (41) is connected to the third node (Q3), and charges the third node (Q3) according to the previous gate output signal (Gn-4) and the first clock signal (CLK3) of the current stage; The first pull-down stabilizing unit (42) is connected to the third node (Q3) and is used to pull the third node (Q3) down to a low level according to the second clock signal (CLK7) of this stage in a stabilizing phase, and the high level time period of the second clock signal (CLK7) of this stage does not overlap with the high level time period of the first clock signal (CLK3) of this stage.

2. The gate driving circuit according to claim 1, characterized in that: The pre-output unit (41) comprises a second switch element (T2) and a third switch element (T3), the second switch element (T2) comprises a second control terminal, a third path terminal and a fourth path terminal, the second control terminal of the second switch element (T2) is connected to a fourth node (Q4), the third path terminal of the second switch element (T2) receives the first clock signal (CLK3) of the current stage, and the fourth path terminal of the second switch element (T2) is connected to the third node (Q3); the third switch element (T3) comprises a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switch element (T3) receives the previous stage gate output signal (Gn-4), the fifth path terminal of the third switch element (T3) receives the first high level signal (DCH), and the sixth path terminal of the third switch element (T3) is connected to the fourth node (Q4).

3. The gate driving circuit according to claim 2, characterized in that: The first pull-down stabilizing unit (42) comprises a fourth switch element (T4) and a fifth switch element (T5); the fourth switch element (T4) comprises a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switch element (T4) receives the second clock signal (CLK7) of the current stage, the seventh path terminal of the fourth switch element (T4) is connected to the third node (Q3), and the eighth path terminal of the fourth switch element (T4) receives a low level signal (VGL); the fifth switch element (T5) comprises a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switch element (T5) receives the second clock signal (CLK7) of the current stage, the ninth path terminal of the fifth switch element (T5) is connected to the fourth node (Q4), and the tenth path terminal of the fifth switch element (T5) receives the low level signal (VGL).

4. The gate driving circuit according to claim 2, characterized in that: The output module (40) further comprises a first capacitor (C1), wherein a first end of the first capacitor (C1) is connected to the fourth node (Q4), and a second end of the first capacitor (C1) is connected to the third node (Q3).

5. The gate driving circuit according to claim 1, characterized in that: The pre-charging module (10) comprises a sixth switch element (T6), the sixth switch element (T6) comprises a sixth control terminal, an eleventh path terminal and a twelfth path terminal, the sixth control terminal of the sixth switch element (T6) receives the previous-stage gate output signal (Gn-4), the eleventh path terminal of the sixth switch element (T6) receives the third clock signal (CLK1) of the current stage, and the twelfth path terminal of the sixth switch element (T6) is connected to the first node (Q1); And / or, the pull-down module (20) comprises a seventh switch element (T7), the seventh switch element (T7) comprises a seventh control terminal, a thirteenth channel terminal and a fourteenth channel terminal, the seventh control terminal of the seventh switch element (T7) receives a subsequent gate output signal (Gn+4), the thirteenth channel terminal of the seventh switch element (T7) is connected to the first node (Q1), and the fourteenth channel terminal of the seventh switch element (T7) receives a fourth clock signal (CLK5) of the current stage; And / or, the stabilization module (30) comprises an eighth switch element (T8), a ninth switch element (T9), a tenth switch element (T10), an eleventh switch element (T11) and a twelfth switch element (T12); the eighth switch element (T8) comprises an eighth control terminal, a fifteenth channel terminal and a sixteenth channel terminal, the eighth control terminal of the eighth switch element (T8) receives the second clock signal (CLK7) of the current stage, the fifteenth channel terminal of the eighth switch element (T8) is connected to the output terminal (V), and the sixteenth channel terminal of the eighth switch element (T8) is connected to the output terminal (V). The ninth switch element (T9) comprises a ninth control terminal, a seventeenth path terminal and an eighteenth path terminal, the ninth control terminal of the ninth switch element (T9) is connected to the second node (Q2), the seventeenth path terminal of the ninth switch element (T9) is connected to the first node (Q1), and the eighteenth path terminal of the ninth switch element (T9) receives the low level signal (VGL); the tenth switch element (T10) comprises a tenth control terminal, a nineteenth path terminal and a twentieth path terminal, the tenth switch element (T10) The tenth control terminal is connected to the first node (Q1), the nineteenth path terminal of the tenth switch element (T10) is connected to the second node (Q2), and the twentieth path terminal of the tenth switch element (T10) receives the low level signal (VGL); the eleventh switch element (T11) includes an eleventh control terminal, a twenty-first path terminal and a twenty-second path terminal, the eleventh control terminal of the eleventh switch element (T11) is connected to the second node (Q2), and the twenty-first path terminal of the eleventh switch element (T11) is connected to the output terminal (V , the twenty-second channel terminal of the eleventh switch element (T11) receives the low level signal (VGL); the twelfth switch element (T12) includes a twelfth control terminal, a twenty-third channel terminal and a twenty-fourth channel terminal, the twelfth control terminal of the twelfth switch element (T12) receives the second high level signal (DC), the twenty-third channel terminal of the twelfth switch element (T12) is connected to the twelfth control terminal of the twelfth switch element (T12), and the twenty-fourth channel terminal of the twelfth switch element (T12) is connected to the second node (Q2).

6. The gate driving circuit according to claim 5, characterized in that: The duty cycle of the third clock signal (CLK1) of this stage, the first clock signal (CLK3) of this stage, the fourth clock signal (CLK5) of this stage and the second clock signal (CLK7) of this stage are all 50%, the clock cycles are all equal, and they are spaced one quarter of the clock cycle in sequence.

7. The gate driving circuit according to claim 2, characterized in that: The first high level signal (DCH) received by the fifth channel end of the third switch element (T3) is replaced by the second clock signal (CLK7) of the current stage.

8. The gate driving circuit according to claim 1, characterized in that: The output module (40) further comprises a second pull-down stabilizing unit, which is connected to the output terminal (V) and pulls the output terminal (V) down to a low level according to a rear-stage gate output signal (Gn+4).

9. The gate driving circuit according to claim 8, characterized in that: The second pull-down stabilization unit includes a thirteenth switch element (T13); the thirteenth switch element (T13) includes a thirteenth control terminal, a twenty-fifth channel terminal and a twenty-sixth channel terminal, the thirteenth control terminal of the thirteenth switch element (T13) receives the rear-stage gate output signal (Gn+4), the twenty-fifth channel terminal of the thirteenth switch element (T13) is connected to the output terminal (V), and the twenty-sixth channel terminal of the thirteenth switch element (T13) receives a low-level signal (VGL).

10. A display device, characterized in that: It comprises the gate driving circuit as claimed in any one of claims 1 to 9.

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