Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention discloses a memory, an operation method of the memory, a memory system and electronic equipment. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit includes: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to: determine a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table comprises a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles are in one-to-one correspondence; a refresh control circuit configured to adjust a refresh cycle of the refresh signal to a target refresh cycle; wherein the refresh signal is used for indicating to execute refresh operation on the memory cell array.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and relate to but are not limited to a memory and an operating method thereof, a memory system, and an electronic device. Background Art

[0002] Semiconductor memories are divided into volatile memories and non-volatile memories according to whether the stored data is retained when power is off, among which volatile memories whose data is lost when power is off may include static random-access memory (SRAM) and dynamic random access memory (DRAM).

[0003] Volatile memory maintains the data stored in the memory cell by periodic refresh. As the temperature rises, the data retention characteristics of the memory cell deteriorate. Therefore, it is necessary to refresh with a shorter refresh cycle (i.e., refresh more frequently) to ensure data reliability. However, frequent refresh will lead to increased power consumption. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, a memory system, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit comprising:

[0006] a temperature sensing circuit, the temperature sensing circuit being configured to: sense a temperature of the memory and generate a temperature signal based on the sensed temperature;

[0007] A control logic circuit, the control logic circuit being configured to: determine a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles correspond one to one;

[0008] A refresh control circuit is configured to: adjust a refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array.

[0009] In a second aspect, an embodiment of the present disclosure further provides a method for operating a memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the operating method includes:

[0010] sensing a temperature of the memory, and generating a temperature signal based on the sensed temperature;

[0011] Determining a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles correspond one to one;

[0012] The refresh cycle of the refresh signal is adjusted to the target refresh cycle; wherein the refresh signal is used to indicate that a refresh operation is performed on the memory cell array.

[0013] In a third aspect, an embodiment of the present disclosure further provides a memory system, the memory system comprising:

[0014] One or more memories as described in any of the above embodiments;

[0015] A memory controller is coupled to the memory and configured to control the memory.

[0016] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising the memory system as described in the above embodiment.

[0017] In the disclosed embodiments, the temperature of the memory is sensed by a temperature sensing circuit and a temperature signal is generated based on the sensed temperature. The control logic circuit determines a target refresh cycle based on the temperature signal and a mapping table. The refresh control circuit adjusts the refresh cycle of the refresh signal to the target refresh cycle. Thus, on the one hand, the refresh cycle can be adjusted based on temperature changes to avoid data loss and ensure data reliability. On the other hand, the refresh cycle can be flexibly adjusted based on temperature changes to avoid frequent refresh operations, thereby reducing power consumption and increasing the service life of the memory. On the third hand, different mapping tables can be customized for different memories without changing the circuit design, thereby increasing the flexibility of refresh cycle adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0019] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0020] Figure 2b is a schematic diagram of a solid state hard disk according to an embodiment of the present disclosure;

[0021] Figure 3 is a schematic diagram showing the variation of leakage current with temperature according to an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram showing the variation of data retention time with temperature according to an embodiment of the present disclosure;

[0023] Figure 5 is a refresh cycle of different temperatures shown according to an embodiment of the present disclosure;

[0024] Figure 6 is a schematic diagram showing the variation of power consumption with self-refresh cycle according to an embodiment of the present disclosure;

[0025] Figure 7a and Figure 7b is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0026] Figure 8 is a schematic diagram showing a refresh cycle changing with temperature according to an embodiment of the present disclosure;

[0027] Fig. 9 is a schematic diagram showing another refresh cycle changing with temperature according to an embodiment of the present disclosure;

[0028] Fig.10 is a schematic diagram of another memory according to an embodiment of the present disclosure;

[0029] Fig.11 is a flow chart of a method for operating a memory according to an embodiment of the present disclosure;

[0030] Fig.12 is a schematic diagram showing a method of adjusting a refresh cycle according to an embodiment of the present disclosure;

[0031] Fig.13 is a schematic diagram of a process of generating a mapping table through an algorithm according to an embodiment of the present disclosure;

[0032] Fig.14 It is a schematic diagram of a process of adjusting a temperature window according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0035] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0036] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0038] Figure 1 1 is a schematic diagram of a system 100 according to an embodiment of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0039] like Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0040] The memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CF Card), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded MultiMedia Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0041] The memory controller 106 may be configured to control the operation of the memory 104, such as read, erase, and write operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0042] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108 in the memory card 202. In some embodiments, the storage capacity and / or operation speed of the SSD 206 is greater than the storage capacity and / or operation speed of the memory card 202. The memory 104 may include a volatile memory and a non-volatile memory, such as a NAND flash memory, a dynamic random access memory, a ferroelectric random access memory, a magnetic random access memory, a phase change random access memory, a resistive random access memory, a nano random access memory, etc.

[0043] The leakage current of the storage unit of the volatile memory is proportional to the temperature, that is, the leakage current increases with the increase of temperature, such as Figure 3 As shown. Since the charge stored in the memory cell is limited, the data retention time of the memory cell is inversely proportional to the temperature. For example, the data retention time at 40°C is t1, and the data retention time at 80°C is t2, and t2 is less than t1, as shown in Figure 4 In order to ensure data reliability, volatile memory needs to perform periodic refresh operations to maintain the data stored in the storage unit.

[0044] There are two ways to perform periodic refresh operations: one is for the memory controller to issue a periodic refresh command, and the memory controller is responsible for maintaining the data; the other is for the memory to generate a refresh signal internally (also known as self-refresh). Self-refresh is a method used to maintain data without an external refresh command. A timer is set inside the memory to trigger periodic refresh operations internally. The user issues a self-refresh entry command to enter the self-refresh mode, and the memory automatically performs a refresh operation internally until a self-refresh exit command is issued.

[0045] Self-refresh operations usually use a fixed refresh cycle, and this fixed cycle should be short enough to ensure that the data remains unchanged during high temperatures. For example, to ensure that the memory works normally at temperatures below 80°C, the refresh cycle should be less than t2, which will result in too frequent self-refresh operations at temperatures below 80°C, which will also cause additional power consumption without any benefits, and also reduce the service life of the memory.

[0046] It should be noted that since the leakage current increases with the increase of temperature, this requires that the refresh cycle of the self-refresh operation becomes shorter with the increase of temperature. For example, the refresh cycle is t low , at high temperature t high , t high Less than t low ,like Figure 5 However, a shorter refresh cycle means a higher refresh frequency, which will lead to higher power consumption. For example, the refresh cycle is t low When the power consumption is P low , the refresh cycle is t high When the power consumption is P high , P high Greater than P low ,like Figure 6 shown.

[0047] Based on this, in order to solve one or more of the above technical problems, an embodiment of the present disclosure provides a memory.

[0048] Figure 7a and Figure 7b is a schematic diagram of a memory 300 according to an embodiment of the present disclosure. Figure 7a and Figure 7b As shown, the memory 300 includes a memory cell array 320 and a peripheral circuit 310 coupled to the memory cell array 320; the peripheral circuit 310 includes:

[0049] The temperature sensing circuit 330 is configured to: sense the temperature of the memory 300 and generate a temperature signal based on the sensed temperature;

[0050] The control logic circuit 340 is configured to: determine a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles correspond one to one;

[0051] The refresh control circuit 350 is configured to: adjust the refresh period of the refresh signal to a target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array 320 .

[0052] In the disclosed embodiment, the memory 300 includes but is not limited to DRAM, double data rate synchronous dynamic random access memory (Double Data Rate, DDR), low power double data rate dynamic random access memory (Low Power Double Data Rate, LPDDR), graphics double data rate dynamic random access memory (Graphics Double Data Rate, GDDR) and high bandwidth memory (High Bandwidth Memory, HBM), etc.

[0053] Reference Figure 7b As shown, the memory 300 includes a plurality of word lines 322 and a plurality of bit lines 323, and the peripheral circuit 310 is coupled to the memory cell array 320 through the plurality of word lines 322 and the plurality of bit lines 323. The memory cell array 320 includes a plurality of memory cells 321 arranged in an array, and the memory cell 321 includes a transistor 324 and an energy storage element 325 coupled to the transistor 324. The transistor 324 includes a semiconductor column 326, a gate dielectric layer 327 and a gate 328, the semiconductor column includes a source, a drain and a channel between the source and the drain, the gate dielectric layer 327 covers the sidewall of the channel, and the gate 328 contacts at least one sidewall of the gate dielectric layer 327; wherein the word line 322 is coupled to the gate of the memory cell 321 in the same row, and the bit line 323 is coupled to the semiconductor column (for example, the drain of the semiconductor column) of the memory cell 321 in the same column.

[0054] In a specific embodiment, the storage unit 321 may be a volatile storage unit. For example, a DRAM storage unit, and the energy storage element 325 may be a capacitor. Of course, in other embodiments, the storage unit 321 may be a phase change storage unit, and the energy storage element 325 may be a phase change storage layer; or, the storage unit 321 may also be a ferroelectric storage unit, and the energy storage element 325 may be a ferroelectric storage layer; the present disclosure does not limit this.

[0055] The temperature sensing circuit 330 can sense the temperature of the memory 300 and output a temperature signal based on the sensed temperature. In a specific embodiment, the temperature sensing circuit 330 includes a temperature sensor, which can convert an analog temperature signal into a digital temperature signal and send the digital temperature signal to the control logic circuit 340. The temperature signal output by the temperature sensor can be a voltage signal corresponding to the sensed temperature, and the number of temperature sensors can be one or more. Although the present embodiment describes the case where the temperature sensing circuit 330 is located in the memory 300, the temperature sensing circuit 330 can be outside the memory 300 and sense the temperature of the memory 300.

[0056] It should be noted that the memory 300 may be divided into a plurality of temperature sections according to its operating temperature range, and the temperature signals corresponding to different temperatures may be the same or different. For example, if the first temperature and the second temperature belong to the same temperature section, the temperature signals corresponding to the first temperature and the second temperature may be the same; for another example, if the first temperature and the second temperature belong to different temperature sections, the temperature signals corresponding to the first temperature and the second temperature may be different.

[0057] For example, refer to Figure 8 As shown, 7 key temperatures are selected within the operating temperature range of the memory 300, for example, the key temperature T e1 、T e2 、T e3 、T e4 、T e5 、T e6 and T e7 , can be divided into 7 temperature sections, and the 7 temperature sections correspond to 7 preset temperature signals respectively. For example, the preset temperature signal T in Table 1 code1 、T code2 、T code3 、T code4 、T code5 、T code6 and T code7 .

[0058] In a specific example, the operating temperature range of the memory 300 is 20°C≤T≤80°C, and the seven key temperatures are 25°C, 35°C, 45°C, 50°C, 60°C, 70°C and 80°C. When the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40°C, corresponding to the third temperature segment, the temperature sensor outputs a temperature signal T code3 .

[0059] It should be noted that the critical temperature and / or the number of critical temperatures can be determined based on the temperature variation characteristics of the leakage current of the memory 300. For example, if the leakage current of the memory 300 changes dramatically at at least one temperature, the temperature can be determined as the critical temperature. For another example, if the leakage current of the memory 300 is more sensitive to temperature variations, more critical temperatures can be selected to divide more temperature segments to achieve more precise adjustment of the refresh cycle. The above values ​​are only examples for conveying the present disclosure to those skilled in the art, and the critical temperature and / or the number of critical temperatures are not limited thereto.

[0060] The control logic circuit 340 may receive a temperature signal and determine a target refresh cycle based on the received temperature signal and a mapping table. For example, referring to Table 1, the mapping table includes 7 preset temperature signals T code1 、T code2 、T code3 、T code4 、T code5 、T code6 and T code7 , the 7 preset temperature signals correspond to 7 preset refresh cycles R1, R2, R3, R4, R5, R6 and R7 respectively. When the control logic circuit 340 receives the temperature signal T code3 When the target refresh cycle is determined to be R3, the refresh control circuit 350 adjusts the refresh cycle of the refresh signal to the target refresh cycle R3, and performs a refresh operation on the memory cell array 320 with the target refresh cycle R3 as the refresh cycle.

[0061] Table 1 Mapping table

[0062]

[0063] For example, at the first moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 is 75° C. and outputs a temperature signal T code7 , the control logic circuit 340 is based on the temperature signal T code7 The target refresh cycle is determined to be R7 by looking up the mapping table. The refresh control circuit 350 adjusts the refresh cycle of the refresh signal to the target refresh cycle R7 to avoid data loss. At the second moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 drops to 40°C and outputs a temperature signal T code3 , the control logic circuit 340 is based on the temperature signal T code3The target refresh cycle is determined to be R3 by looking up the mapping table, and the refresh control circuit 350 adjusts the refresh cycle of the refresh signal to the target refresh cycle R3. It can be understood that after the temperature drops to 40°C, the leakage current of the storage unit will decrease, and the refresh cycle is adjusted to the target refresh cycle R3, which is sufficient to maintain the data, thereby avoiding frequent refreshes. In this way, the refresh cycle can be adjusted based on the change in temperature to avoid data loss, thereby ensuring the reliability of the data; at the same time, the refresh cycle can be flexibly adjusted based on the change in temperature to avoid frequent refresh operations, thereby reducing power consumption.

[0064] In practical applications, different mapping tables can be customized for different memories, increasing the flexibility of adjusting the refresh cycle. For example, before the memory leaves the factory, R&D personnel develop and design different mapping tables for different memories and write (also called program) the mapping tables into the memory.

[0065] In the disclosed embodiments, the temperature of the memory is sensed by a temperature sensing circuit and a temperature signal is generated based on the sensed temperature. The control logic circuit determines a target refresh cycle based on the temperature signal and a mapping table. The refresh control circuit adjusts the refresh cycle of the refresh signal to the target refresh cycle. Thus, on the one hand, the refresh cycle can be adjusted based on temperature changes to avoid data loss and ensure data reliability. On the other hand, the refresh cycle can be flexibly adjusted based on temperature changes to avoid frequent refresh operations, thereby reducing power consumption and increasing the service life of the memory. On the third hand, different mapping tables can be customized for different memories without changing the circuit design, thereby increasing the flexibility of refresh cycle adjustment.

[0066] In some embodiments, the peripheral circuit 310 further includes:

[0067] The register circuit 360 is configured to: store a mapping table; wherein the mapping table includes a plurality of sub-mapping tables, and the sub-mapping tables are used to record the correspondence between the preset temperature signal and the preset refresh cycle;

[0068] An address decoding circuit 370, the address decoding circuit 370 is configured to: decode and generate a first target address based on the temperature signal; wherein the first target address is used to indicate a physical address of a first sub-mapping table in the plurality of sub-mapping tables;

[0069] The control logic circuit 340 is specifically configured to: based on the first target address, obtain the first sub-mapping table and determine the target refresh cycle.

[0070] In the embodiment of the present disclosure, the mapping table can be stored in the register circuit 360, and the mapping table includes multiple sub-mapping tables, and different mapping sub-tables record the corresponding relationship between different preset temperature signals and preset refresh cycles. For example, referring to Table 1, the mapping table includes 7 sub-mapping tables, and the first sub-mapping table records the preset temperature signal T code1 and the mapping relationship between the preset refresh cycle R1, and the second sub-mapping table records the preset temperature signal T code2 and the mapping relationship between the preset refresh cycle R2, ..., the seventh sub-mapping table records the preset temperature signal T code7 and the mapping relationship between the preset refresh period R7, the number of sub-mapping tables in the mapping table is not limited to 7, and the number of sub-mapping tables can be less than or greater than 7.

[0071] Exemplarily, the address decoding circuit 370 receives the temperature signal T code3 , decode the temperature signal to generate a first target address, and send the first target address to the control logic circuit 340; the control logic circuit 340 reads the third sub-mapping table in the register circuit 360 based on the first target address, and determines the target refresh cycle R3. It can be understood that multiple sub-mapping tables are stored in different positions in the register circuit 360, corresponding to multiple different physical addresses, the first sub-mapping table is a sub-mapping table among the multiple sub-mapping tables, and the first target address is the physical address corresponding to the sub-mapping table. In this example, the first sub-mapping table is the third sub-mapping table, and the first target address is the physical address of the third sub-mapping table.

[0072] The register circuit 360 includes but is not limited to a mode register, which can store various operating parameters and control parameters of the operating memory 300, etc. The mode register can be programmed to set multiple operating parameters and control parameters, and the mode register can store parameter codes. For example, the mode register can store parameter codes (i.e., a mapping table) of multiple refresh cycles related to the temperature signal, and the mode register can be read to determine the target refresh cycle. In a specific embodiment, the mode register can store data temporarily or permanently.

[0073] In some embodiments, the memory cell array 320 includes a first memory cell and a second memory cell, and the data retention time of the second memory cell is less than the data retention time of the second memory cell; the control logic circuit 340 is specifically configured as follows:

[0074] Based on the first target address, obtaining a first sub-mapping table, and determining a first target refresh cycle of the first storage unit;

[0075] Based on the offset first target address, a second sub-mapping table among the plurality of sub-mapping tables is obtained to determine a second target refresh cycle of the second storage unit; wherein the second sub-mapping table is different from the first sub-mapping table; and the second target refresh cycle is less than the first target refresh cycle.

[0076] The memory cell array 320 includes a plurality of memory cells 321. The data retention characteristics of any two memory cells 321 at the same temperature may be the same or different, depending on the characteristics of the memory cells 321. For example, the memory cell array 320 includes a first memory cell and a second memory cell. At the same temperature, the data retention time of the second memory cell is less than the data retention time of the second memory cell, that is, the data retention characteristic of the second memory cell is worse. In order to avoid data loss, different refresh cycles can be set for memory cells with different data retention characteristics. The following will be combined with Table 1, Figure 8 and Fig. 9 Provide explanation.

[0077] For example, combining Table 1 and Figure 8 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40° C., the temperature signal T code3 The address decoding circuit 370 is based on the temperature signal T code3 Decoding generates a first target address; the control logic circuit 340 reads the third sub-mapping table based on the first target address and determines the target refresh cycle R3 of the first storage unit. Here, the first sub-mapping table is the third sub-mapping table, the first target address is the physical address of the third sub-mapping table, and the first target refresh cycle is the target refresh cycle R3.

[0078] For example, combining Table 1 and Fig. 9 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40° C., the temperature signal T code3 The address decoding circuit 370 is based on the temperature signal T code3 Decoding generates a first target address; the control logic circuit 340 reads the fourth sub-mapping table based on the offset first target address, and determines the target refresh cycle R4 of the second storage unit, R4<R3. Here, the second sub-mapping table is the fourth sub-mapping table, the offset first target address is the physical address of the fourth sub-mapping table, and the second target refresh cycle is the target refresh cycle R4.

[0079] It should be noted that, in the embodiment of the present disclosure, the second sub-mapping table can be obtained by offsetting the target address, and in other embodiments, the second sub-mapping table can be obtained by offsetting the temperature signal. For example, a second target address different from the first target address is generated based on the offset temperature signal decoding, and the second target address is used to indicate the physical address of the second sub-mapping table.

[0080] In the embodiment of the present disclosure, a second sub-mapping table different from the first sub-mapping table can be obtained by offsetting the first target address, and a second target refresh cycle is determined based on the second sub-mapping table. In this way, different refresh cycles can be set for storage units with different data retention characteristics, thereby avoiding data loss in the second storage unit with poor data retention characteristics due to temperature increase, which is beneficial to further ensure data reliability.

[0081] In some embodiments, the first memory cell and the second memory cell are located in the same memory cell row; the refresh control circuit 350 is specifically configured to: adjust the refresh period of the memory cell row to the second target refresh period.

[0082] The memory cell array 320 includes a plurality of memory cell rows, each memory cell row includes a plurality of memory cells 321, and one memory cell row is coupled to a word line 322. Since the refresh operation of the memory 300 is usually performed row by row, when the first memory cell and the second memory cell are located in the same memory cell row, the refresh cycle can be adjusted to the second target refresh cycle, thereby avoiding the loss of data of the first memory cell and the second memory cell.

[0083] In some embodiments, the first storage cell and the second storage cell are located in different storage cell rows; the refresh control circuit 350 is specifically configured to: adjust the refresh period of the storage cell row corresponding to the first storage cell to the first target refresh period; and adjust the refresh period of the storage cell row corresponding to the second storage cell to the second target refresh period.

[0084] It can be understood that in the embodiment of the present disclosure, when the first storage unit and the second storage unit are located in different storage unit rows, the refresh cycles can be adjusted separately for different storage unit rows, that is, the refresh cycle of the storage unit row corresponding to the first storage unit is adjusted to the first target refresh cycle, and the refresh cycle of the storage unit row corresponding to the second storage unit is adjusted to the second target refresh cycle. While ensuring that the data of the first storage unit and the second storage unit are not lost, the power consumption can be reduced and the service life of the memory can be increased.

[0085] In some embodiments, the peripheral circuit 310 further includes:

[0086] An address shift circuit 380, the address shift circuit 380 is configured to: generate a second target address based on the first target address by shifting, the second target address being used to indicate a physical address of a second sub-mapping table in the plurality of sub-mapping tables;

[0087] The control logic circuit 340 is specifically configured to: based on the second target address, obtain the second sub-mapping table and determine the second target refresh cycle.

[0088] For example, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40° C., the temperature sensing circuit 330 outputs a temperature signal T code3 The address decoding circuit 370 is based on the temperature signal T code3 The decoding generates a first target address; the address shift circuit 380 generates a second target address based on the first target address by shifting; the control logic circuit 340 reads the fourth sub-mapping table based on the second target address to determine the target refresh cycle R4 of the second storage unit, R4<R3.

[0089] In some embodiments, the address shift operation may be performed for a specific temperature window. e2 To T e6 .

[0090] For example, refer to Figure 8 As shown, when the temperature is less than or equal to T e2 When the temperature is greater than T, the preset refresh cycle can be set to a fixed value R2 to avoid data loss while reducing power consumption; e2 and less than or equal to T e6 , 4 preset refresh cycles R3, R4, R5, and R6 can be set for the 4 temperature segments respectively; when the temperature is greater than T e6 and less than or equal to T e7 When the preset refresh cycle can be set to a fixed value R7, to avoid data loss due to high temperature. e2 To T e6 The data retention characteristics of the storage unit vary significantly with temperature. Therefore, the data retention characteristics of the storage unit can be optimized for a specific temperature window T. e2 To T e6 Perform address offset operation.

[0091] For example, when the temperature sensed by the temperature sensor is greater than T e2 and less than or equal to T e6 When the address shift circuit 380 generates a second target address based on the first target address offset, the control logic circuit 340 determines the first target refresh cycle and the second target refresh cycle based on the first target address and the second target address, respectively, to adapt to the data retention characteristics of different storage cells.

[0092] For example, when the temperature sensed by the temperature sensor is less than or equal to T e2 Or greater than T e6 When the first target address is set, the control logic circuit 340 determines a first target refresh cycle based on the first target address.

[0093] In the embodiment of the present disclosure, by setting the address shift circuit 380, the first target address generated by decoding the temperature signal can be shifted to generate a second target address, and the second target refresh cycle is determined based on the second target address. In this way, for storage units with different data retention characteristics, there is no need to change the mapping table or add other mapping tables (for example, different mapping tables are designed for storage units with different data retention characteristics), and the refresh cycle can be adjusted through simple circuit design.

[0094] In some embodiments, at a first temperature, there is a first difference between the first target refresh period and the second target refresh period; at a second temperature, there is a second difference between the first target refresh period and the second target refresh period; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

[0095] At different temperatures, the difference between the data retention time of the first storage unit and the second storage unit may be different. For example, at low temperatures, the difference between the data retention time of the first storage unit and the second storage unit is small; at high temperatures, the difference between the data retention time of the first storage unit and the second storage unit is large. Therefore, different refresh cycle offsets can be set based on different temperatures.

[0096] Exemplarily, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40°C, the first target refresh cycle is determined to be R3, the second target refresh cycle is determined to be R4, and there is a first difference between the first target refresh cycle R3 and the second target refresh cycle R4; when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 60°C, the first target refresh cycle is determined to be R5, the second target refresh cycle is determined to be R6, and there is a second difference between the first target refresh cycle R5 and the second target refresh cycle R6; wherein, the second difference is greater than the first difference.

[0097] In the disclosed embodiment, different refresh cycle offsets are set for different temperatures. Based on the differences in data retention characteristics of different storage units at different temperatures, the refresh cycle can be reasonably set, which is beneficial to further reduce power consumption and increase the service life of the memory 300.

[0098] Fig.10 is a schematic diagram of another memory 300 according to an embodiment of the present disclosure. Fig.10 The storage cell array 320, temperature sensing circuit 330, control logic circuit 340, refresh control circuit 350, register circuit 360, address decoding circuit 370, and address shift circuit 380 are similar to the above embodiment and will not be described in detail. Fig.10The peripheral circuit 310 further includes an electrical fuse circuit 390 , which is configured to store a mapping table. The control logic circuit 340 is specifically configured to read the mapping table in the electrical fuse circuit 390 and save the read mapping table into the register circuit 360 .

[0099] The electric fuse circuit 390 is used to save the mapping table. The electric fuse circuit 390 includes a programmable logic device, such as a one-time programmable (OTP) register, a few-time programmable (FTP) register, or a multi-time programmable (MTP) register. OTP includes a fuse OTP or an anti-fuse OTP. Before the memory 300 leaves the factory, the mapping table can be written into the electric fuse circuit 390. Since OTP, FTP, MTP, etc. are non-volatile, the mapping table can still be saved when the memory 300 is powered off to avoid the loss of the mapping table.

[0100] The control logic circuit 340 can first read the mapping table in the electric fuse circuit 390, and cache the read mapping table in the register circuit 360, so that when the temperature changes (for example, increases or decreases), the target refresh cycle is determined based on the temperature signal output by the temperature sensing circuit 330 and the mapping table cached in the register circuit 360, and the refresh cycle of the refresh signal is adjusted to the target refresh cycle in a timely manner.

[0101] In the disclosed embodiment, an electric fuse circuit is provided to store the mapping table. Due to the non-volatility of the electric fuse circuit, the mapping table can still be saved when the memory is powered off, thereby avoiding the loss of the mapping table.

[0102] In some embodiments, the memory 300 is also configured to: after the usage time of the memory 300 is greater than or equal to a preset time length, update the preset refresh cycle corresponding to at least one preset temperature signal in the mapping table; wherein the updated preset refresh cycle is less than the preset refresh cycle corresponding to at least one preset temperature signal before the update.

[0103] Compared to when the memory 300 is just leaving the factory, the performance of the memory 300 may degrade after being used for a period of time. For example, the data retention time of the storage unit may be reduced at at least one temperature. Therefore, after the usage time of the memory 300 is greater than or equal to the preset time, the preset refresh period corresponding to at least one preset temperature signal may be adjusted to a smaller value. For example, the preset temperature signal T in the third sub-mapping table code3 The corresponding preset refresh cycle is R3. After a period of use, the preset temperature signal T in the third sub-mapping table can be code3The corresponding preset refresh cycle is R3', and R3' is less than R3. The preset duration includes one month, half a year, one year or other longer time. It should be noted that after the usage time of the memory 300 is greater than or equal to the preset duration, the preset refresh cycle corresponding to one or more preset temperature signals in the mapping table can be updated, and the present disclosure has no special restrictions on this.

[0104] In the embodiment of the present disclosure, after the usage time of the memory is greater than or equal to the preset time, the preset refresh cycle corresponding to at least one preset temperature signal in the mapping table is updated, and the updated preset refresh cycle is less than the preset refresh cycle corresponding to at least one preset temperature signal before the update. In this way, the preset refresh cycle corresponding to the preset temperature signal can be adjusted in time according to the usage time of the memory, which can further avoid data loss and increase the service life of the memory.

[0105] Based on the above memory, an embodiment of the present disclosure further provides a method for operating the memory.

[0106] Fig.11 is a flow chart of a method for operating a memory according to an embodiment of the present disclosure. Fig.11 As shown, the operation method at least includes the following steps:

[0107] Step S410: sensing the temperature of the memory, and generating a temperature signal based on the sensed temperature;

[0108] Step S420: determining a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles correspond one to one;

[0109] Step S430: adjusting the refresh period of the refresh signal to the target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array.

[0110] In some embodiments, the mapping table includes a plurality of sub-mapping tables, and the sub-mapping tables are used to record the correspondence between the preset temperature signal and the preset refresh cycle; the above step S420 includes:

[0111] Based on the temperature signal, decoding generates a first target address; wherein the first target address is used to indicate a physical address of a first sub-mapping table among the multiple sub-mapping tables;

[0112] Based on the first target address, a first sub-mapping table is obtained to determine a target refresh period.

[0113] In some embodiments, the memory cell array includes a first memory cell and a second memory cell, and the data retention time of the second memory cell is less than the data retention time of the second memory cell;

[0114] The above method of acquiring the first sub-mapping table based on the first target address and determining the target refresh cycle includes:

[0115] Based on the first target address, obtaining a first sub-mapping table, and determining a first target refresh cycle of the first storage unit;

[0116] The above operation method also includes:

[0117] Based on the offset first target address, a second sub-mapping table among the plurality of sub-mapping tables is obtained to determine a second target refresh cycle of the second storage unit; wherein the second sub-mapping table is different from the first sub-mapping table; and the second target refresh cycle is less than the first target refresh cycle.

[0118] In some embodiments, the obtaining of a second sub-mapping table from the plurality of sub-mapping tables based on the offset first target address and determining a second target refresh cycle of the second storage unit includes:

[0119] Based on the first target address, offset generates a second target address, where the second target address is used to indicate a physical address of a second sub-mapping table in the plurality of sub-mapping tables;

[0120] Based on the second target address, a second sub-mapping table is obtained to determine a second target refresh cycle.

[0121] In some embodiments, at a first temperature, there is a first difference between the first target refresh period and the second target refresh period; at a second temperature, there is a second difference between the first target refresh period and the second target refresh period; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

[0122] In some embodiments, the first storage unit and the second storage unit are located in the same storage unit row; the above-mentioned adjusting the refresh period of the refresh signal to the target refresh period includes:

[0123] The refresh period of the memory cell row is adjusted to a second target refresh period.

[0124] In some embodiments, the first storage unit and the second storage unit are located in different storage unit rows; and the step of adjusting the refresh period of the refresh signal to the target refresh period includes:

[0125] Adjusting the refresh period of the memory cell row corresponding to the first memory cell to a first target refresh period;

[0126] The refresh period of the memory cell row corresponding to the second memory cell is adjusted to a second target refresh period.

[0127] In some embodiments, the peripheral circuit includes an electric fuse circuit and a register circuit, and the electric fuse circuit is configured to store a mapping table; the above operation method further includes:

[0128] The mapping table in the electric fuse circuit is read, and the read mapping table is stored in the register circuit.

[0129] In some embodiments, the above operation method further includes:

[0130] After the usage time of the memory is greater than or equal to the preset time length, the preset refresh cycle corresponding to at least one preset temperature signal in the mapping table is updated; wherein the updated preset refresh cycle is less than the preset refresh cycle corresponding to at least one preset temperature signal before the update.

[0131] The above operation method has been introduced in detail on the memory side and will not be repeated here for the sake of brevity.

[0132] Fig.12 This is a schematic diagram of adjusting the refresh cycle according to an embodiment of the present disclosure. Fig.12 As shown, the temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature; the control logic circuit receives the temperature signal and determines the target refresh cycle based on the temperature signal and the mapping table; the refresh control circuit adjusts the refresh cycle of the refresh signal to the target refresh cycle. Here, the mapping table is used to store the results of the computer algorithm, and the algorithm can be developed in parallel with the circuit design of the memory; it is written after the chip is tested. Of course, in other circuit design and chip testing processes, the algorithm can be optimized according to the circuit design and test results.

[0133] In a specific embodiment, referring to Fig.12 As shown, the address decoding circuit receives the temperature signal, decodes the temperature signal to generate a target address; the control logic circuit reads the first sub-mapping table in the register circuit based on the target address and outputs the result, which is used to indicate the target refresh cycle.

[0134] Fig.13 FIG. 1 is a flow chart showing a method of generating a mapping table by an algorithm according to an embodiment of the present disclosure. Fig.13 The above embodiments illustrate the process of generating a mapping table in the embodiment of the present disclosure.

[0135] Execute step S510: select a key temperature. Select at least one key temperature within the operating temperature range of the memory. For example, if the operating temperature range of the memory is 20°C ≤ T ≤ 80°C, 7 key temperatures can be selected: 25°C, 35°C, 45°C, 50°C, 60°C, 70°C and 80°C.

[0136] Execute step S520: calculate the configuration value. Calculate the refresh cycles (ie, configuration values) corresponding to the 7 key temperatures, and establish a corresponding relationship between the 7 key temperatures and the 7 configuration values, ie, a mapping table.

[0137] Execute step S530: save the mapping table to the electrical fuse circuit. For example, the data of the mapping table is stored in the electrical fuse circuit through programming.

[0138] Execute step S540: test the configuration value, for example, provide a test temperature and test the memory.

[0139] Execute step S550: determine whether the configuration value meets the requirements based on the test results; if so, complete; if not, return to step S520, recalculate the configuration value by adjusting the algorithm, and write the newly calculated configuration value into the capacitor wire circuit until the requirements are met. Here, at the test temperature, when the configuration value corresponding to the test temperature is used as the refresh cycle, the memory is sufficient to retain the data, and it can be determined that the configuration value meets the requirements.

[0140] Fig.14 FIG. 1 is a flow chart of adjusting the temperature window according to an embodiment of the present disclosure. Fig.14 The above embodiments illustrate the process of adjusting the temperature window in the embodiment of the present disclosure.

[0141] Execute step S610: select a key temperature. Select at least one key temperature within the operating temperature range of the memory. For example, the operating temperature range of the memory is 20°C ≤ T ≤ 80°C, and 7 key temperatures can be selected: 25°C, 35°C, 45°C, 50°C, 60°C, 70°C, and 80°C.

[0142] Execute step S620: determine the temperature window. For example, when the temperature is greater than 40°C and less than or equal to 70°C, the refresh cycle changes with the temperature, and 40°C to 70°C can be used as the temperature window.

[0143] Execute step S630: offset the temperature signal. For example, once the above temperature window cannot meet the requirements, the minimum threshold of the temperature window needs to be switched from 40°C to 35°C. Simply offset the temperature by -5°C so that the actual temperature is 40°C and the temperature signal is the temperature signal corresponding to 35°C. Then read the configuration value according to the offset temperature signal.

[0144] Execute step S640: test the configuration value, for example, provide a test temperature and test the memory.

[0145] Execute step S650: determine whether the requirements are met based on the test results; if so, complete; if not, return to step S630, re-offset the temperature signal by adjusting the algorithm, and write the configuration value corresponding to the new temperature window into the capacitor wire circuit until the requirements are met. Here, at the test temperature, when the configuration value corresponding to the test temperature is used as the refresh cycle, the memory is sufficient to retain the data, and it can be determined that the temperature window meets the requirements.

[0146] The present disclosure also provides a memory system. Figure 1 As shown, the memory system 102 includes:

[0147] One or more memories 300 according to any of the above embodiments;

[0148] The memory controller 106 is coupled to the memory 300 and is configured to control the memory 300 .

[0149] The memory 300 may correspond to the reference Figure 1 Regarding the memory 104 in the illustrated embodiment, the functions, applications and interaction between the memory 300 and the memory controller 106 are not described in detail herein.

[0150] An embodiment of the present disclosure further provides an electronic device, including the memory system as described in the above embodiment.

[0151] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0152] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0153] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; The peripheral circuit comprises: a temperature sensing circuit, the temperature sensing circuit being configured to: sense a temperature of the memory and generate a temperature signal based on the sensed temperature; A control logic circuit, the control logic circuit being configured to: determine a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles correspond one to one; A refresh control circuit is configured to: adjust a refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array.

2. The memory according to claim 1, characterized in that: The peripheral circuit also includes: A register circuit, the register circuit being configured to: store the mapping table; wherein the mapping table includes a plurality of sub-mapping tables, the sub-mapping tables being used to record the corresponding relationship between the preset temperature signal and the preset refresh cycle; An address decoding circuit, the address decoding circuit being configured to: decode and generate a first target address based on the temperature signal; wherein the first target address is used to indicate a physical address of a first sub-mapping table among the multiple sub-mapping tables; The control logic circuit is specifically configured to: based on the first target address, obtain the first sub-mapping table and determine the target refresh cycle.

3. The memory according to claim 2, characterized in that: The memory cell array includes a first memory cell and a second memory cell, and the data retention time of the second memory cell is shorter than the data retention time of the second memory cell; the control logic circuit is specifically configured as follows: Based on the first target address, obtaining the first sub-mapping table, and determining a first target refresh period of the first storage unit; Based on the offset first target address, a second sub-mapping table among the multiple sub-mapping tables is obtained to determine a second target refresh cycle of the second storage unit; wherein the second sub-mapping table is different from the first sub-mapping table; and the second target refresh cycle is less than the first target refresh cycle.

4. The memory according to claim 3, characterized in that: The peripheral circuit also includes: An address shift circuit, wherein the address shift circuit is configured to: generate a second target address by shifting based on the first target address, wherein the second target address is used to indicate a physical address of the second sub-mapping table in the plurality of sub-mapping tables; The control logic circuit is specifically configured to: based on the second target address, obtain the second sub-mapping table and determine the second target refresh period.

5. The memory according to claim 3, characterized in that: At a first temperature, there is a first difference between the first target refresh period and the second target refresh period; At a second temperature, there is a second difference between the first target refresh period and the second target refresh period; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

6. The memory according to claim 3, characterized in that: The first storage unit and the second storage unit are located in the same storage unit row; the refresh control circuit is specifically configured as follows: The refresh period of the memory cell row is adjusted to the second target refresh period.

7. The memory according to claim 3, characterized in that: The first storage unit and the second storage unit are located in different storage unit rows; the refresh control circuit is specifically configured as follows: adjusting a refresh period of a memory cell row corresponding to the first memory cell to the first target refresh period; The refresh period of the memory cell row corresponding to the second memory cell is adjusted to the second target refresh period.

8. The memory according to claim 2, characterized in that: The peripheral circuit also includes: an electric fuse circuit, the electric fuse circuit being configured to: store the mapping table; The control logic circuit is specifically configured to: read the mapping table in the electrical fuse circuit, and save the read mapping table into the register circuit.

9. The memory according to claim 1, characterized in that: The memory is further configured to: After the usage time of the memory is greater than or equal to the preset time length, the preset refresh period corresponding to at least one preset temperature signal in the mapping table is updated; wherein the updated preset refresh period is less than the preset refresh period corresponding to the at least one preset temperature signal before the update.

10. A method for operating a memory, characterized in that: The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the operating method includes: sensing a temperature of the memory, and generating a temperature signal based on the sensed temperature; Determining a target refresh cycle based on the temperature signal and a mapping table; wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh cycles, and the plurality of preset temperature signals and the plurality of preset refresh cycles correspond one to one; The refresh cycle of the refresh signal is adjusted to the target refresh cycle; wherein the refresh signal is used to indicate that a refresh operation is performed on the memory cell array.

11. The operating method according to claim 10, characterized in that: The mapping table includes a plurality of sub-mapping tables, and the sub-mapping tables are used to record the corresponding relationship between the preset temperature signal and the preset refresh cycle; and determining the target refresh cycle based on the temperature signal and the mapping table includes: Based on the temperature signal, decoding generates a first target address; wherein the first target address is used to indicate a physical address of a first sub-mapping table among the multiple sub-mapping tables; Based on the first target address, the first sub-mapping table is obtained to determine the target refresh period.

12. The operating method according to claim 11, characterized in that: The memory cell array includes a first memory cell and a second memory cell, and the data retention time of the second memory cell is less than the data retention time of the second memory cell; the acquiring the first sub-mapping table based on the first target address and determining the target refresh cycle includes: Based on the first target address, obtaining the first sub-mapping table, and determining a first target refresh period of the first storage unit; The operation method also includes: Based on the offset first target address, a second sub-mapping table among the multiple sub-mapping tables is obtained to determine a second target refresh cycle of the second storage unit; wherein the second sub-mapping table is different from the first sub-mapping table; and the second target refresh cycle is less than the first target refresh cycle.

13. The operating method according to claim 12, characterized in that: The acquiring, based on the first target address of the offset, a second sub-mapping table among the plurality of sub-mapping tables, and determining a second target refresh period of the second storage unit comprises: Based on the first target address, offset to generate a second target address, where the second target address is used to indicate a physical address of the second sub-mapping table in the plurality of sub-mapping tables; Based on the second target address, the second sub-mapping table is obtained to determine the second target refresh period.

14. The operating method according to claim 12, characterized in that: At a first temperature, there is a first difference between the first target refresh period and the second target refresh period; At a second temperature, there is a second difference between the first target refresh period and the second target refresh period; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

15. The operating method according to claim 12, characterized in that: The first storage unit and the second storage unit are located in the same storage unit row; and the step of adjusting the refresh period of the refresh signal to the target refresh period comprises: The refresh period of the memory cell row is adjusted to the second target refresh period.

16. The operating method according to claim 12, characterized in that: The first storage unit and the second storage unit are located in different storage unit rows; and the step of adjusting the refresh period of the refresh signal to the target refresh period comprises: adjusting a refresh period of a memory cell row corresponding to the first memory cell to the first target refresh period; The refresh period of the memory cell row corresponding to the second memory cell is adjusted to the second target refresh period.

17. The operating method according to claim 10, characterized in that: The peripheral circuit includes an electric fuse circuit and a register circuit, and the electric fuse circuit is configured to store the mapping table; the operating method further includes: The mapping table in the electrical fuse circuit is read, and the read mapping table is stored in the register circuit.

18. The operating method according to claim 11, characterized in that: The operation method also includes: After the usage time of the memory is greater than or equal to the preset time length, the preset refresh period corresponding to at least one preset temperature signal in the mapping table is updated; wherein the updated preset refresh period is less than the preset refresh period corresponding to the at least one preset temperature signal before the update.

19. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 9; A memory controller is coupled to the memory and is configured to control the memory.

20. An electronic device, characterized in that: include: The memory system of claim 19.

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