Package substrate and manufacturing method thereof

Abstract

The invention relates to a package substrate and a manufacturing method thereof. A method for manufacturing a package substrate according to the present invention comprises: a step for generating a glass structure in which a core through-hole, a cavity, or all of the core through-hole and the cavity are formed in a glass core including a first surface and a second surface facing each other; forming an insulating layer on the first surface or the second surface by using an insulating film; and forming an upper layer on an upper portion of the insulating layer, the upper layer including an upper distribution layer and an upper surface connection layer. The step of forming the insulating layer includes: a first curing step of performing first curing on a first insulating film after the first insulating film is laminated on the first surface; and a second curing step in which a second insulating film is laminated on the first insulating film on which the first curing has been performed, and then the second curing is performed on the second insulating film. Therefore, the warping of the packaging substrate can be improved, and the electrical element can be prevented from falling off.

Description

Technical Field

[0001] The present embodiment relates to a semiconductor package substrate and a method for manufacturing the same, and more specifically, to a method for manufacturing a package substrate including a glass core and an insulating layer and related technologies for a package substrate manufactured using the same. Background Art

[0002] In the manufacture of electronic components, the process of realizing circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling wafers into a state that can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] Recently, the four core technologies in the semiconductor industry that enable the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as line widths of nanometer units below microns, more than tens of millions of cells, high-speed operation, and large amounts of heat dissipation, but there is no relatively perfect packaging technology to back it up. Therefore, compared to the performance of semiconductor technology itself, the electrical performance of semiconductors is also determined by packaging technology and its electrical connections.

[0004] Ceramic or resin is currently used as a material for a package substrate. However, research is recently underway to use silicon or glass as a package substrate for high-end use. In particular, a package substrate having a cavity structure is being developed by using a glass core.

[0005] As related prior arts, there are U.S. Patent Publication No. US20220293560A1, Korean Patent Publication No. 10-2018-0142742, etc. Summary of the invention

[0006] Problem that the invention aims to solve

[0007] The purpose of the implementation example is to provide a packaging substrate and a method for manufacturing the same, which can improve the bending phenomenon that may occur due to differences in thermal expansion degrees, stress generated by the differences in thermal expansion degrees, etc. in a packaging substrate using a glass core and an insulating film.

[0008] In addition, an object of an implementation example is to provide a method for manufacturing a package substrate capable of preventing a plurality of electrical components arranged in a cavity portion of a glass core from being separated or falling off, and a package substrate manufactured using the method.

[0009] Means used to solve problems

[0010] In order to achieve the above-mentioned purpose, a method for manufacturing a packaging substrate according to an implementation example includes: a step of generating a glass structure, wherein the glass structure is a structure in which a core through hole or a cavity portion or all of these is generated on a glass core including a first surface and a second surface facing each other; a step of forming an insulating layer on the first surface or the second surface using an insulating film; and a step of forming an upper layer including an upper distribution layer and an upper connection layer on the upper part of the insulating layer.

[0011] The step of forming an insulating layer may include: a first curing step, in which the first insulating film is cured for the first time after being stacked on the first surface; and a second curing step, in which the second insulating film is cured for the second time after being stacked on the first insulating film that has been cured for the first time.

[0012] The cavity has a space for arranging an electrical element, and the space is open toward the first surface or the second surface of the glass core and is formed to be recessed, or is formed to penetrate the first surface and the second surface.

[0013] The method for manufacturing the package substrate may further include a step of arranging the electrical element in the cavity portion.

[0014] In one implementation example, the step of arranging the electrical element in the cavity portion may be performed between the step of generating the glass structure and the step of generating the insulating layer.

[0015] In one implementation example, the first insulating film may be stacked on the entire first surface or the cavity portion where the electrical element is arranged.

[0016] In an implementation example, when the first insulating film is stacked on the cavity portion, the first insulating film may be cut based on the shape and size of the cavity portion.

[0017] In one implementation example, the thickness of the first insulating film and the thickness of the second insulating film may be different from each other.

[0018] In one implementation example, a reduced pressure lamination method may be applied in the first curing step and the second curing step, respectively. The pressure and temperature applied in the second curing step may be higher than the pressure and temperature applied in the first curing step.

[0019] The method for manufacturing the package substrate may further include a final curing step after the second curing step.

[0020] The final curing step is a step of additionally curing the first insulating film and the second insulating film.

[0021] In one implementation example, the electrical component may include a passive component or an active component.

[0022] On the other hand, in order to achieve the above-mentioned purpose, a packaging substrate according to an implementation example includes a core layer and an upper layer located on the core layer, wherein the core layer includes: a glass core, including a first surface and a second surface facing each other; a plurality of core through holes and a cavity portion, which penetrate the glass core in the thickness direction of the glass core; a conductive layer, which is arranged on the surface of the glass core; electrical components, which are arranged in the cavity portion; and an insulating layer, which is used to fill the core through holes and the cavity portion.

[0023] The cavity portion has a space, which is open and recessed toward the first surface or the second surface of the glass core, or is formed by passing through the first surface and the second surface. The insulating layer may include a first insulating layer and a second insulating layer. The first insulating layer is formed by stacking and curing a first insulating film on the first surface, and the second insulating layer is formed by stacking and curing a second insulating film on the first insulating layer.

[0024] In one implementation example, the first insulating layer may be formed on the entire first surface or the cavity portion where the electrical components are arranged.

[0025] In an implementation example, the insulating layer may further include a third insulating layer, and the third insulating layer is formed by laminating and curing the third insulating film on the second surface. The third insulating layer may be recessed on the second surface toward the first surface.

[0026] In one implementation example, a first boundary contacting the first insulating film and the second insulating film may be formed between the first insulating layer and the second insulating layer.

[0027] In one implementation example, a second boundary contacting the first insulating film and the third insulating film may be formed between the first insulating layer and the third insulating layer.

[0028] The second boundary may be formed inside the core through hole and the cavity portion.

[0029] In one implementation example, the color of the first insulating layer and the color of the third insulating layer can be distinguished from each other, that is, can be different from each other.

[0030] In one implementation example, the thickness of the first insulating layer and the thickness of the second insulating layer may be different from each other.

[0031] In one implementation example, the glass core may be a quadrilateral plate-shaped glass.

[0032] In one implementation example, the glass core may have a thickness of 300 μm to 1,500 μm.

[0033] In an implementation example, the height from the bottom surface on which the packaging substrate is placed to the corner of the packaging substrate may be less than 12 mm.

[0034] The electrical components may include passive components or active components.

[0035] Effects of the Invention

[0036] According to the packaging substrate and the manufacturing method thereof of the implementation example, the bending phenomenon is drastically reduced after the insulating layer is formed, thereby significantly improving the yield and quality of the packaging substrate.

[0037] In addition, the curved shape is improved, thereby preventing the electrical components arranged in the cavity portion of the glass core from being separated or falling off. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an implementation example.

[0039] Figure 2 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another implementation example.

[0040] Figure 3 Parts (a) and (b) of FIG. 1 are conceptual diagrams illustrating a portion of a package substrate of each implementation example using a cross section.

[0041] Figure 4 1 is a flow chart for explaining, using a cross section, a process of generating a core distribution layer in a process of manufacturing a package substrate according to an implementation example.

[0042] Figure 5 The flowchart uses a cross section to explain a process of generating an insulating layer in a process of manufacturing a package substrate according to an implementation example.

[0043] Figure 6 It is a diagram for explaining a warping phenomenon that occurs in a package substrate when an insulating layer is formed according to the conventional technology.

[0044] Figure 7 It is a cross-sectional view for explaining the concept of a method for manufacturing a package substrate according to an implementation example.

[0045] Figure 8 It is a flow chart that uses a cross section to illustrate the manufacturing process of a packaging substrate according to an implementation example, P1 refers to a first pre-cure step, P2 refers to a second pre-cure step, L1 is a predicted boundary line 1, and L2 is a predicted boundary line 2.

[0046] Fig. 9A and Fig. 9B are photographs of the boundaries of the insulating layer generated according to the method for manufacturing the package substrate of the implementation example; Fig. 9A The samples are respectively a sample in which a 70 μm thick insulating film is used as a first insulating film, and an insulating film of 60 μm thickness and an insulating film of 80 μm thickness are used as a second insulating film and a third insulating film; Fig. 9B These are samples in which, from the left, a 60 μm-thick insulating film, a 70 μm-thick insulating film, and an 80 μm-thick insulating film are used as the second insulating film.

[0047] Fig.10 The following are photographs for explaining the warpage of a package substrate generated by the method for manufacturing a package substrate according to an implementation example.

[0048] Fig.11 is a flow chart illustrating a process of manufacturing a packaging substrate according to another implementation example.

[0049] Fig.12 is a conceptual diagram illustrating the structure of a packaging substrate according to another implementation example using a cross section.

[0050] Description of Reference Numerals

[0051] 100: Semiconductor device 10: Motherboard

[0052] 30: semiconductor element portion 32: first semiconductor element

[0053] 34: second semiconductor element 36: third semiconductor element

[0054] 20: Package substrate 21, 21a: Glass core

[0055] 22: core layer 223: core insulation layer

[0056] 213: First side 214: Second side

[0057] 23: Core through hole 24: Core distribution layer

[0058] 241: Core distribution pattern 26: Upper layer

[0059] 25: Upper distribution layer 251: Upper distribution pattern

[0060] 252: Blind via 253: Upper insulation layer

[0061] 27: Upper connection layer 271: Upper connection electrode

[0062] 272: Upper connection pattern 28: Cavity

[0063] 281: Internal space 282: Cavity distribution layer

[0064] 40: Electrical components 50: Connecting parts

[0065] 51: Component connection part 52: Board connection part

[0066] 60: Overlay DETAILED DESCRIPTION

[0067] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those with common knowledge in the technical field to which the embodiments belong can easily implement them. However, the present invention can be implemented in various forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are given the same reference numerals.

[0068] Throughout this specification, the term "combination of these" included in the Markush form expression refers to a mixture or combination of one or more selected from the group consisting of the constituent elements described in the Markush form expression, and means that one or more selected from the group consisting of the constituent elements is included.

[0069] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. In addition, unless otherwise clearly defined in the text, singular expressions include plural expressions.

[0070] In the present specification, "~" may refer to a compound containing a compound corresponding to "~" or a derivative of "~".

[0071] In this specification, disposing B on A means disposing B in direct contact with A or disposing B on A with another layer between A and B, and is not limited to disposing B in contact with the surface of A.

[0072] In this specification, connecting B on A means that A and B are directly connected or connected through other components. Unless otherwise specified, it is not limited to the direct connection between A and B.

[0073] In this specification, unless otherwise specified, an expression in the singular number is interpreted as including the singular or plural number explained in the text.

[0074] During the process of developing semiconductor devices that can achieve high performance with greater integration and thinner thickness, the inventors realized that in addition to the components themselves, the packaging part is an important factor in improving performance, and conducted research on this. In the process, they confirmed that unlike existing interposers and organic substrates, which use cores with more than two layers as packaging substrates on a mother board, methods such as using a single-layer glass core and a cavity structure can help make the packaging substrate thinner and improve the electrical characteristics of the semiconductor device.

[0075] During the formation of RDL (Re-Distribution Layer), the curing process of insulating layers such as ABF (Ajinomoto Build-up Film) may cause the package substrate to bend (warp). The inventors determined that the cause of this phenomenon is the difference in thermal expansion (thermal expansion coefficient) between the internal components of the substrate and ABF and the stress caused by heat, and realized the need to improve the warping phenomenon.

[0076] Based on this, after repeated studies, the following was confirmed, and the invention was completed: when generating an insulating layer in the core through hole and cavity structure, the pre-curing (pre-cure) of the insulating film is performed multiple times instead of just once, thereby improving the warpage phenomenon of the glass core caused by the difference in CTE (Coefficient of thermal expansion) between the insulating film and the glass core.

[0077] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an implementation example; Figure 2 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another implementation example; Figure 3 Parts (a) and (b) of FIG. 1 are conceptual diagrams illustrating a portion of a package substrate of each implementation example using a cross section.

[0078] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the implementation example includes: a semiconductor element portion 30, including one or more semiconductor elements 32, 34, 36; a packaging substrate 20, electrically connected to the semiconductor element; a motherboard 10, electrically connected to the packaging substrate 20, and transmitting external electrical signals to the semiconductor elements 32, 34, 36 and connecting them to each other.

[0079] According to an implementation example, the packaging substrate 20 includes: a core layer 22 , an upper layer 26 and a cavity portion 28 . The upper layer 26 is located on a surface of the core layer 22 , and the electrical component 40 may be located in the cavity portion 28 .

[0080] The semiconductor element portion 30 refers to an element mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, computing elements (first element 32, second element 34) such as a CPU, a GPU, etc., memory elements (third element 36) such as a memory chip, etc., can be applied as the semiconductor element portion 30, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0081] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0082] The package substrate 20 may further include a lower layer 38 , which is selectively located below the core layer 22 .

[0083] The core layer 22 may include: a glass core 21, including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212, wherein the second thickness 212 is smaller than the first thickness 211; a plurality of core vias 23, which penetrate the glass core 21 along the thickness direction of the glass substrate 21; a core distribution layer 24, which is located on the surface of the glass core 21 or the core vias 23, and electrically connects the first surface 213 and the second surface 214 of the glass core 21 through the core vias 23, wherein the second surface 214 faces the first surface. That is, the core layer 22 may be referred to as a glass structure including the core vias 23, the cavity 28, or all of these in the glass core 21, wherein the glass core 21 includes the first surface 213 and the second surface 214 facing each other.

[0084] The second region 222 of the core layer 22 may function as a cavity structure.

[0085] In the same region, the glass core 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are substantially parallel to each other, so that the glass core 21 has a predetermined thickness as a whole.

[0086] The internal space 281 is formed by the difference in thickness between the first region 221 and the second region 222 , and serves to accommodate a part or all of the electrical element 40 .

[0087] The glass core 21 may include a core through hole 23, and the core through hole 23 passes through the first surface 213 and the second surface 214. The core through holes 23 may be formed entirely in the first region 221 and the second region 222, and may be formed in a desired pitch and pattern.

[0088] As a packaging substrate for semiconductor devices, the prior art uses a stacked silicon substrate and an organic substrate. In the case of a silicon substrate, due to the semiconductor characteristics, there is a concern about the generation of parasitic elements when applied to high-speed circuits, and there is a disadvantage of relatively large power loss. In addition, in the case of an organic substrate, a larger area is required when forming a more complex distribution pattern, but this does not conform to the manufacturing trend of ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a set size, the pattern actually needs to be refined, but due to the material properties of polymers and other materials used for organic substrates, there are actually limitations in the refinement of the pattern.

[0089] In the implementation example, as a method of solving these problems, the glass core 21 is used as a support body for the core layer 22. In addition, by using the core through hole 23 formed while penetrating the glass core 21 together with the glass core 21, a package substrate 20 having characteristics of further shortening the length of current flow, further miniaturization, faster response and less loss is provided.

[0090] The glass core 21 is preferably made of plate glass suitable for semiconductors, such as borosilicate substrate glass, alkali-free glass substrate, etc., but is not limited thereto.

[0091] The core through hole 23 passes through the glass core 21. The core through hole 23 may be formed by removing a predetermined region of the glass core 21, and specifically, may be formed by etching a plate-shaped glass by a physical and / or chemical method.

[0092] Specifically, in the process of forming the core through hole 23, a defect (miss) may be formed on the surface of the glass core 21 by laser or the like, and then chemical etching, laser etching, etc. may be applied, but the invention is not limited thereto.

[0093] The core through holes 23 may have 100 to 3,000, 100 to 2,500, or 225 to 1,024 per unit area (1 cm x 1 cm) of the glass core 21. When such a spacing condition is satisfied, a conductive layer can be formed and the performance of the package substrate can be improved.

[0094] The core distribution layer 24 includes a core distribution pattern 241 as a conductive layer and a core insulation layer 223, wherein the core distribution pattern 241 is used to electrically connect the first surface 213 and the second surface 214 of the glass core 21 through a through hole, and the core insulation layer 223 surrounds the core distribution pattern 241. The core layer 22 forms a conductive layer through the core through hole 23 inside, thereby playing the role of an electrical channel across the glass core 21, and connecting the upper part and the lower part of the glass core 21 at a relatively short distance, so as to have the characteristics of faster transmission of electrical signals and low loss. For example, the conductive layer can be applied with a copper plating layer, but is not limited thereto.

[0095] The shape of the cavity 28 is actually circular, triangular, quadrilateral, hexagonal, octagonal, cross, etc., and there is no limitation on the shape.

[0096] The electrical component 40 may be substantially in the shape of a cylinder, a rectangular hexahedron, or a polygon.

[0097] The cavity portion 28 may include a cavity distribution pattern as a conductive layer, the cavity distribution pattern electrically connecting the electrical element 40 with the core distribution layer 24 , and an insulating layer surrounding the cavity distribution pattern.

[0098] On the other hand, the cavity portion 28 according to another embodiment may be implemented in a form that penetrates the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion 28 may be formed by the same process as the core through hole 23, and the area and shape of the cavity portion 28 that penetrates the glass core 21 may be different from those of the core through hole 23.

[0099] In this embodiment, the insulating layer may be formed after the electrical element 40 is disposed in the cavity portion 28. That is, the insulating layer may also be formed in the cavity portion 28 through the process of forming the core insulating layer 223 described above.

[0100] The core allocation pattern 241 may be formed with a pattern to be electrically connected with the electrical element 40 .

[0101] The electrical element 40 may include an active element such as a transistor or a power transmission element such as a multi-layer ceramic capacitor (MLCC), that is, a passive element.

[0102] When an element such as a transistor that converts an electrical signal between a motherboard and a semiconductor element portion into an appropriate level is used as the electrical element 40, a transistor is applied to a path of the packaging substrate 20, thereby providing a more efficient and faster semiconductor device 100.

[0103] In addition, power transmission elements such as multilayer ceramic capacitors (MLCC) play an important role in the performance of semiconductor elements. Power transmission elements as passive elements are usually used in semiconductor elements at least 200, and the characteristics of the conductive layer around the element in terms of power transmission are also affected by the performance. In one implementation example, a core through hole of a non-circular shape can be used with such a power transmission element in the part where the conductive layer needs low resistance.

[0104] On the other hand, passive components such as capacitors can be individually inserted and applied to the electrical component 40, and a component group including a plurality of passive components can also be formed in a manner of exposing electrodes in a form embedded in an insulator layer (cavity insulating layer) and then inserted into the electrical component. In the latter case, the operability of manufacturing the package substrate can be made smoother, and it is more conducive to positioning the insulating layer in the space between complex components with high reliability.

[0105] The glass core 21 plays an intermediate role and a mediating role in connecting the semiconductor element part 30 and the motherboard 10 at the upper and lower parts thereof, respectively, and the core through hole 23 plays a role as a channel for transmitting these electrical signals, thereby realizing smooth transmission of signals.

[0106] The upper layer 26 is arranged on the first surface 213 .

[0107] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27. The upper connection layer 27 is located on the upper distribution layer 25. The uppermost surface of the upper layer 26 can be protected by a covering layer 60, and an opening portion is formed in the covering layer 60 that can directly contact the connection electrode of the semiconductor element portion.

[0108] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface 213 ; an upper distribution pattern 251 , which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24 and is built into the upper insulating layer 253 .

[0109] The upper insulating layer 253 may be any material as long as it is used as an insulating layer in a semiconductor element or a package substrate, and for example, an epoxy resin containing a filler may be used, but the present invention is not limited thereto.

[0110] The insulator layer may be formed by forming a coating and curing the coating, or by laminating an uncured or semi-cured thin film of the insulator on the core layer 22 and curing the thin film. In this case, if a reduced pressure lamination method is used, the insulator is embedded in the space inside the core through hole 23, and the process can be performed efficiently.

[0111] According to an implementation example, even if multiple insulating layers are stacked and applied, it may be difficult to distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may use the same insulating material. In this case, the boundary may be substantially indistinguishable. Alternatively, according to another implementation example, the boundary of the insulating layer may be generated by setting the pressure and temperature used to cure the multiple insulating layers to be different.

[0112] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined form, and can be formed, for example, by a build-up layer method. Specifically, an insulating layer is formed, and after removing unnecessary portions of the insulating layer, a conductive layer is formed by copper plating or the like, and after selectively removing unnecessary portions of the conductive layer, an insulating layer is re-formed on the conductive layer, and after re-removing the unnecessary portions, a conductive layer is formed by gold plating or the like, and this method is repeated to form the upper distribution pattern 251 in which the conductive layer is formed in a desired pattern in a vertical or horizontal direction.

[0113] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, in order to smoothly transmit electrical signals with the semiconductor element portion 30 and to fully accommodate the desired complex pattern, at least a portion of the upper distribution pattern 251 includes a fine pattern. In this case, the fine pattern refers to a width and a pitch that can be less than 4 μm, less than 3.5 μm, less than 3 μm, less than 2.5 μm, or 1 μm to 2.3 μm (hereinafter, the same applies to the description of the fine pattern).

[0114] The upper connection layer 27 includes an upper connection pattern 272 and an upper connection electrode 271. At least a portion of the upper connection pattern 272 is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253. The upper connection electrode 271 electrically connects the semiconductor element portion 30 to the upper connection pattern 272. The upper connection pattern 272 may also be located on a surface of the upper insulating layer 253, and at least a portion thereof is exposed on the upper insulating layer and embedded in the upper insulating layer 253. For example, in the case where the upper connection pattern 272 is located on a surface of the upper insulating layer 253, the upper insulating layer 253 may be formed by gold plating or the like; in the case where a portion of the upper connection pattern 272 is exposed on the upper insulating layer 253 and embedded in the upper insulating layer 253, a portion of the insulating layer or the conductive layer may be removed by surface grinding, surface etching, or the like after forming a copper plating layer or the like.

[0115] At least a portion of the upper connection pattern 272 may include a fine pattern together with the upper distribution pattern 251 described above. In this way, the upper connection pattern 272 including the fine pattern can electrically connect more components even in a narrow area, thereby making it possible to more smoothly perform electrical signal connection between components or with the outside, thereby achieving a more integrated package.

[0116] The upper surface connection electrode 271 and the semiconductor element portion 30 may be directly connected via a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball.

[0117] The cavity portion 28 includes a cavity distribution layer 282 and an inner space 281 . The cavity portion 28 is located above and / or below the second region 222 and is electrically connected to the core distribution pattern 241 . The electrical element 40 is disposed in the inner space 281 .

[0118] Specifically, the thickness of the glass core 21 in the second region 222 is smaller than that in the first region 221, and the electrical element 40 can be located in the inner space 281 formed by the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass core 21 function as an electrical connection structure for connecting the electrical element 40 to external elements.

[0119] In addition, as described above, a cavity portion penetrating the first region 221 but not the second region 222 , that is, the first surface 213 and the second surface 214 of the OM glass core 1 can be generated, and the electrical element 40 can be arranged in the cavity portion.

[0120] The package substrate 20 is also connected to the motherboard 10. The motherboard 10 can directly connect the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 with the terminal of the motherboard 10, or can be electrically connected through a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 in contact with the motherboard 10 can also be connected to the motherboard 10 through a lower layer 38 located at the lower part of the core layer 22.

[0121] According to an example, in addition to the glass core 21 , other additional substrates may be substantially applied to the package substrate 20 located between the semiconductor device portion 30 and the motherboard 10 .

[0122] In the past, an interposer and an organic substrate were stacked together and used between the connecting element and the motherboard. It is understood that this multi-level form is applicable for at least two reasons, one of which is that there are scale issues when directly bonding the fine pattern of the element to the motherboard, and the other reason is that during the bonding process or the driving process of the semiconductor device, the wiring may be damaged due to the difference in thermal expansion coefficient. In the implementation example, a glass core with a thermal expansion coefficient similar to that of the semiconductor element is applied, and a fine pattern with a small scale sufficient to mount the element is formed on the first surface of the glass core and its upper layer to solve these problems.

[0123] Hereinafter, a method for manufacturing a package substrate according to an implementation example of the present invention will be described.

[0124] Figure 4 and Figure 5 This is a flow chart illustrating a manufacturing process of a package substrate according to an implementation example using a cross section.

[0125] First, if Figure 4 As shown in part (a), a glass core 21a having a flat first surface and a flat second surface is prepared, and a defect (loss) 21b is formed on the glass surface at a predetermined position in order to form a core through hole. The glass can be a glass core suitable for a substrate of an electronic device, for example, an alkali-free glass core, but is not limited thereto. As commercial products, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. In the process of forming the defect (loss), mechanical etching, laser irradiation, etc. can be used.

[0126] like Figure 4 As shown in part (b) of FIG. 1 , an etching step is performed on the glass core 21a having the defect 21b to form the core through hole 23 by a physical or chemical etching process. During the etching process, a through hole is formed in the defective portion of the glass core 21a, and the surface of the glass core 21a may also be etched. In order to prevent such etching of the glass surface, a masking film or the like may be applied. However, considering the trouble of removing the masking film after application, the glass core itself having the defect may be etched. In this case, the thickness of the glass core having the core through hole may be somewhat smaller than the thickness of the initial glass core.

[0127] After this, if Figure 4 As shown in parts (c) and (d) of FIG. 2 , a conductive layer 21d is formed on the glass core 21a, and then a core layer manufacturing step can be performed. As the conductive layer, a metal layer including copper metal can be used as a representative, but it is not limited thereto.

[0128] The surface properties of the glass (including the surface of the glass core and the surface of the core through hole) are different from those of the copper metal, so the adhesion is low. In the implementation example, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0129] The dry method is a method suitable for sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by sputtering a metal. In the process of forming the seed layer 21c, different types of metals such as titanium, chromium, and nickel can be sputtered together with copper. In this case, the glass-metal adhesion can be improved by the anchoring effect of the interaction between the surface morphology of the glass and the metal particles.

[0130] Wet mode is the mode of primer treatment, is to utilize the compound substance with the functional group of amine etc. to carry out pretreatment, forms the mode of primer coating 21c thus.According to the degree of desired adhesion, utilize silane coupling agent to carry out pretreatment, can utilize compound or particle with amine functional group to carry out primer treatment afterwards.As mentioned above, the support substrate of realization example needs to have the high performance of the degree that can be enough to form fine pattern, and also should keep this high performance after primer treatment.Accordingly, when this primer comprises nanoparticle, preferably be applicable to the nanoparticle of the size below 150nm with average diameter, for example, the particle with amine group is preferably applicable to nanoparticle.Give an example, the bonding strength improver of the applicable CZ series etc. of MEC company is formed.

[0131] For the seed layer / undercoat layer 21c, the conductive layer can selectively form a metal layer to be in a state where the conductive layer is removed or not removed. In addition, for the seed layer / undercoat layer 21c, the part that needs or does not need to form a conductive layer can be selectively processed into an activated or inactivated state in the gold plating, and then the subsequent process can be carried out. For example, the activation or inactivation treatment can be treated with light irradiation treatment of a predetermined wavelength, chemical treatment, etc. The formation of the metal layer can use the copper plating method used in the manufacture of semiconductor elements, but is not limited to this.

[0132] like Figure 4 As shown in part (e), a portion of the core distribution layer can be removed when the portion is not needed, and gold plating is performed after a portion of the seed layer is removed or inactivated, thereby forming a conductive layer in a predetermined pattern, thereby also forming an etching layer 21e of the core distribution layer.

[0133] Figure 5 The manufacturing steps of forming an insulating layer and an upper distribution pattern are described according to an implementation example.

[0134] like Figure 5As shown in part (a) of the embodiment of the present invention, the core through hole may be subjected to an insulating layer forming step, in which the hollow space is filled with an insulating layer after forming a core distribution layer as the conductive layer. At this time, the applicable insulating layer may be an insulating layer manufactured in the form of a thin film, for example, a method of laminating an insulating layer in the form of a thin film by reduced pressure, etc. If reduced pressure lamination is performed in this way, the insulating layer is fully embedded in the hollow space inside the core through hole, and the core insulating layer can be formed without gaps.

[0135] exist Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer manufacturing steps.

[0136] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming an insulating layer 23a or a laminated insulating film (film), and it is preferable to simply use a laminated insulating film. The lamination of the insulating film can be carried out by laminating the insulating film and curing the insulating film. At this time, if a reduced pressure lamination method is adopted, the insulating resin can also be fully immersed in the layer where the conductive layer is not formed inside the core through hole. The upper insulating layer is also directly in contact with the glass core in at least a portion, so it is suitable to have a layer with sufficient adhesion. Specifically, the glass core and the upper insulating layer preferably have a characteristic of an adhesion test value of more than 4B according to ASTMD3359 test.

[0137] The upper distribution pattern is formed by repeatedly forming the insulating layer 23a and forming the conductive layer 23c in a predetermined pattern and then etching the unnecessary part to form the etching layer 23d of the conductive layer. In the case of conductive layers formed adjacent to each other with the insulating layer in between, the blind through hole 23b can be formed in the insulating layer and then subjected to a gold plating process. The blind through hole 23b can be formed by dry etching such as laser etching and plasma etching, and wet etching using a mask layer and an etching solution.

[0138] After that, although not shown, an upper connection layer and a cover layer may be formed.

[0139] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the formation of the upper distribution layer. Specifically, the upper connection pattern and the upper connection electrode can be formed by forming an etching layer of the insulating layer on the insulating layer 23e and then forming an etching layer of the conductive layer thereon, but it is also possible not to use the etching method, but to use a method of selectively forming only the conductive layer. The covering layer can be formed to form an opening (not shown) at a position corresponding to the upper connection electrode to expose the upper connection electrode, and can be directly connected to the element connection part or the terminal of the element.

[0140] If the upper layer is generated, the lower connection layer and the covering layer are formed, and the process of forming the lower layer can be performed. The lower distribution layer and / or the lower connection layer can be formed in a similar manner to the upper connection layer and the covering layer formation steps described above, and the covering layer (not shown) can be selectively formed.

[0141] Figure 6 It is a diagram for explaining a warping phenomenon that occurs in a package substrate when an insulating layer is formed according to the conventional technology.

[0142] The electrical components can be formed to be inserted into the insulating layer. This is called embedding. At this time, if a thick insulating film, such as ABF (Ajinomoto Build-up Film), is used to fill the remaining space after the electrical components are placed in the cavity, that is, the cavity area, after curing, the electrical components are placed in the cavity area. Figure 6 As shown, asymmetric shrinkage may occur on one surface of the substrate.

[0143] The step for curing the insulating layer may include a pre-curing step in which the insulating film or the like is not completely cured but is preliminarily cured, and a curing step in which the insulating film or the like is additionally completely cured.

[0144] When performing the pre-curing step, a large shrinkage force may occur in a specific direction due to chemical reactions between the insulating film of ABF and the components within the insulating film, CTE (Coefficient of thermal expansion) deviation of the glass core, residual thermal stress, etc., and warping (WARPAGE; bending phenomenon) may occur due to the stress generated at this time.

[0145] like Figure 6 As shown, the glass core is formed into a convex shape due to bending in the direction of the insulating film, so defects in the packaging substrate may occur. As described later, the manufacturing process of the packaging substrate is as follows. The position of the electrical component is fixed by an adhesive film in the through-type cavity, and then the insulating film is placed on the surface facing the adhesive film. Then, pre-curing is performed together with reduced pressure lamination, and the adhesive film is removed for subsequent steps. At this time, shrinkage force is easily generated in the insulating layer due to the stress remaining in the insulating layer, and bending occurs in the glass core due to various reasons including this reason.

[0146] In this case, the component arranged in the cavity region may be detached, moved or separated from the original position. In addition, in the case of pre-curing, the insulating film is not completely cured, so the separation of the component may occur relatively easily.

[0147] Warp (warpage) is to place the package substrate (or glass core) on a flat surface (bottom), and measure the height of the corner of the package substrate (or glass core) from the bottom plane on which it is placed. Figure 6 As shown, due to the shrinkage caused by the pre-curing, a vertex of the package substrate (or glass core) is separated from the bottom plane by nearly 20 mm, about 2 cm, which may play a fatal role in the production of the package substrate.

[0148] According to the package substrate of the implementation example, the height of the corners can be less than 12 mm. Figure 6 The example of the distance of about 2 cm is an excellent characteristic.

[0149] The package substrate of the implementation example is placed on a flat plane, and the height of the corner of the package substrate from the plane on which it is placed can be less than 10 mm, less than 8 mm, less than 6 mm, or less than 4 mm. The height of the separation can be more than 0 mm or more than 1 mm. For such a package substrate, the degree of bending is relatively small, thereby enabling a stable manufacturing process of the package substrate and reducing the defective rate.

[0150] For the height separated by the corners, the package substrate is placed on a flat plane, and the height of the corner separated from the plane on which it is placed is measured without applying any additional external force. For example, the maximum value is taken from the four corners of the quadrilateral package substrate and the height separated by the corners is calculated.

[0151] Accordingly, according to an implementation example of the present invention, it is proposed to perform the pre-curing process of the insulating film multiple times instead of just once.

[0152] Figure 7 It is a cross-sectional view for explaining the concept of a method for manufacturing a package substrate according to an implementation example.

[0153] Figure 7 The package substrate in the figure is a conceptually simplified diagram for explaining the formation of the insulating layer. Figures 1 to 3 The content of the description.

[0154] according to Figure 7 The cavity 29 is formed by penetrating the first surface and the second surface of the glass core 21, and an electrical element 40 is arranged inside the cavity 29. The cavity 29 can be formed simultaneously with the core through hole through the same formation step, or can be formed independently after or before the core through hole is formed.

[0155] and Figure 7Differently, the cavity portion 29 can be formed in a form that only opens and recesses the surface of any one of the first surface or the second surface. In this case, the cavity portion 29 can also be formed simultaneously with the core through hole through the same forming step, or can be formed independently after forming the core through hole or before forming the core through hole.

[0156] As described above, electrical components 40 may include passive components and / or active components.

[0157] like Figure 7 As shown, in order to fill the core through hole and cavity 29 of the glass core 21 used to constitute the core layer, a relatively thinner insulating film is used instead of the previous thicker insulating film, and the insulating layer can be generated on at least one surface of the glass core through more than two steps of processing.

[0158] That is, the insulating film is stacked two or more times and pre-cured after each deposition. This minimizes warpage and substantially prevents the electrical element from being detached from the substrate.

[0159] Specifically, the first insulating film 61 (including the case where components of the insulating film are embedded in the hole or cavity space by applying reduced pressure lamination) can be laminated and cured from the first surface toward the second surface, thereby generating the first insulating layer.

[0160] Then, a second insulating layer formed by laminating and curing the second insulating film 63 may be formed on the first insulating layer. At the same time or by another process, a third insulating layer formed by laminating and curing the third insulating film 64 from the second surface toward the first surface is generated.

[0161] That is, a first insulating layer can be formed by laminating a first insulating film and a first curing step (pre-cure), and a second insulating layer can be formed on the upper part of the glass core (on the upper part of the first insulating layer) by laminating a second insulating film and a second curing step (pre-cure).

[0162] Furthermore, in the second curing step, not only is the second insulating layer laminated on the upper part of the glass core (the upper part of the first insulating layer), but the second insulating layer and the third insulating layer can also be formed simultaneously on the lower part (the second surface) of the glass core by laminating the third insulating film and the second curing step (pre-cure). In this case, the third insulating film can be applied in the same manner as the second insulating film. Furthermore, in this case, curing can be performed simultaneously on both sides of the glass core to disperse the generation of stress, and it can be more conducive to suppressing the occurrence of bending.

[0163] As described above, through the two-step pre-curing process, the insulating layer is stably formed inside the core through hole and the cavity portion 29, and the bending phenomenon of the substrate can be improved or substantially improved.

[0164] Figure 8 This is a flow chart illustrating a manufacturing process of a package substrate according to an implementation example using a cross section.

[0165] pass Figure 8 , the steps for forming an insulating layer on a packaging substrate are described in more detail as follows.

[0166] First, if Figure 8 As shown in part (a) of FIG. 1 , the glass core 21 is attached to an adhesive film 80 such as a PI tape (polyimide tape), and the electric component 40 is selected and arranged in the cavity portion 29 (the position of the electric component is specified).

[0167] After this, if Figure 8 As shown in part (b) of FIG. 1 , the first lamination process (1st Lamination on top; first lamination on top) can be performed on the first surface. If the first insulating film 61 is completely laminated on the first surface of the glass core 21 and a first pre-cure step (1st Pre-cure; first pre-cure) is performed on it, then Figure 8 As shown in part (c) of FIG. 2 , the first insulating layer can embed the insulator into the inner space of the cavity portion 29 .

[0168] The adhesive film 80 can be removed in a subsequent process as required. For example, the adhesive film 80 can use an adhesive film whose adhesive force can be reduced by irradiation with ultraviolet rays. For the adhesive film 80, the adhesive force of the adhesive film 80 can be reduced by irradiating the adhesive film directly or through the glass core with ultraviolet rays, so that the adhesive film can be easily removed from the glass core.

[0169] Furthermore, the electrical component 40 can be fixed in position by first curing the first insulating layer that has been cured in advance. If the degree of bending is controlled below a predetermined level, subsequent processes can be applied without the adhesive film 80 for fixation.

[0170] If the first insulating layer is generated, Figure 8 As shown in part (c), a second curing step (2nd Lamination on top & bottom; second lamination on the top or bottom) can be performed, and a second curing (2nd Pre-cure; second pre-cure) is performed after the first insulating film 61 and / or the second insulating film 63 are respectively stacked on the second surface after the first curing.

[0171] If the second curing is completed, Figure 8 As shown in part (d) of , an insulating layer distinguished by the boundary between insulating films can be generated. That is, the insulating layer may include a first insulating layer and a second insulating layer, the first insulating layer is formed by stacking and curing the first insulating film 61 on the first surface toward the second surface, and the second insulating layer is formed by stacking and curing the second insulating film 63 on the first insulating layer. Optionally, a third insulating layer may also be included, the third insulating layer is formed by stacking and curing the third insulating film 64 on the second surface toward the first surface. Between the first insulating layer and the second insulating layer, a predicted boundary L1 where the first insulating film 61 and the second insulating film 63 are in contact can be formed; between the first insulating layer and the third insulating layer, a predicted boundary L2 where the first insulating film 61 and the third insulating film 64 are in contact can be formed.

[0172] According to an example, the thickness of the first insulating film 61 applied to the first curing and the thickness of the second insulating film 63 applied to the second curing may be different from each other.

[0173] The first insulating film 61 and the second insulating film 63 may have a thickness ratio of 1:0.5 to 2 or a thickness ratio of 1:0.6 to 1.5. For example, when the total thickness of the first insulating film 61 and the second insulating film 63 is 80um, the thickness ratio of the first insulating film 61 / the second insulating film 63 may be in the range of 30 / 50, 50 / 30 or 40 / 40; when the total thickness of the first insulating film 61 and the second insulating film 63 is 60um, the thickness ratio of the first insulating film 61 / the second insulating film 63 may be in the range of 30 / 30, 20 / 40 or 40 / 20. Alternatively, when the total thickness of the first insulating film 61 and the second insulating film 63 is 30um, the thickness ratio of the first insulating film 61 / the second insulating film 63 may be in the range of 15 / 15, 10 / 20 or 20 / 10.

[0174] Of course, the pre-curing step may be performed more than twice. According to the size of the cavity 29 and the height of the glass core 21, the thickness of the insulating film and the number of curing times may be set to be optimal.

[0175] Insulating films such as ABF can be thermally cured by applying heat.

[0176] Specifically, for the insulating film, a portion of the insulating film components is guided to be arranged inside the through hole, cavity, etc. by reduced pressure lamination, and then pre-cured by thermal curing. At this time, pre-curing does not mean that the insulating film is completely cured, but refers to the degree of curing to an intermediate step, and the curing can be controlled by adjusting the curing temperature, etc.

[0177] The temperature and pressure during the first curing and the second curing are different. The pressure and temperature applied during the second curing step are higher than the pressure and temperature applied during the first curing step.

[0178] The first curing step may be performed at a first curing temperature of 60°C to 145°C.

[0179] The first curing temperature may be 60° C. or above or 65° C. or above. The first curing temperature may be 145° C. or below, 140° C. or below, 130° C. or below, 120° C. or below, 110° C. or below, 100° C. or below, or 90° C. or below. In this case, the insulating layer is not completely cured but cured at a pre-cured level.

[0180] The first curing step can be performed at 15kgf / cm 2 Below, 12kgf / cm 2 Below or 10kgf / cm 2 The process is carried out under the following reduced pressure conditions, wherein the reduced pressure conditions may also be 2 kgf / cm 2 Above or 5kgf / cm 2 above.

[0181] The second curing step may be performed at a second curing temperature of 120°C to 180°C.

[0182] The second curing temperature may be 120° C. or higher, 130° C. or higher, 140° C. or higher, 150° C. or higher, or 160° C. or higher. The second curing temperature may be 180° C. or lower, 170° C. or lower, or 165° C. or lower. In this case, the insulating layer is not completely cured but can be cured at a pre-cured level.

[0183] The second curing step can be at 22kgf / cm 2 Below, 20kgf / cm 2 Below or 18kgf / cm 2 The pressure reduction conditions may also be 10 kgf / cm 2 Above or 13kgf / cm 2 above.

[0184] The curing temperature of the first curing step may be higher than the curing temperature of the second curing step.

[0185] The temperature rise to the first curing temperature may be performed for 20 minutes to 120 minutes, and may be performed for 20 minutes to 80 minutes. The first curing temperature may be maintained for 20 minutes to 120 minutes, and may be maintained for 20 minutes to 80 minutes.

[0186] The temperature rise to the secondary curing temperature may be performed for 20 minutes to 100 minutes, and may be performed for 20 minutes to 80 minutes. The secondary curing temperature may be maintained for 20 minutes to 100 minutes, and may be maintained for 20 minutes to 80 minutes.

[0187] When curing is performed separately under such temperature and pressure conditions, a pre-cured or cured insulating layer can be obtained at a desired level.

[0188] If a pre-curing step such as a first curing and / or a second curing is performed, a final curing step for completely curing the insulating film may be additionally performed. A step for flattening the surface of the substrate may be performed between the pre-curing and the curing process. That is, the upper surface of the insulating layer may be flattened. For example, a method for placing a flattening film (e.g., a PET film) on the insulating layer may be used during the decompression lamination process. However, the flattening method is not limited thereto.

[0189] According to an example, such planarization may also be performed between the first curing and the second curing described above.

[0190] On the other hand, referring to Figure 8 It is obvious to those skilled in the art that the aforementioned pre-curing step of the insulating film can also be applied to a cavity portion that is open in one direction of the first surface or the second surface of the glass core 21 .

[0191] Fig. 9A and Fig. 9B The following are photographs showing the boundaries of insulating layers generated by manufacturing a package substrate according to various implementation examples using a microscope.

[0192] If you pass Figure 8 The process forms Fig. 9A or Fig. 9B That is, a first boundary L1 where the first insulating film 61 and the second insulating film 63 are in contact is formed between the first insulating layer and the second insulating layer, and a second boundary L2 where the first insulating film 61 and the third insulating film 64 are in contact is formed between the second insulating layer and the third insulating layer.

[0193] Fig. 9B L2 represents a second boundary (a line between two types of materials) formed between the second insulating layer 63 and the third insulating layer 64 in the cavity 29. This boundary is observed because the insulating layer is generated through multiple curing steps rather than a single curing step, and different temperatures and pressures are applied during curing.

[0194] For example, for the boundary, it can be observed that the boundary of the color difference is a line.

[0195] For example, for the boundary, a stripe shape with relatively constant color, constant thickness and color change (for example, a color change such as a gradient) can be observed. For example, the predetermined interval can be 2 μm to 30 μm, or 3 μm to 10 μm.

[0196] In addition, the colors of the insulating layers may be distinguished in the boundary, for example, the color of the first insulating layer and the color of the third insulating layer may be distinguished from each other.

[0197] like Fig. 9A and Fig. 9B As shown, the thickness of the first insulating film 61 may be 60 μm, 70 μm, or 80 μm, and the formation position of the second boundary may be different according to the thickness of the first insulating film 61 .

[0198] Fig.10 The following are photographs for explaining the warpage of a package substrate generated by the method for manufacturing a package substrate according to an implementation example.

[0199] As described above, the warpage can be measured as the average height of the corner of the glass core from the bottom plane where the package substrate or the glass core is placed. Fig.10 FIG. 4 shows the warpage when the curing process is divided into multiple steps and performed on the insulating film according to the implementation example of the present invention.

[0200] The glass core may have a quadrilateral shape (according to an implementation example, the width and length of the glass core are about 53 cm), and according to an example, its thickness may be 400 μm to 600 μm. In the case where a plurality of steps are divided for the glass core in this condition and a curing process for the insulating film is performed, as shown in FIG. Fig.10 As shown, a vertex of the glass core is spaced less than 0.1 mm from the bottom plane.

[0201] In with Figure 6 When compared, the degree of improvement in this warpage is very large, and it can be evaluated that the warpage has almost disappeared.

[0202] Fig.11 is a flow chart illustrating a process of manufacturing a packaging substrate according to another implementation example.

[0203] As shown in the figure, Fig.11 The cavity portion 29 in the glass core 21 also has a structure that penetrates the first surface and the second surface of the glass core 21, and as an example, a capacitor 41 is arranged as an electrical element.

[0204] As described above, in addition to passive elements such as the capacitor 41 , active elements may be disposed in the cavity portion 29 as electrical elements.

[0205] like Fig.11 As shown in part (a) of FIG. 2 , an adhesive film 80 such as a PI tape is attached to the glass core 21 , and an electric element such as a capacitor 41 is arranged in the cavity portion 29 .

[0206] According to the present implementation example, the first insulating film may be laminated and cured on the cavity portion 29 of the first surface where the capacitor 41 is arranged or on a region including the cavity portion 29 , rather than on the entire first surface.

[0207] That is, according to Fig.11 The first insulating layer 61a formed on the package substrate is not formed on the entire surface of the upper portion of the glass core 21, but is formed to fill all or part of the blank area of ​​the core through hole and / or the cavity portion 29. In this case, the first insulating layer 61a can function as an insulating layer surrounding the electrical element such as the capacitor 41.

[0208] In this case, the first insulating film may be cut based on the shape and size of the cavity 29 and stacked on the upper portion of the cavity 29. For example, the shape of the cut first insulating film may be substantially the same as or similar to the shape of the cavity 29 when viewed from above.

[0209] The size (width) of the first insulating film can be adjusted to be larger or smaller and suitable, taking into account the volume of the insulating layer to be embedded in the cavity 29, the thickness of the insulating layer, etc. For example, the size of the first insulating film can be slightly smaller than the size of the opening shape of the cavity 29, and the thickness can be slightly smaller than the thickness of the cavity 29.

[0210] Accordingly, unnecessary insulating portion formation is minimized in the region other than the cavity portion 29, while a sufficient amount of insulating material can be embedded in the cavity portion. Furthermore, surface undulation that may occur between a plurality of electronic components and / or between an electronic component and the cavity can be minimized, and a substantially flat surface of the insulating layer can be obtained.

[0211] As described above, the step of forming the insulating layer can be performed at different times according to the thickness of the glass core 21, the thickness of the insulating film, or the size and properties of the electrical component. On this basis, the region of the insulating layer as the object of the first curing can also be deformed into various structures according to the arrangement of the cavity portion 29, the size and properties of the electrical component.

[0212] If the first insulating layer 61a is formed, Figure 8As shown in part (c), the second insulating film is stacked on the entire first surface and second surface of the glass core 21, and the second curing can be performed.

[0213] After performing the second curing, Fig.11 As shown in part (c) of FIG. 1 , a second insulating layer 63a that completely surrounds the glass core 21 and the first insulating layer 61a can be formed.

[0214] Fig.12 is a conceptual diagram illustrating the structure of a packaging substrate according to another implementation example using a cross section.

[0215] As shown in the figure, the package substrate may include: a core layer, i.e., a glass structure, wherein the glass structure is a structure having a core through hole 23, a cavity 29, and an electrical component 40 disposed in the cavity 29 in a glass core 21; an upper layer 26, located in the upper part of the core layer; and a lower layer 38, located in the lower part of the core layer. A cover layer 60 is formed on the upper layer 26 and the lower layer 38. The number of electrical components 40 is not specified, and two electrical components 40 are shown in this implementation example.

[0216] A core distribution pattern 241 is formed on the surface of the core through hole 23 and the cavity portion 29. The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the organic substrate 21. In addition, an element conductive layer 42 for electrically connecting the electrical element 40 to the upper distribution pattern 251 of the upper layer 26 is formed on a portion of the upper surface, the side surface, and a portion of the lower surface of the electrical element 40.

[0217] On the other hand, as shown in the figure, the first insulating layer 61a fills the space between the two electrical components 40 and the inner space of the cavity. Fig.12 The package substrate is compared with the reference Fig.11 The first insulating layer 61a is similar to the first insulating layer described above, and is formed only in a limited area that can cover the cavity portion, rather than the entire first surface of the glass core 21. In addition, the first insulating layer 61a may not be stacked on the upper surface of the cavity portion 29, but may fill the side surface of the cavity portion 29, that is, fill the empty space in the area where the electrical components 40 are arranged.

[0218] According to an implementation example, the electrical element 40 may be a capacitor. When the capacitor is disposed in the cavity 29 penetrating the glass core 21, a surface of the capacitor other than the upper or lower surface of the two side surfaces may be connected to the upper distribution pattern 251. Fig.12 As shown, the two electrodes 42a and 42b of the capacitor can be electrically connected to the upper distribution pattern 251 formed on the upper layer 26, and the current flows into the first electrode 42a and flows to the outside through the second electrode 42b. The electrodes 42a and 42b can also be formed as part of the element conductive layer 42, and can also be formed in stages through a separate lamination process.

[0219] Of course, the two electrodes 42 a and 42 b of the capacitor may be formed in a direction of being the second surface which is the lower surface of the glass core 21 instead of being the first surface which is the upper surface.

[0220] The element conductive layer 42 is formed on the electrical element 40, and the first insulating layer 61a surrounding the element conductive layer 42 is formed, and then the second insulating layer 63a can be formed on the first insulating layer 61a and the upper and lower parts of the glass core 21. That is, instead of using the conventional method of filling the cavity area at one time, a relatively thin insulating film is used instead of the conventional thick insulating film to fill the cavity 29, and an insulating layer can be generated on at least one surface of the glass core through a process of two or more steps. That is, the insulating film is stacked twice or more, and solidified before and after each stacking. Accordingly, warping is minimized and the electrical element can be prevented from detaching from the substrate.

[0221] The upper layer 26 is formed on the upper portion of the second insulating layer 63a formed on the first surface. The upper layer 26 may include an upper insulating layer 253 and an upper distribution pattern 251, wherein the upper distribution pattern 251 is a conductive layer having a predetermined pattern and at least a portion thereof is electrically connected to the core distribution pattern 241 and the two electrodes 42a, 42b of the element conductive layer 42, and is embedded in the upper insulating layer 253.

[0222] The same insulating material may be used for the second insulating layer 63a and the upper insulating layer 253. In this case, it may be difficult to distinguish their boundaries in the cross section. Alternatively, according to another implementation example, the pressure and temperature used to cure the multi-layer insulator are set to be different, so that the boundaries can be relatively easily distinguished from the cross section of the insulator.

[0223] The second insulating layer 63a and the upper insulating layer 253 may be made of different insulating materials. In this case, the boundary between the insulating layers can be more easily distinguished.

[0224] In addition, as described above, the upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined form, and can be formed by, for example, a build-up layer. According to the manufacturing method of the package substrate of the embodiment described above and the package substrate manufactured by the manufacturing method, the bending phenomenon caused by the difference in the degree of thermal expansion of the substrate components can be improved, and the electrical components can be prevented from being separated or falling off from the substrate.

[0225] The present invention as described above is described with reference to the embodiments shown in the accompanying drawings, but this is only exemplary, and anyone with ordinary knowledge in the relevant technical field can understand that various modifications and variations of the embodiments can be made therefrom. That is, the scope of rights of the present invention is not limited to the above-mentioned embodiments, and various modifications and improved forms of practitioners using the basic concepts of the embodiments defined by the claims are also included in the scope of rights of the embodiments. Therefore, the true technical protection scope of the present invention should be defined by the technical ideas of the claims.

Claims

1. A method for manufacturing a packaging substrate, characterized in that: include: a step of generating a glass structure, wherein the glass structure is a structure in which a core through hole or a cavity portion or all of these is generated in a glass core including a first surface and a second surface facing each other, forming an insulating layer on the first surface or the second surface using an insulating film, and A step of forming an upper layer including an upper distribution layer and an upper connection layer on the upper portion of the insulating layer; The steps of forming the insulating layer include: a first curing step of curing the first insulating film after laminating the first insulating film on the first surface, and The second curing step is to perform a second curing on the second insulating film after stacking the second insulating film on the first insulating film that has been subjected to the first curing.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: The cavity has a space for arranging an electrical element, and the space is open in the direction of the first surface or the second surface of the glass core and is formed in a concave shape, or is formed through the first surface and the second surface. The method for manufacturing the package substrate further includes the step of arranging the electrical components in the cavity portion. The step of arranging the electrical element in the cavity is performed between the step of generating the glass structure and the step of forming the insulating layer. The first insulating film is stacked on the entire first surface or the cavity portion where the electrical element is arranged.

3. The method for manufacturing a packaging substrate according to claim 2, wherein: In a case where the first insulating film is stacked on the cavity portion, the first insulating film is cut based on the shape and size of the cavity portion.

4. The method for manufacturing a packaging substrate according to claim 1, wherein: The thickness of the first insulating film and the thickness of the second insulating film are different from each other.

5. The method for manufacturing a packaging substrate according to claim 1, wherein: In the first curing step and the second curing step, a reduced pressure lamination method is applied respectively, The pressure and temperature applied in the second curing step are higher than the pressure and temperature applied in the first curing step.

6. The method for manufacturing a packaging substrate according to claim 1, wherein: The method for manufacturing the package substrate further comprises a final curing step after the second curing step. The final curing step is a step of additionally curing the first insulating film and the second insulating film.

7. The method for manufacturing a packaging substrate according to claim 2, wherein: The electrical components include passive components or active components.

8. A packaging substrate, characterized in that: include: core layer, and an upper layer, located on the core layer; The core layer comprises: A glass core includes a first surface and a second surface facing each other, A plurality of core through holes and cavities penetrate the glass core in the thickness direction of the glass core, A conductive layer is disposed on the surface of the glass core, An electrical component is arranged in the cavity portion, and an insulating layer filling the core through hole and the cavity portion; The cavity has a space, and the space is open toward the first surface or the second surface of the glass core and is formed concavely, or is formed through the first surface and the second surface. The insulating layer comprises: a first insulating layer formed by laminating and curing a first insulating film on the first surface, and The second insulating layer is formed by laminating and curing a second insulating film on the first insulating layer.

9. The packaging substrate according to claim 8, characterized in that: The first insulating layer is formed on the entire first surface or the cavity portion where the electrical element is arranged.

10. The packaging substrate according to claim 8, characterized in that: The insulating layer further includes a third insulating layer formed by laminating and curing a third insulating film on the second face.

11. The packaging substrate according to claim 10, characterized in that: A first boundary in contact with the first insulating film and the second insulating film is formed between the first insulating layer and the second insulating layer, A second boundary in contact with the first insulating film and the third insulating film is formed between the first insulating layer and the third insulating layer, The second boundary is formed inside the core through hole and the cavity portion.

12. The packaging substrate according to claim 10, characterized in that: The color of the first insulating layer and the color of the third insulating layer are different from each other.

13. The packaging substrate according to claim 8, characterized in that: The thickness of the first insulating layer and the thickness of the second insulating layer are different from each other.

14. The packaging substrate according to claim 8, characterized in that: The glass core is quadrilateral, and the thickness of the glass core is 300 μm to 1,500 μm. The height between the bottom surface on which the package substrate is placed and the corner of the package substrate is 12 mm or less.

15. The packaging substrate according to claim 8, characterized in that: The electrical components include passive components or active components.

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