Integrated chip and packaging method

Abstract

The embodiment of the invention discloses an integrated chip and a packaging method, relates to the technical field of semiconductors, and is convenient for optimizing the heat dissipation performance of the chip by improving the internal structure of the chip. The integrated chip comprises a first crystal grain; the at least one second crystal grain is vertically stacked on the first crystal grain, and the front surface of the second crystal grain is bonded with the back surface of the first crystal grain; a heat through hole is formed in the back surface of the first crystal grain in an extending manner from the interior of the first crystal grain, and the heat through hole is used for conducting at least part of heat generated by the first crystal grain to the outside of the at least one second crystal grain. Therefore, at least one part of heat generated by the first crystal grain can be conducted out of at least one crystal grain above the first crystal grain through the heat through hole, and does not completely pass through the second crystal grain above the first crystal grain. The method is suitable for chip structure design and packaging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an integrated chip and a packaging method. Background Art

[0002] As semiconductor process nodes approach their limits, advanced packaging technology is developing rapidly. 3D stacking technology achieves higher integration density and performance improvement by integrating heterogeneous chips in the vertical direction. This technology usually uses through-silicon vias (TSV) and hybrid bonding processes to achieve efficient interconnection between chip layers.

[0003] In the related art, the second die, such as a cache die, is stacked vertically on the first die. The first die can be a system-level die (SOC Die, commonly known as a system-level chip, or a processor die (CPU Die, sometimes also called Core Die), which expands the cache capacity to a certain extent without increasing the chip area. However, the first die will generate a lot of heat during operation, and this heat needs to be naturally conducted to the outside of the package layer by layer through the second die and the silicon carrier. The heat can easily cause the temperature of the upper second die to rise during the transmission process, which will have an adverse effect on its performance and may even damage it. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides an integrated chip and a packaging method, which improves the internal structure of the chip to optimize the heat dissipation performance of the chip.

[0005] In order to achieve the above-mentioned invention object, the following technical scheme is adopted: According to a first aspect of an embodiment of the present invention, there is provided an integrated chip, comprising: a first crystal grain; at least one second crystal grain stacked vertically on the first crystal grain, and the front side of the second crystal grain is bonded to the back side of the first crystal grain; a thermal via is extended from the inside of the first crystal grain to the back side of the first crystal grain, and the thermal via is used to conduct at least part of the heat generated by the first crystal grain to the outside of the at least one second crystal grain.

[0006] According to a specific implementation of the embodiment of the present application, a first virtual crystal grain is provided on both sides of the at least one second crystal grain, and a first heat dissipation channel connected to the thermal via is provided in the first virtual crystal grain.

[0007] According to a specific implementation of an embodiment of the present application, a lateral heat dissipation channel is provided at a bonding interface between the first grain and at least one second grain, and the lateral heat dissipation channel is connected to the thermal via for laterally directing at least part of the heat from the central area of ​​the first grain to the outer area of ​​the second grain.

[0008] According to a specific implementation method of the embodiment of the present application, a lateral heat dissipation channel is provided at the bonding interface between the first grain and at least one second grain, and the lateral heat dissipation channel is connected to the thermal via and the first heat dissipation channel, and the lateral heat dissipation channel is used to laterally direct at least part of the heat from the central area of ​​the first grain to the first heat dissipation channel in the virtual grains on both sides of the second grain.

[0009] According to a specific implementation method of an embodiment of the present application, a redistribution layer is provided at the bonding interface between the first grain and at least one second grain, and metal grooves and bonding pad grooves are arranged in the redistribution layer. Conductive material is filled in the metal groove to form a metal wire, and the metal wire constitutes the lateral heat dissipation channel and is connected to the thermal via.

[0010] According to a specific implementation of the embodiment of the present application, the first heat dissipation channel of the first virtual die is in communication with the external environment of the chip package.

[0011] According to a specific implementation of the embodiment of the present application, a second virtual grain is further provided on the at least one second grain, a second heat dissipation channel is provided in the second virtual grain, and the second heat dissipation channel is communicated with the first heat dissipation channel in the first virtual grain.

[0012] According to a specific implementation method of an embodiment of the present application, the first end of the second heat dissipation channel is connected to the first heat dissipation channel in the first virtual grain, and the second end of the second heat dissipation channel terminates inside the second virtual grain, or the second end of the second heat dissipation channel extends outside the second virtual grain.

[0013] According to a second aspect of an embodiment of the present invention, there is provided a chip packaging method, comprising: Providing at least one first die, forming a thermal via in the first die leading to a back surface; Provide at least one die, vertically stack at least one of the die on top of the first die, and bond the back side of the first die to the front side of the at least one die to form a 3D chip packaging structure; flip the front side of the first die of the 3D chip packaging structure downward onto a substrate.

[0014] According to a specific implementation of the embodiment of the present application, providing at least one die includes: providing at least one first virtual die, and forming a first heat dissipation channel in the first virtual die; Vertically stacking at least one of the dies onto the first die, and bonding the first die to the at least one die, including: aligning the first heat dissipation channel with the thermal via in the first die, so that after bonding is completed, the first heat dissipation channel is connected to the thermal via in the first die.

[0015] According to a specific implementation method of an embodiment of the present application, providing at least one grain includes: providing at least one second grain, forming a lateral heat dissipation channel in the bonding interface between the first grain and the second grain, and the lateral heat dissipation channel is connected to the thermal via, and is used to laterally direct the heat of the first grain to the outside of the second grain.

[0016] According to a specific implementation of the embodiment of the present application, forming a transverse heat dissipation channel in the bonding interface between the first die and the second die includes: Depositing an oxide layer and a silicon nitride layer in sequence on the redistribution layer on the surface of the first grain; forming metal trenches and bonding pad trenches in the oxide layer and the silicon nitride layer; Metal materials are filled in the metal grooves and bonding pad grooves to form lateral heat dissipation channels.

[0017] According to a specific implementation method of an embodiment of the present application, after providing at least one second grain, it also includes: setting first virtual grains on both sides of the second grain respectively, and forming a first heat dissipation channel in the first virtual grain, and the lateral heat dissipation channel is connected to the first heat dissipation channels in the two first virtual grains.

[0018] According to a specific implementation method of the embodiment of the present application, it also includes: setting a second virtual grain on the at least one grain, and forming a second heat dissipation channel in the second virtual grain, and the second heat dissipation channel is connected to the first heat dissipation channel in the first virtual grain.

[0019] According to a specific implementation of the embodiment of the present application, the second end of the second heat dissipation channel terminates inside the second virtual die, or extends and penetrates outside the second virtual die.

[0020] According to a specific implementation method of an embodiment of the present application, providing at least one first grain and forming a thermal via in the first grain leading to the back side includes: providing a first wafer containing a first grain, and forming a thermal via in the first grain leading to the back side; providing at least one grain, including: providing a second wafer containing a grain, and forming a bonding pad on the second wafer; vertically stacking at least one of the grains on top of the first grain, and bonding the first grain to the at least one grain to form a 3D chip packaging structure, including: hybrid bonding the first wafer and the second wafer to form a wafer-level 3D stacking structure.

[0021] The integrated chip and packaging method provided in the embodiment of the present application improve the internal structure of the chip, and set a thermal via in the first crystal grain to conduct at least part of the heat generated by the first crystal grain to the outside of the at least one second crystal grain. In this way, at least part of the heat generated by the first crystal grain (Core die) can be conducted to the outside of at least one crystal grain above the first crystal grain through the thermal via, without all passing through the second crystal grain above the first crystal grain. By changing the conduction path of part of the heat, the heat directly received by the second crystal grain above the first crystal grain can be reduced to a certain extent, so that the temperature rise of the second crystal grain above the first crystal grain is not easy to be too high, thereby facilitating the optimization of the heat dissipation performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structure of an integrated chip provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of an integrated chip provided by yet another embodiment of the present invention; Figure 3 A schematic diagram of the structure of an integrated chip provided by another embodiment of the present invention; Figure 4 A schematic diagram of a packaging method flow chart provided by an embodiment of the present invention; Figures 5 to 21 A schematic diagram of a structural cross section and a top view of a key process in an integrated chip packaging process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In order to realize the different features of the provided subject matter, the present invention provides many different embodiments or examples. The following describes specific examples of components and arrangements to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first and second components are formed in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact.

[0027] In the existing 3D stacked chip packaging technology, heat management has always been an important factor limiting the improvement of chip performance. As the number of vertically stacked chips increases, the first die, generally the SOC Die or CPU Die, is usually located at the bottom of the stacking structure, while the second die, generally the Cache Die, is located above it. In the prior art, this stacking method requires that a large amount of heat generated by the first die be transferred to the outside layer by layer through the second die, resulting in a long heat transfer path and low heat dissipation efficiency. At the same time, the performance of the second die is reduced due to heat accumulation, and there is even a risk of overheating of the die.

[0028] Embodiment 1 In response to the above problems, an embodiment of the present invention provides a new integrated chip, which is suitable for chip structure design and packaging. By setting a thermal via from at least the first crystal grain to the outside, at least part of the heat generated by the first crystal grain can be directly conducted to the outside of the chip along a predetermined direction without passing through the second crystal grain on the upper layer, thereby improving the heat dissipation performance.

[0029] Figure 1 The integrated chip structure provided according to an embodiment of the present invention is shown. Please note: In order to highlight the innovative purpose of the present invention, the number of chip stacking layers shown in the figure is only for illustration and cannot be regarded as a limitation on the specific number of stacking layers. The chip includes: a first die 102; the first die 102 can be a CPU die, a SoC die, etc., which contains complex circuits and modules inside, carries data calculation, processing and other tasks, and is generally the main heat source of the entire integrated chip.

[0030] At least one second die 104 is vertically stacked on the first die 102, and the front side of the second die 104 is bonded to the back side of the first die 102. Specifically, the at least one second die 104 and the first die 102 can be stacked by hybrid bonding technology to achieve physical connection and electrical interconnection.

[0031] A thermal via 106 is provided extending from the inside of the first die 102 to the back of the first die, and the thermal via 106 is used to conduct at least part of the heat generated by the first die 102 to the outside of the at least one second die 104, thereby reducing the heat load directly borne by the upper second die. Since the thermal via 106 is provided from the inside of the first die 102 to the outside, the heat transfer between the first die 102 and the upper stacked second die is reduced, thereby improving the performance of the second die in the stacked structure.

[0032] Specifically, the thermal vias 106 may be designed to be arranged in a grid or distributed in a point pattern according to the heat distribution of the core area to ensure maximum heat conduction.

[0033] The integrated chip provided in the embodiment of the present application improves the internal structure of the chip, and sets a thermal via 106 in the first crystal grain 102, which is used to conduct at least part of the heat generated by the first crystal grain 102 to the outside of the at least one second crystal grain 104. In this way, at least part of the heat generated by the first crystal grain 102 can be conducted to the outside of the at least one second crystal grain 104 above the first crystal grain 102 through the thermal via 106, without all passing through the second crystal grain above the first crystal grain 102. By changing the conduction path of part of the heat, the heat directly received by the second crystal grain above the first crystal grain 102 can be reduced to a certain extent, so that the temperature rise of the second crystal grain above the first crystal grain 102 is not easy to be too high, thereby facilitating the optimization of the heat dissipation performance of the chip.

[0034] In some embodiments, the thermal via 106 is a thermal via (Thermal TSV) filled with metal material. The thermal via 106 can be prepared by the following steps: using photolithography technology to define the location of the thermal via on the first crystal grain 102, and forming a hole structure with one longitudinal end exposed to the surface of the first crystal grain 102 by dry etching process; filling the formed hole structure with a metal material with good thermal conductivity such as gold, silver, copper or aluminum to form an efficient thermal via 106. Among them, the cross-sectional area and spacing of the thermal via can be optimized according to the heat distribution of the chip.

[0035] Specifically, in order to prevent the metal material from diffusing to other areas of the chip, a barrier layer is deposited on the wall of the thermal via, such as tantalum, titanium nitride, etc. Subsequently, the metal material is filled by an electroplating process, and chemical mechanical polishing (CMP) is used to remove excess filling metal material on the surface of the first grain 102 .

[0036] In some embodiments, at least a portion of the lower ends of the thermal vias 106 are connected to the metal layer (Metal x) in the first die 102. The thermal vias 106 can be connected to the metal layer by thermocompression bonding or welding to form a stable heat transfer path.

[0037] Figure 2 A schematic diagram of the cross-sectional structure of an integrated chip according to an embodiment of the present invention is shown. A first virtual crystal grain 108 is provided on both sides of the at least one second crystal grain 104, and a first heat dissipation channel 110 connected to the thermal via 106 is provided in the first virtual crystal grain 108. The first heat dissipation channel 110 is connected to the thermal via 106 in the first crystal grain 102, and is used to further guide the heat generated by the first crystal grain 102 to the first virtual crystal grain 108 for dissipation. The first heat dissipation channel 110 can be a longitudinal heat conduction channel formed by photolithography and deep silicon etching (DRIE, Deep Reactive Ion Etching). Subsequently, a metal material with high thermal conductivity, such as copper or tungsten, is filled in the channel to ensure efficient heat transfer.

[0038] Figure 3 The bonding interface structure between the first die 102 and the second die 104 is also shown. The bonding interface between the first die 102 and at least one second die 104 is provided with a transverse heat dissipation channel 112, which is connected to the thermal via 106 and is used to guide at least part of the heat from the first die 102 to the outside of the second die 104 laterally.

[0039] In this embodiment, a transverse heat dissipation channel 112 is provided to communicate with the thermal via 106, so that at least part of the heat generated in the central area of ​​the first die 102 is guided horizontally to the outer area of ​​the second die 104, thereby avoiding heat concentration in the central area of ​​the chip and passing upward through the second die 104, thereby improving the heat dissipation performance.

[0040] In some embodiments, the first virtual die 108 is located on both sides of the second die 104. A lateral heat dissipation channel 112 is provided at the bonding interface between the first die 102 and at least one second die 104, and the lateral heat dissipation channel 112 is connected to the thermal via 106 and the first heat dissipation channel 110. The lateral heat dissipation channel 112 is used to laterally guide at least part of the heat from the first die 102 to the first heat dissipation channel 110 in the virtual die on both sides of the second die 104.

[0041] The transverse heat dissipation channel 112 can be defined in position and size on the joint surface of the first die 102 and the second die 104 by photolithography and etching processes. High thermal conductivity metal materials, such as silver, copper or aluminum, are filled in the formed transverse heat dissipation channel 112. The thermal conductive metal materials are deposited in the channel by electroplating, chemical vapor deposition and other processes to ensure rapid heat conduction.

[0042] In some embodiments, a redistribution layer (RDL) is provided at the bonding interface between the first die 102 and at least one second die 104, and a metal trench and a bonding pad trench are arranged in the redistribution layer. A conductive material is filled in the metal trench to form a metal line, and the metal line constitutes the lateral heat dissipation channel and is connected to the thermal via.

[0043] In the present embodiment, by forming the thermal vias 106, the lateral heat dissipation channels 112 and the first heat dissipation channels 110 in the first virtual die 108 inside the chip, an efficient three-dimensional heat dissipation network is formed together, and the specific heat conduction path thereof may be: heat is transferred upward from the high heat density area of ​​the first die 102 to the lateral heat dissipation channels 112 through the thermal vias (an example of the thermal vias 106); the lateral heat dissipation channels 112 conduct the heat from the central area of ​​the first die 102 to the outside of the second die 104; and the heat is finally guided to the external environment of the packaging shell through the first heat dissipation channels 110 in the first virtual die 108, thereby achieving effective heat dissipation.

[0044] In the embodiment of the present invention, without increasing the chip packaging area, the operating temperature of the first die 102 and the second die 104 is effectively reduced through an optimized heat dissipation path, which significantly improves the heat dissipation performance inside the chip, and improves the thermal management capability, reliability and life of the chip.

[0045] In order to achieve efficient heat dissipation, in some embodiments, the first heat dissipation channel 110 of the first virtual die 108 is connected to the external environment of the chip package. Specifically, one end of the first heat dissipation channel 110 passes through the top of the virtual die and is directly exposed to the outside of the chip package. The external environment of the package can further integrate a heat sink, a heat pipe or other heat dissipation module to quickly discharge the heat inside the chip.

[0046] Continue to view Figure 3, because the first die and the second die on the top need to be ground very thin in the wafer-level packaging process, in order to balance the overall thickness, a dummy wafer will be bonded (Bonding) at the end to ensure the overall 3D stacking thickness, so as not to affect the subsequent outsourced semiconductor assembly and test (OSAT, Outsourced Semiconductor Assembly and Test). Therefore, a second dummy die 114 is also provided on the at least one second die 104, and a second heat dissipation channel 116 is provided in the second dummy die 114, and the second heat dissipation channel 116 is connected to the first heat dissipation channel 110 in the first dummy die 108. The second dummy die 114 is arranged above the second die 104 and above the first dummy die 108, so as to further optimize the heat dissipation and guide the heat to a higher level heat dissipation path through the second heat dissipation channel 116 therein.

[0047] In this embodiment, by providing the second heat dissipation channel 116 in the second virtual die 114 , heat can be further dispersed through a multi-level channel system, thereby reducing the temperature in the entire stack structure.

[0048] Continue to view Figure 3 Specifically, a first end of the second heat dissipation channel 116 is communicated with the first heat dissipation channel 110 in the first virtual die 108 , and a second end of the second heat dissipation channel 116 terminates inside the second virtual die 114 .

[0049] Alternatively, the second end of the second heat dissipation channel 116 extends outside the second dummy die 114 .

[0050] Specifically, there are two situations for the second heat dissipation channel 116. The first situation is that the first end of the second heat dissipation channel 116 is connected to the first heat dissipation channel 110 in the first virtual die 108, ensuring that heat is conducted from the first die 102 to the first virtual die 108 through the thermal vias and the transverse heat dissipation channel 112, and then enters the second heat dissipation channel 116. The second situation is that the second heat dissipation channel 116 penetrates and extends outside the second virtual die 114, directly introduces heat into the external environment of the package shell, and combines with an external heat dissipation system, such as a heat sink or a heat pipe, to dissipate heat.

[0051] However, the thickness of the SOC die (including the core die) and the second die 104 is relatively thin, generally between 5 and 15um, while the thickness of the silicon carrier is about 750um. This thickness difference makes it difficult for the TSV (Through-Silicon Via) path to directly penetrate the silicon carrier and connect to the outside. In this case, it is possible to consider preparing a thermal channel from the top of the virtual die downward, so as to lead the TSV in the first virtual die 108 to the outside through the second virtual die 114.

[0052] Since the preparation of thermal channels on the top of the dummy die requires increased design complexity and manufacturing costs, of course, this can also help improve the reliability and performance of the TSV path. Therefore, it is necessary to consider the balance between cost and heat dissipation efficiency.

[0053] In the embodiment of the present invention, the heat of the first die 102 is transferred to the heat dissipation channel in the first virtual die 108 through the thermal vias and the lateral heat dissipation channel 112, and the thermal vias 106 are further optimized through the heat dissipation channel of the second virtual die 114, and finally the heat is guided to the external environment or the heat dissipation module, forming a complete heat transfer network connecting the 3D stacking structure, improving the heat dissipation efficiency, thereby ensuring the stability and long-term operation capability of the chip in a high power consumption state to a certain extent.

[0054] Embodiment 2 Figure 4 The present invention provides a packaging method that can be used to package an integrated chip, including: providing at least one first die 102, and forming a thermal via 106 in the first die 102 that leads to the back side.

[0055] The first die 102 may be provided in the form of a single die, or in the form of a wafer including at least one first die 102. Figure 5 In some embodiments, at least one SOC wafer including a first die 102 is provided, which is first processed by a 2D-related process, mainly including the formation of a multi-layer metal interconnect structure, and the preparation of a bonding pad via and a bonding pad for subsequent packaging and stacking processes.

[0056] After completing the metal wiring and bonding pad preparation on the front side of the wafer, continue to refer to Figure 5The wafer is face-down bonded to a temporary silicon carrier and thinned to reduce its thickness to a target thickness range, and then cut into single first dies 102 .

[0057] Next, a thermal via 106 leading to the back side is formed in the first die. In some embodiments, the thermal via 106 is formed in the first die 102 by thermal via (Through-Silicon Via) technology. Specifically, the process includes: depositing a dielectric layer and a barrier layer, see Figure 6 and Figure 7 Specifically, oxide and silicon nitride (SiN) may be deposited in sequence on the back of the first crystal grain 102, wherein oxide is deposited to form a dielectric layer and silicon nitride is deposited to form a barrier layer. A thermal via mask (TSV Mask) is used for photolithography and etching to form a thermal via hole (TSV Trench, sometimes translated as trench in Chinese depending on the etching position).

[0058] See also Figure 2 or Figure 3 , providing at least one die, vertically stacking the at least one die on the first die 102, and bonding the back side of the first die 102 to the front side of the at least one die (face to backbonding) to form a 3D chip packaging structure.

[0059] The first die of the 3D chip packaging structure is flipped onto the substrate with the front side facing downward. Before, after or at the same time as the first die 102 forms the thermal via 106 leading to the back side, at least one die, such as the second die 104 or a dummy die, is provided to also complete the 2D process. After completing the 2D process, these die are photolithographically fabricated with bonding pads and bonding vias, and after surface metallization and bonding pad preparation are completed, they are separated into individual cores through a cutting process and thinned to a target thickness according to design requirements.

[0060] Afterwards, the first die 102 is vertically stacked with at least one die using a hybrid bonding process, and high-density electrical connection is achieved through direct metal interconnection and oxide interconnection, while reducing the thermal resistance of the bonding interface to form a 3D chip packaging structure. During the bonding process, appropriate temperature and pressure are used to ensure a strong electrical and physical connection between the die.

[0061] It should be noted that, before stacking, the preparation process steps of the first die 102 and at least one other die for stacking can be interchangeable or performed simultaneously, and the description of them first or later cannot be regarded as limiting their specific processes.

[0062] As mentioned above, wafer level packaging can be used, so see Fig.21 As shown, in some embodiments, providing at least one first die 102 and forming a thermal via 106 in the first die 102 leading to the back side includes: providing a first wafer including the first die 102 and forming a thermal via 106 in the first die 102 leading to the back side.

[0063] Providing at least one die includes providing a second wafer including the die, and forming a bonding pad on the second wafer.

[0064] At least one of the die is vertically stacked on top of the first die, and the first die is bonded to the at least one die to form a 3D chip packaging structure, including: hybrid bonding the back side of the first wafer and the front side of the second wafer to form a wafer-level 3D stacking structure (3DIC wafer).

[0065] Then, the final 3DIC wafer is cut into individual dies before proceeding to the subsequent substrate process.

[0066] See also Figure 8 and Fig. 9 As shown, in some embodiments, forming a thermal via 106 in the first die leading to the back side includes: forming a thermal via filled with a thermal conductive material in the first die 102 .

[0067] See also Figure 6 , a thermal via mask (TSV Mask) is used to perform photolithography (Litho) on the barrier layer on the surface of the first die 102 to define the location and size of the thermal via. Subsequently, a vertical hole (Trench) is formed in the first die 102 using dry etching (Dry Etching) and wet cleaning (WetCleaning) process technology; see Figure 8 and Fig. 9 In the hole, a barrier layer, such as tantalum or silicon nitride, is first deposited to prevent metal diffusion. Then, a copper seed layer is deposited to provide a conductive base for subsequent metal filling. Through the electroplating process, the thermal via is filled with a high thermal conductivity metal material, such as copper, aluminum or silver. The thickness of the metal filling is optimized according to the chip's heat dissipation requirements. Fig.10 and Fig.11After filling the metal, the CMP process is used to remove the excess metal and oxide layer on the surface of the thermal via to ensure the flatness of the back side of the first grain 102 and prepare for the subsequent bonding process.

[0068] See also Fig.10 According to the function of TSV, holes are divided into the following categories: signal TSV, power TSV and thermal TSV, among which active TSVs such as signal TSV and power TSV need to land on the metal layer (Metal X) in the first die 102 to achieve electrical interconnection. Of course, these active TSVs can also transfer heat.

[0069] See also Fig.10 and Fig.11 , a metal line is formed on the first crystal grain 102 and connected to the thermal via 106. Specifically, first, a layer of silicon oxide is deposited on the surface of the first crystal grain 102 as a dielectric layer, and then photolithography and etching are performed on the dielectric layer using a photomask technique to define the position and shape of the metal trench. Fig.12 and Fig.13 , through physical vapor deposition (PVD, Physical Vapor Deposition) or chemical vapor deposition (CVD, Chemical Vapor Deposition) process, highly conductive materials such as copper or aluminum are deposited in the metal trench. The CMP process is used to remove excess metal materials so that the metal wire groove is flush with the surface of the dielectric layer to form a complete metal wire network.

[0070] After forming the thermal via 106, a connection channel of the interconnection point is etched between the thermal via and the predetermined interconnection position of the metal wire slot using a directional etching process (DRIE). Copper or other conductive metal materials are deposited in the connection channel through an electroplating process, so that the thermal via forms a stable electrical and thermal connection with the metal wire network.

[0071] In some embodiments, providing at least one die includes: providing at least one second die 104, forming a transverse heat dissipation channel 112 in the bonding interface between the first die 102 and the second die 104, and the transverse heat dissipation channel 112 is connected to the thermal via 106, and is used to laterally guide the heat of the first die 102 to the outside of the second die 104.

[0072] See also Fig.14 Specifically, a cache wafer is provided, and the cache wafer completes 2D related processes and is prepared to the top metal layer. Fig.15 Schematic diagram of the bonding pad through hole and the bonding pad cross section; see Fig.15 , use the bonding pad via mask to make bonding pad vias and bonding pads on the buffer wafer. Fig.16 and Fig.17 , the cache wafer after the previous process is completed is thinned to the target thickness, and then cut into a single second die (Cache die).

[0073] The providing of at least one crystal grain includes: providing at least one first virtual crystal grain, and forming a first heat dissipation channel 110 in the first virtual crystal grain 108. The virtual crystal grain is formed into a single crystal grain by laser cutting after completing preliminary processing on a silicon wafer. Subsequently, the virtual crystal grain is thinned to a target thickness by back grinding or chemical mechanical polishing (CMP) process, which is generally substantially the same as the thickness of the second crystal grain 104. In the virtual crystal grain, a heat dissipation channel mask (Thermal Via Mask) is used for photolithography and etching to form a first heat dissipation channel 110 that passes through the virtual crystal grain. A high thermal conductivity material, such as copper or tungsten, is filled in the heat dissipation channel by an electroplating process, and the surface of the channel is flattened by a CMP process to ensure the bonding quality with other stacked crystal grains.

[0074] In one embodiment, forming a lateral heat dissipation channel in the bonding interface between the first grain and the second grain includes: depositing an oxide layer and a silicon nitride layer in sequence on the redistribution layer on the surface of the first grain; forming a metal groove and a bonding pad groove in the oxide layer and the silicon nitride layer; and filling the metal groove and the bonding pad groove with metal material to form a lateral heat dissipation channel.

[0075] Vertically stacking at least one of the die on the first die 102, and bonding the first die 102 to the at least one die, including: aligning the first heat dissipation channel 110 with the thermal via 106 in the first die 102, so that after the bonding is completed, the first heat dissipation channel 110 is connected to the thermal via 106 in the first die 102. Specifically, when the virtual die is vertically stacked on the first die 102, it is necessary to ensure that the first heat dissipation channel 110 is aligned with the thermal via 106 in the first die 102, and a hybrid bonding technology is used to ensure the precise alignment of the first heat dissipation channel 110 with the thermal via through a high-precision alignment process. After the alignment is completed, the thermal connection between the first heat dissipation channel 110 and the thermal via is achieved through a thermal compression bonding or a direct metal-to-metal contact process.

[0076] See also Fig.18Specifically, an oxide is deposited on a silicon carrier wafer, and then a second die is bonded to the silicon carrier wafer. At the same time, according to a design scheme, a first dummy die is inserted next to the second die.

[0077] Next, oxide filling and surface polishing are performed, see Fig.19 , filling oxide between the second grain and the first dummy grain, and exposing the surface silicon of the second grain and the dummy grain through a chemical mechanical polishing (CMP) process.

[0078] In the embodiment of the present invention, through the above process, efficient connection between the thermal via 106 in the first grain 102 and the metal wire and the virtual grain heat dissipation channel is achieved, forming a multi-level heat dissipation network, which significantly improves the heat dissipation performance of the 3D stacking structure.

[0079] Specifically, after the second die 104 is prepared through wafer preparation, the following process is performed: The second die 104 is cut from the cache wafer into individual cores and thinned to a target thickness by mechanical grinding or chemical mechanical polishing (CMP) process. A metallized bonding pad (Bond Pad) and an interconnect metal layer are prepared on the front side of the second die 104 to prepare for subsequent electrical and thermal connection with the first die 102.

[0080] A patterning process is performed on the top of the first crystal grain 102 and the bottom of the second crystal grain 104 using a photomask, and then a trench of the lateral heat dissipation channel 112 is etched using a dry etching technique, such as deep reactive ion etching.

[0081] The metal grooves of the formed lateral heat dissipation channel 112 are filled with high thermal conductivity metal materials to ensure efficient lateral heat conduction. Finally, the interface is flattened by a CMP process to ensure good contact between the channel and other bonding areas.

[0082] The formed lateral heat dissipation channel 112 is connected to the thermal via 106 in the first die 102 and is used to conduct the heat generated by the first die 102 from the high heat density area to the outer area of ​​the second die 104 laterally, thereby preventing all the heat dissipated upward from the first die 102 from being concentrated on the second die 104.

[0083] See also Fig.19 and Figure 3As shown, in another embodiment, after providing at least one second die 104, it also includes: setting first virtual die 108 on both sides of the second die 104 respectively, and forming a first heat dissipation channel 110 in the first virtual die 108, and the lateral heat dissipation channel 112 is connected to the first heat dissipation channels 110 in the two first virtual die 108.

[0084] Specifically, in this embodiment, after providing at least one second die 104, a first virtual die 108 is inserted into the reserved areas on both sides of the second die 104 to ensure that the virtual die and the second die 104 are closely matched in physical position. The virtual die generally has no actual function in the entire chip structure, but it can help evenly distribute heat and prevent overheating in certain areas. In addition, it can also provide mechanical support to prevent actual functional chips from being damaged during stacking and packaging.

[0085] The virtual die is photolithographically processed using a thermal via mask to define the location of the thermal via. Subsequently, a first thermal via 110 vertically penetrating the virtual die is formed by a DRIE process.

[0086] Both ends of the transverse heat dissipation channel 112 are connected to the first heat dissipation channels 110 in the two first virtual dies 108. In this way, the heat generated by the first die 102 can be transferred to the first heat dissipation channel 110 through the transverse heat dissipation channel 112, and finally form an overall heat dissipation network, thereby improving the overall heat dissipation performance.

[0087] In the embodiment of the present invention, an efficient transverse heat dissipation channel 112 is formed between the first die 102 and the second die 104, and a first heat dissipation channel 110 is provided in the virtual die on both sides of the second die 104. This multi-level heat dissipation network design can significantly improve the heat dissipation efficiency of the chip, avoid thermal interference of high-heat areas on other functional chips, and ensure efficient operation and stability of the chip.

[0088] According to an embodiment of the present invention, improvements can be made on the basis of the existing 3D stacked chip structure, and the existing 3D packaging form and its hybrid bonding process characteristics can be utilized to significantly improve the heat dissipation performance of the stacked chip without adding additional modules or complex processes.

[0089] In the embodiment of the present invention, the thermal vias 106, the lateral heat dissipation channels 112 and the heat dissipation vias in the first die 102, the second die 104 and the virtual die are organically integrated to form a three-dimensional heat dissipation network that combines vertical and horizontal directions. This three-dimensional heat dissipation system can efficiently remove the heat inside the stacked chips, reduce the heat accumulation inside the chips, and avoid the performance degradation caused by overheating. It is suitable for the packaging and thermal management of various high-performance 3D chips.

[0090] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0091] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0092] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An integrated chip, characterized in that: include: first grain; at least one second die, vertically stacked on the first die, with the front side of the second die bonded to the back side of the first die; A thermal via is extended from the inside of the first die to the back side of the first die, and the thermal via is used to conduct at least part of the heat generated by the first die to the outside of the at least one second die.

2. The integrated chip according to claim 1, characterized in that: A first virtual crystal grain is disposed on both sides of the at least one second crystal grain, and a first heat dissipation channel communicating with the thermal via is disposed in the first virtual crystal grain.

3. The integrated chip according to claim 1, characterized in that: A lateral heat dissipation channel is provided at the bonding interface between the first die and at least one second die. The lateral heat dissipation channel is connected to the thermal via and is used to laterally guide at least part of the heat from the central area of ​​the first die to the outer area of ​​the second die.

4. The integrated chip according to claim 3, characterized in that: A lateral heat dissipation channel is provided at the bonding interface between the first grain and at least one second grain, and the lateral heat dissipation channel is connected to the thermal via and the first heat dissipation channel, and the lateral heat dissipation channel is used to laterally direct at least part of the heat from the central area of ​​the first grain to the first heat dissipation channel in the virtual grains on both sides of the second grain.

5. The integrated chip according to claim 3 or 4, characterized in that: A redistribution layer is provided at the bonding interface between the first crystal grain and at least one second crystal grain, and metal grooves and bonding pad grooves are arranged in the redistribution layer. Conductive material is filled in the metal groove to form a metal wire, and the metal wire constitutes the lateral heat dissipation channel and is connected to the thermal via.

6. The integrated chip according to claim 2, characterized in that: The first heat dissipation channel of the first virtual die is communicated with the external environment of the chip package shell.

7. The integrated chip according to claim 2, characterized in that: A second virtual crystal grain is further disposed on the at least one second crystal grain. A second heat dissipation channel is disposed in the second virtual crystal grain. The second heat dissipation channel is communicated with the first heat dissipation channel in the first virtual crystal grain.

8. The integrated chip according to claim 7, characterized in that: The first end of the second heat dissipation channel communicates with the first heat dissipation channel in the first virtual die, and the second end of the second heat dissipation channel terminates inside the second virtual die, or the second end of the second heat dissipation channel extends outside the second virtual die.

9. A chip packaging method, characterized in that: include: Providing at least one first die, forming a thermal via in the first die leading to a back surface; Providing at least one die, vertically stacking the at least one die on the first die, and bonding the back surface of the first die to the front surface of the at least one die to form a 3D chip packaging structure; The first die of the 3D chip packaging structure is flipped onto a substrate with the front side facing downward.

10. The method according to claim 9, characterized in that The providing at least one crystal grain comprises: providing at least one first virtual crystal grain, and forming a first heat dissipation channel in the first virtual crystal grain; Vertically stacking at least one of the dies onto the first die, and bonding the first die to the at least one die, including: aligning the first heat dissipation channel with the thermal via in the first die, so that after bonding is completed, the first heat dissipation channel is connected to the thermal via in the first die.

11. The method according to claim 9, characterized in that Providing at least one crystal grain includes: providing at least one second crystal grain, forming a transverse heat dissipation channel in the bonding interface between the first crystal grain and the second crystal grain, wherein the transverse heat dissipation channel is connected to the thermal via and is used to laterally guide the heat of the first crystal grain to the outside of the second crystal grain.

12. The method according to claim 11, characterized in that The forming of a transverse heat dissipation channel in the bonding interface between the first die and the second die comprises: Depositing an oxide layer and a silicon nitride layer in sequence on the redistribution layer on the surface of the first grain; forming metal trenches and bonding pad trenches in the oxide layer and the silicon nitride layer; Metal materials are filled in the metal grooves and bonding pad grooves to form lateral heat dissipation channels.

13. The method according to claim 12, characterized in that After providing at least one second die, the method further includes: arranging first virtual die on both sides of the second die respectively, and forming a first heat dissipation channel in the first virtual die, wherein the lateral heat dissipation channel is connected to the first heat dissipation channels in the two first virtual die.

14. The method according to claim 9, characterized in that Also includes: A second virtual die is disposed on the at least one die, and a second heat dissipation channel is formed in the second virtual die, wherein the second heat dissipation channel is connected to the first heat dissipation channel in the first virtual die.

15. The method according to claim 14, characterized in that The second end of the second heat dissipation channel terminates inside the second virtual die, or extends through to outside the second virtual die.

16. The method according to claim 9, characterized in that: The providing at least one first die, and forming a thermal via in the first die leading to the back side includes: providing a first wafer including a first die, and forming a thermal via in the first die leading to the back side; Providing at least one die, including: providing a second wafer including the die, and forming a bonding pad on the second wafer; Vertically stacking at least one of the dies on the first die, and bonding the first die to the at least one die to form a 3D chip packaging structure, comprising: The back side of the first wafer and the front side of the second wafer are hybrid-bonded to form a wafer-level 3D stacking structure.

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