Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure includes an interconnect structure, a passivation layer, and a conductive bump structure. The interconnect structure includes a conductive pad on top of the interconnect structure. The passivation layer is disposed on the interconnect structure. The conductive bump structure is disposed and embedded in the passivation layer and the conductive pad. In the first direction, a first interface between the passivation layer and the conductive pad is located alongside and misaligned with a second interface between the conductive bump structure and the conductive pad.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the same, and in particular to a semiconductor structure with a bump structure having improved reliability and a method for forming the same. Background Art

[0002] In recent years, advanced integrated circuit (IC) devices have become increasingly multifunctional and have continued to shrink in size. Although the shrinking process generally improves production efficiency and reduces associated costs, it also increases the complexity of processing and manufacturing IC devices. For example, in the semiconductor manufacturing process, it is necessary to turn to copper (Cu)-based interconnects integrated with low dielectric constant (low-k) dielectrics to significantly reduce the resistance (R) and capacitance (C) of the chip. Copper has a lower resistivity than aluminum (Al)-based alloys. Therefore, semiconductor devices manufactured using Cu-based interconnects will show reduced resistance-capacitance (RC) delay. However, when a self-passivation layer is not formed to prevent further oxidation of the underlying copper, the oxidation rate of copper is high. Oxidation of Cu-based interconnects becomes a serious problem in the reliability of subsequent bumping processes.

[0003] Therefore, a new semiconductor structure with improved reliability is desired. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes an interconnect structure, a passivation layer and a conductive bump structure. The interconnect structure includes a conductive pad located on the top of the interconnect structure. The passivation layer is disposed on the interconnect structure. The conductive bump structure is disposed in and embedded in the passivation layer and the conductive pad. In a first direction, a first interface between the passivation layer and the conductive pad is located and is not aligned with a second interface between the conductive bump structure and the conductive pad.

[0005] In addition, an embodiment of the present invention provides a method for forming a semiconductor structure. The method includes forming an interconnect structure, including a conductive pad located on top of the interconnect structure. The method further includes forming a passivation layer on the interconnect structure. The method further includes forming a first opening through the passivation layer to expose the top surface of the conductive pad. The method further includes performing a surface treatment process to form a groove of the conductive pad, which is recessed from the exposed top surface of the conductive pad. The method further includes forming a conductive bump structure on the passivation layer, filling the first opening and the groove of the conductive pad. In a first direction, a first interface between the passivation layer and the conductive pad is located next to and misaligned with a second interface between the conductive bump structure and the conductive pad.

[0006] Since the exposed conductive pad needs to be subjected to a surface treatment process in the solution of the embodiment of the present invention, a unique groove of the conductive pad is formed accordingly. The subsequent conductive bump structure can be further embedded in the conductive pad to enhance the shear strength of the conductive bump structure, thereby improving the reliability of the conductive bump structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be more fully understood by reading the following detailed description and referring to the accompanying drawings, in which:

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0009] Figure 2 yes Figure 1 A partial enlarged view of

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0011] Figure 4 yes Figure 3 A partial enlarged view of

[0012] Figure 5 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0013] Figure 6 yes Figure 5 A partial enlarged view of

[0014] Figure 7 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0015] Figure 8 yes Figure 7 A partial enlarged view of

[0016] Fig. 9 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0017] Fig.10 yes Fig. 9 A partial enlarged view of

[0018] Fig.11 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure;

[0019] Fig.12 yes Fig.11 A partial enlarged view of

[0020] Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 According to some embodiments of the present disclosure, Figure 1 and Figure 4 A schematic cross-sectional view of an intermediate stage of a semiconductor structure;

[0021] Fig.19 According to some embodiments of the present disclosure, Figure 3 and Fig. 9 A schematic cross-sectional view of an intermediate stage of a semiconductor structure;

[0022] Fig. 20 According to some embodiments of the present disclosure, Figure 5 and Fig.11 Schematic cross-sectional view of an intermediate stage of a semiconductor structure. DETAILED DESCRIPTION

[0023] The following description is intended to illustrate the general principles of the invention and should not be taken as limiting. The scope of the invention is best determined by reference to the appended claims.

[0024] Copper (Cu) pads are widely used in advanced semiconductor devices. Compared with aluminum (Al) pads, copper pads have lower parasitic resistance-capacitance (RC) values, thereby improving performance. However, when semiconductor wafers or chips are stored for a long time before forming a bump structure, oxidation of the copper pads may affect the reliability of the bump structure, thereby affecting the manufacturing quality of the semiconductor device. Therefore, a new semiconductor structure with improved bump structure reliability is desirable.

[0025] Figure 1 is a schematic cross-sectional view of a semiconductor structure 500A according to some embodiments of the present disclosure. Figure 2 yes Figure 1 . In some embodiments, the semiconductor structure 500A includes a semiconductor device, such as a printed circuit board (PCB), connected to a substrate (not shown) using a conductive bump structure. The semiconductor structure 500A may include a semiconductor device 250 and a conductive bump structure 240 electrically connected to the semiconductor device 250. In some embodiments, the semiconductor device includes a semiconductor chip, a passive component, a package, or a wafer-level package. In some embodiments, the semiconductor device 250 may include a substrate 200, an interconnect structure 220, a first passivation layer 224, and a conductive pad 226. The semiconductor structure 500A may also include a second passivation layer 228 and a conductive bump structure 240 located on the semiconductor device 250.

[0026] In some embodiments, the substrate 200 may include, but is not limited to, a semiconductor substrate. The substrate 200 may be used to manufacture a circuit element 202 on the active surface of the substrate 200. In some embodiments, the circuit element 202 may include an active device, a passive device, or other applicable devices. The interconnect structure 220 is formed on the substrate 200, covering the circuit element 202. In some embodiments, the interconnect structure 220 provides an electrical transmission path for the circuit element 202. In some embodiments, the interconnect structure 220 includes a redistribution layer (RDL) structure having multiple metal layers, multiple dielectric layers alternately stacked with metal layers, and multiple through holes formed in the dielectric layer on the substrate 200. For example, the dielectric layer of the interconnect structure 220 may be an ultra-low dielectric constant (ELK) dielectric layer. For example, the metal layer of the interconnect structure 220 may include, but is not limited to, copper or its alloy.

[0027] The first passivation layer 224 is disposed on the substrate 200. The first passivation layer 224 is the uppermost dielectric layer of the interconnect structure 220 and provides protection for the underlying circuit element 202. In some embodiments, the first passivation layer 224 may include an organic or inorganic dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, polybenzoxazole (PBO), benzocyclobutene (BCB), etc., or a combination thereof.

[0028] Conductive pad 226 is located at the top of interconnect structure 220. Conductive pad 226 is disposed on first passivation layer 224. In other words, first passivation layer 224 is located below bottom surface 226BS of conductive pad 226. In addition, conductive pad 226 belongs to the uppermost metal layer of interconnect structure 220. In addition, top surface 226TS of conductive pad 226 may be a plane. In some embodiments, conductive pad 226 is used to transmit input / output (I / O), ground or power supply signals of semiconductor device 250. In some embodiments, conductive pad 226 may include copper (Cu) or its alloy.

[0029] In some embodiments, the conductive pad 226 has a groove 227 recessed from the top surface 226TS of the conductive pad 226. The groove 227 may be located at the center of the conductive pad 226. Figure 1 As shown, the groove 227 has a bottom surface 227BS and opposite side surfaces 227S1 and 227S2. The bottom surface 227BS of the groove 227 is surrounded by the top surface 226TS of the conductive pad 226. In addition, the side surfaces 227S1 and 227S2 are connected between the top surface 226TS of the conductive pad 226 and the bottom surface 227BS of the groove 227.

[0030] In some embodiments, the depth H1 of the groove 227 is between about 0.02 μm and 3 μm relative to the thickness T2 of the conductive pad 226, the thickness T2 of the conductive pad 226 is between about 1.5 μm and 3 μm, and the direction 110 is substantially perpendicular to the top surface 226TS of the conductive pad 226. In some embodiments, the ratio of the thickness T2 of the conductive pad 226 to the depth H1 of the groove 227 (i.e., T2 / H1) is between 1 and 75.

[0031] In some embodiments, the bottom surface 227BS of the groove 227 includes a flat surface or a concave surface. Figure 1 As shown, an angle C1 between a side surface 227S1 and a bottom surface 227BS of the groove 227 and an angle C2 between a side surface 227S2 and a bottom surface 227BS may include a sharp angle or a rounded angle.

[0032] The second passivation layer 228 is disposed on the top of the interconnect structure 220. The second passivation layer 228 may cover the first passivation layer 224 and a portion of the conductive pad 226. The second passivation layer 228 may provide protection for the underlying conductive pad 226. In addition, a top surface 228TS of the second passivation layer 228 may be planar.

[0033] In some embodiments, the second passivation layer 228 has an opening 230. The opening 230 is directly located on the groove 227 of the conductive pad 226 to define a formation position of a subsequent conductive bump structure 240. In addition, the opening 230 is formed through the second passivation layer 228 to expose the groove 227 of the conductive pad 226.

[0034] exist Figure 1 In some embodiments shown, a portion of the groove 227 of the conductive pad 226 may be exposed from the opening 230 of the second passivation layer 228. That is, the groove 227 of the conductive pad 226 may cut a portion of the second passivation layer 228 above the top surface 226TS of the conductive pad 226. In this embodiment, the second passivation layer 228 includes opposing protruding portions 228-P1 and 228-P2 located above the top surface 226TS of the conductive pad 226. The protruding portion 228-P1 may protrude from the top surface 226TS and extend along the direction 100 to be located above a portion of the corresponding side 227S1 and bottom surface 227BS of the groove 227. The protruding portion 228-P1 may overhang the groove 227. In addition, the protruding portion 228-P2 may protrude from the top surface 226TS and extend along the direction 100 to be located above a portion of the corresponding side 227S2 and bottom surface 227BS of the groove 227. The protrusion 228-P1 may overhang the groove 227. Figure 1As shown, the protrusion 228-P1, the corresponding side surface 227S1, and a portion of the bottom surface 227BS of the groove 227 overlapping the protrusion 228-P1 may form a side portion 227P1 of the groove 227. In addition, the protrusion 228-P2, the corresponding side surface 227S2, and a portion of the bottom surface 227BS of the groove 227 overlapping the protrusion 228-P2 may form a side portion 227P2 of the groove 227. Except for the side portions 227P1 and 227P2, the rest of the groove 227 may serve as a vertical portion of the groove 227.

[0035] In some embodiments, if the groove 227 does not include the side portions 227P1 and 227P2, the entire groove 227 of the conductive pad 226 may be exposed from the opening 230 of the second passivation layer 228. The side surfaces 227S1 and 227S2 may be aligned with opposite sidewalls of the opening 230.

[0036] like Figure 1 and Figure 2 As shown, the side portions 227P1 and 227P2 of the groove 227 extend along the direction 100 (ie, the transverse direction). In some embodiments, the side portions 227P1 and 227P2 of the groove 227 have a circular, polygonal, fan-shaped, strip-shaped or irregular shape in a cross-sectional view, such as Figure 1 shown.

[0037] In some embodiments, the dimension LD1 of the protruding portion 228-P1 and the dimension LD2 of the protruding portion 228-P2 are both between 0.01 μm and 3 μm in the direction 100. If the dimension LD1 (or the dimension LD2) is greater than 3 μm, a seed layer (e.g., a seed layer of the under-bump metallization (UBM) layer 241) of the subsequent conductive bump structure 240 formed by a deposition process may form a discontinuous layer when lining the side portion 227P2 of the groove 227. In addition, after the conductive bump structure 240 is filled by an electroplating process, a micro-void may be formed at the innermost side of the side portion 227P2 of the groove 227. The discontinuous seed layer and / or micro-void may become an initial crack source and propagate to the interface after long-term electrical stress, resulting in delamination, affecting the reliability of the final semiconductor structure 500A. In some embodiments, the ratio of the dimension LD1 to the dimension LD2 (i.e., LD1 / LD2) is between 0.03 and 3, or vice versa.

[0038] In some embodiments, the second passivation layer 228 may be a multi-layer structure including silicon oxide, silicon nitride, silicon oxynitride, polybenzoxazole (PBO), benzocyclobutene (BCB), etc., or a combination thereof.

[0039] The conductive bump structure 240 is disposed on the second passivation layer 228 and the conductive pad 226. In addition, the conductive bump structure 240 is formed through the opening 230 and connected to the conductive pad 226. Figure 1 As shown, the conductive bump structure 240 is embedded in the second passivation layer 228 and the conductive pad 226. The conductive bump structure 240 may contact the bottom surface 227BS and the opposite side surfaces 227S1, 227S2 of the groove 270 of the conductive pad 226. In addition, the conductive bump structure 240 may fill the side portions 227P1 and 227P2 of the groove 227. In some embodiments, the conductive bump structure 240 may be mushroom-shaped or hourglass-shaped in a cross-sectional view, such as Figure 1 and Figure 2 shown.

[0040] In some embodiments, in direction 100, the interface F1 between the second passivation layer 228 and the conductive pad 226 is located beside and offset from the interface F2 between the conductive bump structure 240 and the conductive pad 226. For example, the interface F1 may be located on the top surface 226TS of the conductive pad 226. In addition, the interface F2 may be located on the bottom surface 227BS of the groove 227 of the conductive pad 226.

[0041] like Figure 1 As shown, in direction 110, the distance between interface F1 and interface F2 may be the same as the depth H1 of groove 227. Therefore, in direction 110, the ratio of thickness T2 of conductive pad 226 to distance H1 between interface F1 and interface F2 (ie, T2 / H1) may be between 1 and 75.

[0042] In some embodiments, the conductive bump structure 240 has an embedded portion 240EP embedded in the second passivation layer 228 and the conductive pad 226. In addition, the embedded portion 240EP may be adjacent to the protruding portions 228-P1 and 228-P2 of the second passivation layer 228. In some embodiments, the embedded portion 240EP of the conductive bump structure 240 has a columnar, inverted hammer, or anchor shape in a cross-sectional view. For example, Figure 1 As shown, the embedded portion 240EP of the conductive bump structure 240 may have an inverted hammer shape or an anchor shape.

[0043] In some embodiments, the embedded portion 240EP of the conductive bump structure 240 includes sub-portions 240EP1 and 240EP2. The sub-portion 240EP1 may be embedded in the second passivation layer 228. The sub-portion 240EP2 may be embedded in the conductive pad 226. In the direction 100, the sub-portion 240EP1 may have a size LD3 and the sub-portion 240EP2 may have a size LD4. In some embodiments, the size LD3 is equal to the size of the opening 230 of the second passivation layer 228. The size LD4 is greater than or equal to the size LD3. In addition, the portion of the conductive bump structure 240 protruding from the top surface 228TS of the second passivation layer 228 may have a size LD5 greater than or equal to the size LD3. In some embodiments, the sub-portion 240EP1 may serve as a narrow neck portion of the conductive bump structure 240.

[0044] In some embodiments, the conductive bump structure 240 includes a micro bump, a copper pillar bump, a controlled collapse chip connection (C4) bump, the like, or a combination thereof. For example, the conductive bump structure 240 may include an under bump metallurgy (UBM) 241 located on the conductive pad 226, a conductive pillar 244 located on the bump metal layer 241, and a solder cap 246 located on the conductive pillar 244.

[0045] like Figure 1 As shown, the bump metal layer (UBM) 241 of the conductive bump structure 240 passes through the opening 230 of the second passivation layer 228 and covers the conductive pad 226. The bump metal layer (UBM) 241 can line the opening 230 of the second passivation layer 228 and fill the groove 227 in the conductive pad 226. The bump metal layer (UBM) 241 can also extend to the top surface 228TS of the second passivation layer 228. In some embodiments, the bump metal layer (UBM) 241 includes a seed layer (not shown), such as a pure copper (Cu) layer, a pure titanium (Ti) layer, a Ti / Cu layer, a TiW / Cu layer, any other metal layer and a combination thereof. In some other embodiments, the seed layer of the bump metal layer (UBM) 241 includes a titanium nitride (TiN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer, a silver (Ag) layer, a gold (Au) layer, an aluminum (Al) layer and a combination thereof. In some other embodiments, the bump metal layer (UBM) 241 includes a nickel (Ni) layer formed on the seed layer. In some embodiments, the bump metal layer (UBM) 241 is formed by a deposition method including physical vapor deposition (PVD), such as sputtering or electroplating methods.

[0046] The conductive pillar 244 of the conductive bump structure 240 is formed on the bump metal layer (UBM) 241 and fills the opening 230 of the second passivation layer 228, as shown in FIG. Figure 1As shown, according to some embodiments of the present disclosure. In addition, the size of the portion of the conductive pillar 244 above the second passivation layer 228 can be the same as the size LD5. In some embodiments, the conductive pillar 244 and the seed layer of the bump metal layer (UBM) 241 can include the same material, such as copper (Cu). In some embodiments, the conductive pillar 244 is formed by a photolithography process and a subsequent electroplating process.

[0047] The solder cap 246 is formed on the conductive pillar 244 through a solder plating process or a screen printing process, a photoresist stripping process, and a solder reflow process.

[0048] In some embodiments, the embedded portion 240EP includes an under bump metallurgy (UBM) 241 and a conductive pillar 244. Figure 1 As shown, the sub-portion 240EP1 may be formed of a bump metal layer (UBM) 241 and a conductive pillar 244. In addition, the sub-portion 240EP2 may be formed of a bump metal layer (UBM) 241.

[0049] Figure 3 is a schematic cross-sectional view of a semiconductor structure 500B according to some embodiments of the present disclosure. Figure 4 yes Figure 3 For the sake of simplicity, the components in the following embodiments are the same as those in the previous reference. Figure 1 and Figure 2 The same or similar elements described above will not be described again. Figure 3 and Figure 4 As shown, the difference between the semiconductor structure 500A and the semiconductor structure 500B at least includes that the semiconductor structure 500B further includes a photosensitive stress buffer layer 236A. In some embodiments, the photosensitive stress buffer layer 236A is used to provide reliable insulation when the semiconductor device 250 is subjected to various types of environmental stress.

[0050] The photosensitive stress buffer layer 236A may be conformally formed on the second passivation layer 228. In some embodiments, the photosensitive stress buffer layer 236A may extend from the top surface 228TS of the second passivation layer 228 into the opening 230. More specifically, the photosensitive stress buffer layer 236A lines the opening 230. The photosensitive stress buffer layer 236A contacts the under-bump metal layer (UBM) 241. In addition, a sub-portion 240EP1 of the embedded portion 240EP of the conductive bump structure 240 is surrounded by the photosensitive stress buffer layer 236A. The second passivation layer 228 and the photosensitive stress buffer layer 236A may cover different portions 240EP2 of the embedded portion 240EP of the conductive bump structure 240. Figure 3As shown, the conductive pillar 244 may be separated from the second passivation layer 228 by the photosensitive stress buffer layer 236A. In addition, the photosensitive stress buffer layer 236A is spaced apart from the conductive pad 226.

[0051] like Figure 3 As shown, the photosensitive stress buffer layer 236A has an opening 238A to expose the groove 227 of the conductive pad 226. In some embodiments, the opening 238A of the photosensitive stress buffer layer 236A is located within and aligned with the opening 230 of the second passivation layer 228. In the direction 100 substantially parallel to the top surface 226TS of the conductive pad 226, the size LD3 of the sub-portion 240EP1 may be equal to the size of the opening 238A and smaller than the size of the opening 230.

[0052] In some embodiments, the photosensitive stress buffer layer 236A may include polyimide or other applicable photosensitive materials. In some embodiments, the photosensitive stress buffer layer 236A is formed by a coating process, a photolithography process, and a subsequent curing process. In this embodiment, the photosensitive stress buffer layer 236A of the semiconductor structure 500B may have a PI (polyimide) pull-in structure because the photosensitive stress buffer layer 236A is pulled into the opening 230 of the second passivation layer 228.

[0053] Figure 5 is a schematic cross-sectional view of a semiconductor structure 500C according to some embodiments of the present disclosure. Figure 6 yes Figure 5 For the sake of simplicity, the components in the following embodiments are the same as those in the previous reference. Figures 1 to 4 The same or similar elements described above will not be described again. Figure 5 and Figure 6 As shown, the difference between the semiconductor structure 500B and the semiconductor structure 500C at least includes that the semiconductor structure 500C further includes a photosensitive stress buffer layer 236B.

[0054] In this embodiment, the photosensitive stress buffer layer 236B is located above the opening 230 of the second passivation layer 228. The conductive pillar 244 of the conductive bump structure 240 may be surrounded by the photosensitive stress buffer layer 236B. The photosensitive stress buffer layer 236B may not extend into the opening 230. More specifically, the photosensitive stress buffer layer 236B may be spaced apart from the opening 230 of the second passivation layer 228. In addition, the photosensitive stress buffer layer 236B is spaced apart from the conductive pad 226 and the embedded portion 240EP of the conductive bump structure 240. Figure 5 As shown, a portion of the conductive bump structure 240 above the embedded portion 240EP may contact the photo-sensitive stress buffer layer 236B and the second passivation layer 228 .

[0055] like Figure 5As shown, the photosensitive stress buffer layer 236B has an opening 238B to expose the groove 227 of the conductive pad 226 and is located in the opening 230 of the second passivation layer 228. In some embodiments, the opening 230 of the second passivation layer 228 is located in and aligned with the opening 238B of the photosensitive stress buffer layer 236B in a direction 110 substantially perpendicular to the top surface 226TS of the conductive pad 226. In a direction 100 substantially parallel to the top surface 226TS of the conductive pad 226, the size of the opening 238B may be larger than the size LD3 of the sub-portion 240EP1 and smaller than the size LD5 of the portion of the conductive bump structure 240 protruding from the top surface 228TS of the second passivation layer 228.

[0056] In some embodiments, the photosensitive stress buffer layer 236A ( Figure 3 ) may be similar or the same as the process and material used to form the photosensitive stress buffer layer 236B. In this embodiment, the photosensitive stress buffer layer 236B of the semiconductor structure 500C may have a PI (polyimide) pull-out structure because the photosensitive stress buffer layer 236B pulls out the opening 230 of the second passivation layer 228.

[0057] Figure 7 is a schematic cross-sectional view of a semiconductor structure 500D according to some embodiments of the present disclosure. Figure 8 yes Figure 7 For the sake of simplicity, the components in the following embodiments are the same as those in the previous reference. Figures 1 to 6 The same or similar elements described above will not be described again. Figure 7 and Figure 8 As shown, the difference between the semiconductor structure 500A and the semiconductor structure 500D at least includes that the semiconductor structure 500D uses the conductive bump structure 340 to replace the conductive bump structure 240 of the semiconductor structure 500A.

[0058] In some embodiments, in direction 100, the interface F1 between the second passivation layer 228 and the conductive pad 226 is located beside and offset from the interface F3 between the conductive bump structure 340 and the conductive pad 226. For example, the interface F1 may be located on the top surface 226TS of the conductive pad 226. In addition, the interface F3 may be located on the bottom surface 227BS of the groove 227 of the conductive pad 226.

[0059] like Figure 7 As shown, in the direction 110, the distance between the interface F1 and the interface F3 may be the same as the depth H1 of the groove 227. Therefore, in the direction 110, the ratio of the thickness T2 of the conductive pad 226 to the distance (H1) between the interface F1 and the interface F3 (i.e., T2 / H1) may be between 1 and 75.

[0060] In some embodiments, the conductive bump structure 340 has an embedded portion 340EP embedded in the second passivation layer 228 and the conductive pad 226. In addition, the embedded portion 340EP may be adjacent to the protruding portions 228-P1 and 228-P2 of the second passivation layer 228. In some embodiments, the embedded portion 340EP of the conductive bump structure 340 has a pillar shape, an inverted hammer shape, or an anchor shape. For example, Figure 4 As shown, the embedded portion 340EP of the conductive bump structure 340 may have an inverted hammer shape or an anchor shape.

[0061] In some embodiments, the embedded portion 340EP of the conductive bump structure 240 includes sub-portions 340EP1 and 340EP2. The sub-portion 340EP1 may be embedded in the second passivation layer 228. The sub-portion 340EP2 may be embedded in the conductive pad 226. In the direction 100, the sub-portion 340EP1 may have a dimension LD6, and the sub-portion 340EP2 may have a dimension LD7. In some embodiments, the dimension LD6 is equal to the dimension of the opening 230 of the second passivation layer 228. The dimension LD7 is greater than or equal to the dimension LD6. In addition, the portion of the conductive bump structure 340 protruding from the top surface 228TS of the second passivation layer 228 may have a dimension LD8 greater than or equal to the dimension LD6. In some embodiments, the sub-portion 340EP1 may serve as a narrow neck portion of the conductive bump structure 340.

[0062] like Figure 7 As shown, the conductive bump structure 340 , such as the ENEPIG bump structure, may include a base layer 341 on the conductive pad 226 , a buffer layer 344 on the base layer 341 , and a final outer layer 346 on the buffer layer 344 .

[0063] like Figure 7 As shown, the base layer 341 forms the opening 230 through the second passivation layer 228 and fills the groove 227 of the conductive pad 226. The embedded portion 340EP of the conductive bump structure 340 is composed of the base layer 341. The base layer 341 may protrude from the top surface 228TS of the second passivation layer 228. In addition, the top surface 341TS of the base layer 341 is flat.

[0064] like Figure 7 As shown, the buffer layer 344 is formed over the second passivation layer 228 and contacts the top surface 341TS of the base layer 341. In the direction 110, the thickness T3 of the base layer 341 is greater than the thickness T4 of the buffer layer 344. The top surface 344TS of the buffer layer 344 is a plane.

[0065] like Figure 7As shown, final outer layer 346 is formed over second passivation layer 228 and contacts top surface 344TS of buffer layer 344. In direction 110, thickness T3 of base layer 341 is greater than thickness T5 of final outer layer 346. Top surface 346TS of final outer layer 346 is planar.

[0066] In some embodiments, the base layer 341, the buffer layer 344, and the final outer layer 346 are made of different metal materials. For example, when the conductive bump structure 340 includes an ENEPIG bump structure, the base layer 341 is made of chemically plated nickel (Ni), the buffer layer 344 is made of chemically plated palladium (Pd), and the final outer layer 346 is made of immersion gold (Au). The nickel base layer 341 can avoid migration and diffusion between the conductive pad 226 made of Cu and the final outer layer 346 made of Au. The palladium buffer layer 344 can prevent the gold atoms of the final outer layer 346 from replacing the nickel atoms of the base layer 341. The gold final outer layer 346 can have low contact resistance and provide friction protection and oxidation resistance.

[0067] Fig. 9 is a schematic cross-sectional view of a semiconductor structure 500E according to some embodiments of the present disclosure. Fig.10 yes Fig. 9 For the sake of simplicity, the components in the following embodiments are the same as those in the previous reference. Figures 1 to 8 The same or similar elements described above will not be described again. Fig. 9 and Fig.10 As shown, the difference between the semiconductor structure 500D and the semiconductor structure 500E at least includes that the semiconductor structure 500E further includes a photosensitive stress buffer layer 236A. In some embodiments, the photosensitive stress buffer layer 236A of the semiconductor structures 500B and 500E may have the same or similar position, structure, material, and process.

[0068] The photosensitive stress buffer layer 236A may be conformally formed on the second passivation layer 228. In some embodiments, the photosensitive stress buffer layer 236A may extend from the top surface 228TS of the second passivation layer 228 into the opening 230. More specifically, the photosensitive stress buffer layer 236A lines the opening 230. The photosensitive stress buffer layer 236A contacts the base layer 341. In addition, a sub-portion 340EP1 of the embedded portion 340EP of the conductive bump structure 340 is surrounded by the photosensitive stress buffer layer 236A. The photosensitive stress buffer layer 236A and the second passivation layer 228 may cover a different portion 340EP2 of the embedded portion 340EP of the conductive bump structure 340.

[0069] like Fig. 9As shown, the photosensitive stress buffer layer 236A has an opening 238A to expose the groove 227 of the conductive pad 226. In some embodiments, the opening 238A of the photosensitive stress buffer layer 236A is located within and aligned with the opening 230 of the second passivation layer 228. In the direction 100 substantially parallel to the top surface 226TS of the conductive pad 226, the dimension LD6 of the sub-portion 340EP1 may be equal to the dimension of the opening 238A and smaller than the dimension of the opening 230.

[0070] In the present embodiment, the photosensitive stress buffer layer 236A of the semiconductor structure 500E may have a PI (polyimide) pull-in structure because the photosensitive stress buffer layer 236A is pulled into the opening 230 of the second passivation layer 228 .

[0071] Fig.11 is a schematic cross-sectional view of a semiconductor structure 500F according to some embodiments of the present disclosure. Fig.12 yes Fig.11 For the sake of simplicity, the components in the following embodiments are the same as those in the previous reference. Figures 1 to 10 The same or similar elements described above will not be described again. Fig.11 and Fig.12 As shown, the difference between the semiconductor structure 500E and the semiconductor structure 500F at least includes that the semiconductor structure 500F further includes a photosensitive stress buffer layer 236B. In some embodiments, the photosensitive stress buffer layer 236A of the semiconductor structures 500C and 500F may have the same or similar position, structure, material, and process.

[0072] In some embodiments, the photosensitive stress buffer layer 236B is located above the opening 230 of the second passivation layer 228. The base layer 241 of the conductive bump structure 340 may be surrounded by the photosensitive stress buffer layer 236B. The photosensitive stress buffer layer 236B may not extend into the opening 230. More specifically, the photosensitive stress buffer layer 236B may be spaced apart from the opening 230 of the second passivation layer 228. In addition, the photosensitive stress buffer layer 236B is spaced apart from the conductive pad 226 and the embedded portion 340EP of the conductive bump structure 340. Fig.11 As shown, a portion of the conductive bump structure 340 above the embedded portion 340EP may contact the photo-sensitive stress buffer layer 236B and the second passivation layer 228 .

[0073] like Fig.11As shown, the photosensitive stress buffer layer 236B has an opening 238B to expose the groove 227 of the conductive pad 226 and is located in the opening 230 of the second passivation layer 228. In some embodiments, the opening 230 of the second passivation layer 228 is located in and aligned with the opening 238B of the photosensitive stress buffer layer 236B in a direction 110 substantially perpendicular to the top surface 226TS of the conductive pad 226. In a direction 100 substantially parallel to the top surface 226TS of the conductive pad 226, the size of the opening 238B may be larger than the size LD6 of the sub-portion 340EP1 and smaller than the size LD8 of the portion of the conductive bump structure 340 protruding from the top surface 228TS of the second passivation layer 228.

[0074] Since the conductive pad 236 of the semiconductor structures 500A to 500F has a unique groove 227, the subsequent conductive bump structure 240 (or conductive bump structure 340) may have an embedded portion 240EP (or embedded portion 340EP) further embedded in the conductive pad 226 to enhance the shear strength of the conductive bump structure 240 (or conductive bump structure 340), thereby improving the reliability of the conductive bump structure 240 (or conductive bump structure 340).

[0075] A method of forming the semiconductor structures 500A and 500D will be described. Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 According to some embodiments of the present disclosure, Figure 1 The semiconductor structure 500A (or Figure 7 For the sake of simplicity, the elements in the following embodiments are similar to those in the previous reference. Figures 1 to 12 The description of the same or similar elements will not be repeated.

[0076] See also Fig.13 , a substrate 200 is provided. Next, a circuit element 202 is formed on the substrate 200. Next, an interconnection structure 220 is formed on the substrate 200 and the circuit element 202. The interconnection structure 220 may include a conductive pad 226 located on the top of the interconnection structure 220 and electrically connected to the circuit element 202. Thus, a semiconductor device 250 is formed. Fig.13 As shown, the top surface 226TS of the conductive pad 226 is convex.

[0077] Next, a second passivation layer 228 ( Figure 1 ) of the lower portion 228-1. The second passivation layer 228 ( Figure 1) may completely cover the top surface 226TS of the conductive pad 226 and the top surface 224TS of the first passivation layer 224 exposed from the conductive pad 226.

[0078] See also Fig.14 Next, a planarization process is performed to remove the second passivation layer 228 ( Figure 1 ) and a portion of the lower portion 228-1 of the conductive pad 226 to planarize the second passivation layer 228 ( Figure 1 ) and the top of the conductive pad 226. Fig.14 As shown, after the planarization process, the top surface 226TS of the conductive pad 226 is a plane flush with the top surface 228-1TS of the lower portion 228-1 of the second passivation layer 228. More specifically, after the planarization process, the top surface 226TS of the conductive pad 226 and the top surface 228-1TS of the lower portion 228-1 of the second passivation layer 228 are both flush planes. Therefore, Fig.14 The top surface of the intermediate semiconductor structure shown (including the top surface 226TS of the conductive pad 226 and the top surface 228-1TS of the lower portion 228-1 of the second passivation layer 228) is planar. In some embodiments, the planarization process includes chemical mechanical polishing (CMP).

[0079] See also Fig.15 , next, another deposition process is performed to form an upper portion 228-2 of the second passivation layer 228 covering the lower portion 228-1 of the second passivation layer 228 and the top surface 226TS of the conductive pad 226. Therefore, the second passivation layer 228 includes a lower portion 228-1 and an upper portion 228-2 located on the lower portion 228-1, and is formed on the interconnect structure 220. In addition, the top surface of the upper portion 228-2 of the second passivation layer 228 can serve as the top surface 228TS of the second passivation layer 228. In some embodiments, the thickness of the upper portion 228-2 of the second passivation layer 228 can serve as the thickness T1 of the second passivation layer 228 above the top surface 226TS of the conductive pad 226, ranging from about 5 μm to 25 μm. Due Fig.14 The top surface of the intermediate semiconductor structure shown is a plane, and the upper portion 228-2 of the second passivation layer 228 forms a flat top surface after the deposition process. In some embodiments, the lower portion 228-1 and the upper portion 228-2 of the second passivation layer 228 can have the same or similar materials and manufacturing processes. Therefore, the lower portion 228-1 and the upper portion 228-2 of the second passivation layer 228 can form an integral passivation layer without an interface.

[0080] See also Fig.16 Next, a patterning process is performed to form a second passivation layer 228 (ie, Fig.15An opening 230 is formed in the upper portion 228-2 of the second passivation layer 228. The opening 230 is formed to expose a portion of the top surface 226TS of the conductive pad 226. In some embodiments, the patterning process includes a photolithography process and a subsequent anisotropic etching process, such as dry etching.

[0081] Fig.17 It is shown that oxide 226OX is formed on conductive pad 226. Fig.16 When the intermediate semiconductor structure 400 shown is in long queue storage before performing a subsequent bumping process, a portion of the top surface 226TS of the conductive pad 226 exposed from the opening 230 may be oxidized to form an oxide 226OX.

[0082] When Fig.16 or Fig.17 The intermediate semiconductor structure 400 shown is to be subjected to a bumping process, such as Fig.18 As shown, the conductive pad 226 exposed from the opening 230 is subjected to a surface treatment process 1000. The surface treatment process 1000 may remove Fig.17 Any possible oxide 226OX on the exposed conductive pad 226 shown. In addition, the surface treatment process 1000 can also remove a portion of the exposed conductive pad 226 to form a groove 227 of the conductive pad 226. The groove 227 of the conductive pad 226 is recessed from the top surface 226TS of the conductive pad 226 exposed by the opening 230. In some embodiments, the opposite side surfaces 227S1 and 227S2 of the groove 227 can have a vertical profile, an overcut profile, or an undercut profile. In the present embodiment, the opposite side surfaces 227S1 and 227S2 of the groove 227 can have a vertical profile or an undercut profile. In some embodiments, the surface treatment process 1000 includes a physical surface treatment process or a chemical surface treatment process. For example, the physical surface treatment process can include dry etching. The chemical surface treatment process can include wet cleaning.

[0083] See also Figure 1 Next, a bump process is performed to form a conductive bump structure 240 on the second passivation layer 228. The conductive bump structure 240 forms a groove 227 that fills the opening 300 and the conductive pad 226. In addition, the conductive bump structure 240 is connected to the conductive pad 226. In some embodiments, the bump process includes integrally forming a bump metallization (UBM) layer 241 on the second passivation layer 228 by a deposition method. The bump metallization (UBM) layer 241 forms a lining opening 230 and fills the groove 227 of the conductive pad 226.

[0084] like Figure 1As shown, next, the bump process further includes completely forming a photoresist layer (not shown) on the UBM layer 241. In some embodiments, the photoresist layer includes a dry film photoresist or a liquid photoresist. Next, the photoresist layer is patterned by a photolithography process, including an exposure step and a development step to form an opening (not shown) above the conductive pad 226. In some embodiments, the opening defines the diameter and shape of the subsequent conductive column 244.

[0085] like Figure 1 As shown, next, the bump process further includes forming a conductive pillar 244 on the portion of the UBM layer 241 not covered by the photoresist layer pattern. The conductive pillar 244 is formed by electroplating or electrochemical deposition (ECD), fills the opening 230 of the second passivation layer 228 and the opening of the photoresist layer, and covers a portion of the UBM layer 241. Therefore, the conductive pillar 244 is formed by the photoresist layer and is electrically connected to the conductive pad 226 through the UBM layer 241. In some embodiments, the conductive pillar 244 and the seed layer (not shown) of the UBM layer 241 are made of the same material, such as copper (Cu).

[0086] like Figure 1 As shown, next, the bump process further includes forming a solder cap 246 on the conductive pillar 244 through a solder plating process, a photoresist stripping process, and a solder reflow process. After forming the solder cap 246, the conductive bump structure 240 is formed. Therefore, according to some embodiments of the present disclosure, a semiconductor structure 500A is formed.

[0087] Or, in the Fig.16 or Fig.17 The intermediate semiconductor structure 400 is shown to undergo a surface treatment process 1000 ( Fig.18 ), another bump process may be performed to form a conductive bump structure 340 (eg, an ENEPIG bump structure) on the second passivation layer 228, such as Figure 7 As shown, the conductive bump structure 340 forms the groove 227 filling the opening 300 and the conductive pad 226 . In addition, the conductive bump structure 340 is connected to the conductive pad 226 .

[0088] In some embodiments, the bump process includes depositing a base layer 341 on the second passivation layer 228 by an electroless plating method. The base layer 341 forms a groove 227 filling the opening 230 and the conductive pad 226 .

[0089] like Figure 3As shown, next, the bump process further includes depositing a buffer layer 344 on the base layer 341 by a chemical plating method. Next, the bump process further includes depositing a final outer layer 346 on the buffer layer 344 by a chemical plating method. After forming the final outer layer 346, the conductive bump structure 340 is formed. Therefore, according to some embodiments of the present disclosure, a semiconductor structure 500B is formed.

[0090] Fig.19 According to some embodiments of the present disclosure, Figure 3 The semiconductor structure 500B (or Fig. 9 The components in the following embodiments are the same as those in the previous reference. Figures 1 to 18 The same or similar elements described above will not be described repeatedly.

[0091] when Fig.16 or Fig.17 The intermediate semiconductor structure 400 shown will be Fig.18 In the surface treatment process 1000 shown in FIG. 1 , a coating process is performed to conformally form a photosensitive stress buffer material layer 236A on the second passivation layer 228, as shown in FIG. Fig.19 The photosensitive stress buffer layer 236A may cover the top surface 228TS of the second passivation layer 228 and line the opening 230 of the second passivation layer 228. In addition, the photosensitive stress buffer layer 236A may cover the top surface 226TS of the conductive pad 226 exposed from the opening 230 of the second passivation layer 228 ( Fig.16 or Fig.17 ).

[0092] Next, a photolithography process including an exposure step and a development step is performed to form an opening 238A through the photosensitive stress buffer layer 236A, exposing a portion of the conductive pad 226. The photosensitive stress buffer layer 236A is processed by the photolithography process to remove the photosensitive stress buffer layer 236A directly on the portion of the conductive pad 226 in the opening 230, forming the opening 238A. The remaining photosensitive stress buffer layer 236A may cover the top surface 228TS of the second passivation layer 228 and line the opening 230 of the second passivation layer 228.

[0093] Next, the photosensitive stress buffer layer 236A having the opening 238A undergoes a curing process to cure the photosensitive stress buffer layer 236A. After the curing process, the level of the photosensitive stress buffer layer 236A may decrease due to the shrinkage of the photosensitive stress buffer layer.

[0094] Next, proceed Fig.18 The surface treatment process 1000 is shown to form the groove 227 of the conductive pad 226, as shown in FIG. Figure 3 (or Fig. 9 ) as shown.

[0095] Next, if Figure 3 (or Fig. 9 ), similar to Figure 1 (or Figure 7 ) to form a conductive bump structure 240 (or a conductive bump structure 340) on the second passivation layer 228 and the photosensitive stress buffer layer 236A. In addition, the conductive bump structure 240 (or a conductive bump structure 340) passes through the openings 230 and 238A and is connected to the conductive pad 226. After completing the above process, a conductive bump structure 240 (or a conductive bump structure 340) is formed. Figure 3 The semiconductor structure 500B (or as shown in FIG. Fig. 9 The semiconductor structure 500D according to some embodiments of the present disclosure is shown.

[0096] Fig. 20 According to some embodiments of the present disclosure, Figure 5 The semiconductor structure 500C (or Fig.11 The components in the following embodiments are similar to those in the previous reference embodiments. Figures 1 to 19 The same or similar elements described above will not be described repeatedly.

[0097] when Fig.16 or Fig.17 The intermediate semiconductor structure 400 shown will be Fig.18 In the surface treatment process 1000 shown in FIG. 1 , a coating process is performed to conformally form a photosensitive stress buffer layer 236B on the second passivation layer 228, as shown in FIG. Fig. 20 The photosensitive stress buffer layer 236B may cover the top surface 228TS of the second passivation layer 228 and line the opening 230 of the second passivation layer 228. In addition, the photosensitive stress buffer layer 236B may cover the top surface 226TS of the conductive pad 226 exposed from the opening 230 of the second passivation layer 228 ( Fig.16 or Fig.17 ).

[0098] Next, a patterning process including a photolithography process (including an exposure step and a development step) is performed to form an opening 238B through the photosensitive stress buffer layer 236B, exposing a portion of the conductive pad 226 in the opening 230 and a portion of the second passivation layer 228 in the opening 238B. The portion of the photosensitive stress buffer layer 236B lining the opening 230 along the second passivation layer 228 and the photosensitive stress buffer layer 236B directly on the portion of the conductive pad 226 in the opening 230 are removed by the photolithography process to form the opening 238B.

[0099] Next, proceed Fig.18The surface treatment process 1000 is shown to form the groove 227 of the conductive pad 226, as shown in FIG. Figure 5 (or Fig.11 ) as shown.

[0100] Next, if Figure 5 (or Fig.11 ), similar to Figure 1 (or Figure 7 ) to form a conductive bump structure 240 (or a conductive bump structure 340) on the second passivation layer 228 and the photosensitive stress buffer layer 236B. In addition, the conductive bump structure 240 (or a conductive bump structure 340) passes through the openings 230 and 238B and is connected to the conductive pad 226. After completing the above process, a conductive bump structure 240 (or a conductive bump structure 340) is formed. Figure 5 The semiconductor structure 500C (or as shown in FIG. Fig.11 The semiconductor structure 500F shown in FIG. 5 is according to some embodiments of the present disclosure.

[0101] Embodiments provide a semiconductor structure. According to some embodiments of the present disclosure, the semiconductor structure includes an interconnect structure, a topmost passivation layer, and a conductive bump structure. The conductive bump structure is disposed on and embedded in the topmost passivation layer and the conductive pad. In a first direction, substantially parallel to the top surface of the conductive pad, a first interface between the topmost passivation layer and the conductive pad is located next to and misaligned with a second interface between the conductive bump structure and the conductive pad.

[0102] When the intermediate semiconductor structure is to be bumped after long-term queue storage, the exposed conductive pad made of copper may be subjected to a surface treatment process. The surface treatment process includes dry etching (physical) or wet cleaning (chemical), which may remove any possible oxide on the exposed conductive pad. The surface treatment process may further remove a portion of the exposed conductive pad to form a visible and irregular groove recessed from the top surface of the conductive pad exposed from the opening of the top passivation layer.

[0103] In some embodiments, in a second direction substantially perpendicular to a top surface of the conductive pad, a ratio of a first thickness of the conductive pad to a first distance between the first interface and the second interface is between 1 and 75.

[0104] In some embodiments, the groove of the conductive pad has a first bottom surface, a first side surface, and a second side surface. The first bottom surface is surrounded by the first top surface. The first and second side surfaces are opposite and connect the first top surface of the conductive pad and the first bottom surface of the groove. In some embodiments, the first interface is located between the passivation layer and the first top surface of the conductive pad, and the second interface is located between the first bottom surface of the conductive pad groove and the conductive bump structure. In some embodiments, the conductive bump structure contacts the first bottom surface, the first side surface, and the second side surface of the groove. In some embodiments, the first bottom surface of the groove includes a plane or a concave surface. In some embodiments, the first angle between the first side surface and the first bottom surface of the groove includes a sharp angle or a rounded angle.

[0105] In some embodiments, the passivation layer includes a first protrusion and a second protrusion opposite to each other. The first protrusion protrudes from the first top surface and is located above the first side surface and the first bottom surface. The second protrusion protrudes from the first top surface and is located above the second side surface and the first bottom surface of the groove.

[0106] In some embodiments, the embedded portion is adjacent to the first protruding portion and the second protruding portion. In some embodiments, in the first direction, the third dimension of the first protruding portion and the fourth dimension of the second protruding portion are between 0.01 μm and 3 μm. In some embodiments, the ratio of the third dimension to the fourth dimension is between 0.03 and 3.

[0107] In some embodiments, the first and second sides of the groove have a vertical profile or an undercut profile below the top passivation layer and / or the photosensitive stress buffer layer. In some embodiments, the first extension portion, the first side, and the first bottom portion overlapping the first extension portion form a side portion of the groove. In some embodiments, the conductive bump structure fills the side portion of the groove. In some embodiments, the side portion of the groove has a circular, polygonal, fan-shaped, strip-shaped, or irregular shape.

[0108] In some embodiments, the embedded portion of the subsequently formed conductive bump structure can be formed according to the shape of the groove and have a columnar, inverted hammer or anchor shape. The inverted hammer or anchor-shaped conductive bump structure can be formed according to the groove having a side portion. In some embodiments, the embedded portion of the conductive bump structure includes a first sub-portion embedded in the passivation layer and a second sub-portion embedded in the conductive pad. The first sub-portion has a first size in the first direction. The second sub-portion has a second size greater than or equal to the first size.

[0109] In some embodiments, the conductive bump structure such as a microbump, a copper pillar bump or a controlled collapse chip connection (C4) bump includes an under bump metallurgy (UBM) layer on a conductive pad, a conductive pillar on the bump metal layer, and a solder cap on the conductive pillar. The embedded portion includes the bump metal layer and the conductive pillar. In some embodiments, the first sub-portion is composed of the bump metal layer and the conductive pillar, and the second sub-portion is composed of the bump metal layer.

[0110] In some embodiments, the conductive bump structure, such as the ENEPIG bump structure, includes a base layer on the conductive pad, a buffer layer on the base layer, and a final outer layer on the buffer layer. In some embodiments, the base layer protrudes from the top surface of the passivation layer.

[0111] In some embodiments, the semiconductor structure further comprises a photosensitive stress buffer layer conformally formed on the passivation layer. The conductive bump structure is surrounded by the photosensitive stress buffer layer. In some embodiments, the photosensitive stress buffer layer is located above the embedded portion of the conductive bump structure. In some embodiments, the photosensitive stress buffer layer extends into the passivation layer and surrounds the embedded portion of the conductive bump structure.

[0112] Since the exposed conductive pads need to undergo a surface treatment process in the copper RDL solution, a unique groove of the conductive pads is formed accordingly. The subsequent conductive bump structure can be further embedded in the conductive pads to enhance the shear strength of the conductive bump structure, thereby improving the reliability of the conductive bump structure.

[0113] Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor structure comprising: An interconnect structure includes a conductive pad located on top of the interconnect structure; A passivation layer is disposed on the interconnect structure; as well as A conductive bump structure is disposed in and embedded in the passivation layer and the conductive pad, wherein in a first direction, a first interface between the passivation layer and the conductive pad is located and not aligned with a second interface between the conductive bump structure and the conductive pad. 2 . The semiconductor structure of claim 1 , wherein in the second direction, a ratio of a first thickness of the conducting pad to a first distance between the first interface and the second interface is between 1 and 75. 3 . 3 . The semiconductor structure as claimed in claim 1 , wherein a portion of the conductive bump structure embedded in the passivation layer and the conductive pad has a pillar shape, an inverted hammer shape or an anchor shape.

4. The semiconductor structure as claimed in claim 3, wherein the conductive bump structure of the embedded portion comprises: a first sub-portion embedded in the passivation layer, wherein the first sub-portion has a first dimension in the first direction; as well as A second sub-portion is embedded in the conductive pad, wherein the second sub-portion has a second dimension greater than or equal to the first dimension.

5. The semiconductor structure as claimed in claim 1, wherein the conducting pad comprises: A groove is recessed from the first top surface of the conductive pad, wherein the groove has a first bottom surface, a first side surface and a second side surface, the first bottom surface is surrounded by the first top surface, and the first and second side surfaces connect the first top surface of the conductive pad and the first bottom surface of the groove. 6 . The semiconductor structure as claimed in claim 5 , wherein the first interface is located on a first top surface of the conducting pad, and the second interface is located on a first bottom surface of the conducting pad in the groove. 7 . The semiconductor structure as claimed in claim 5 , wherein the conductive bump structure contacts the first bottom surface, the first side surface and the second side surface. The semiconductor structure as claimed in claim 5 , wherein the first bottom surface of the groove comprises a flat surface or a concave surface. 9 . The semiconductor structure as claimed in claim 1 , wherein a first angle between the first side surface and the first bottom surface comprises a sharp angle or a rounded angle.

10. The semiconductor structure of claim 3, wherein the passivation layer comprises: a first protrusion protruding from the first top surface and located above the first side surface and the first bottom surface; A second protrusion protrudes from the first top surface and is located above the second side surface and the first bottom surface of the groove. The semiconductor structure of claim 10 , wherein the embedded portion is adjacent to the first protruding portion and the second protruding portion. 12 . The semiconductor structure of claim 10 , wherein in the first direction, a third dimension of the first protruding portion and a fourth dimension of the second protruding portion are between 0.01 μm and 3 μm. 13 . The semiconductor structure of claim 12 , wherein a ratio of the third size to the fourth size is between 0.03 and 3. 14 . The semiconductor structure of claim 10 , wherein the first extending portion, the first side surface, and a first bottom surface portion overlapping the first extending portion form a side portion of the groove. The semiconductor structure as claimed in claim 14 , wherein the conductive bump structure fills a side portion of the groove. 16 . The semiconductor structure as claimed in claim 14 , wherein a side portion of the groove has a circular, polygonal, fan-shaped, stripe-shaped or irregular shape.

17. The semiconductor structure according to claim 4, wherein the conductive bump structure comprises: a bump metal layer located on the conductive pad; A conductive column located on the bump metal layer; as well as A solder cap is located on the conductive column, wherein the embedded portion includes the bump metal layer and the conductive column. 18 . The semiconductor structure of claim 17 , wherein the first sub-portion consists of the bump metal layer and the conductive pillar, and the second sub-portion consists of the bump metal layer.

19. The semiconductor structure according to claim 3, wherein the conductive bump structure comprises: a base layer located on the conductive pad; a buffer layer located on the base layer; as well as A final outer layer is located on the buffer layer, wherein the base layer, the buffer layer and the final outer layer are made of different metal materials, and the embedded part is composed of the base layer. 20 . The semiconductor structure of claim 19 , wherein the base layer protrudes from a top surface of the passivation layer.

21. The semiconductor structure of claim 3, further comprising: A photosensitive stress buffer layer is conformally formed on a passivation layer, wherein a conductive bump structure is surrounded by the photosensitive stress buffer layer.

22. The semiconductor structure of claim 21, wherein the photosensitive stress buffer layer is located on the embedded portion of the conductive bump structure.

23. The semiconductor structure of claim 21, wherein the photosensitive stress buffer layer extends into the passivation layer and surrounds the embedded portion of the conductive bump structure.

24. A method of forming a semiconductor structure, comprising: forming an interconnect structure including a conductive pad located on top of the interconnect structure; forming a passivation layer on the interconnect structure; forming a first opening through the passivation layer to expose a top surface of the conductive pad; performing a surface treatment process to form a groove of the conductive pad recessed from an exposed top surface of the conductive pad; A conductive bump structure is formed on the passivation layer to fill the first opening and the groove of the conductive pad, wherein in a first direction, a first interface between the passivation layer and the conductive pad is located beside and offset from a second interface between the conductive bump structure and the conductive pad. 25 . The method for forming a semiconductor structure as claimed in claim 24 , wherein opposite side surfaces of the groove have a vertical profile, an overcut profile or an undercut profile.

26. The method for forming a semiconductor structure according to claim 24, wherein forming a conductive bump structure comprises: forming a bump metallization layer lining the first opening and filling the conductive pad groove; forming a conductive column on the bump metallization layer and filling the first opening; A solder cap is formed on the conductive post.

27. The method for forming a semiconductor structure according to claim 24, wherein forming a conductive bump structure comprises: depositing a base layer filling the first opening and the conductive pad groove, wherein the base layer protrudes from a top surface of the passivation layer; depositing a buffer layer on the base layer; The final outer layer is deposited over the buffer layer.

28. The method of forming a semiconductor structure according to claim 24, further comprising: Before forming the conductive bump structure, a photosensitive stress buffer layer is conformally formed on the passivation layer; A second opening is formed through the photosensitive stress buffer layer to expose a portion of the conductive pad.

29. The method of forming a semiconductor structure according to claim 28, further comprising: A photolithography process is performed to remove the photosensitive stress buffer layer directly on the conductive pad portion to form a second opening in the first opening.

30. The method of forming a semiconductor structure according to claim 28, further comprising: A photolithography process is performed to remove the first opening in the passivation layer and the photosensitive stress buffer layer directly on the conductive pad portion to form a second opening in the first opening.

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