Semiconductor interconnection structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor interconnection structure, a manufacturing method thereof and electronic equipment. The semiconductor interconnection structure is located above a device functional area of a substrate and comprises a plurality of interconnection layers which are arranged in a stacked mode in the direction away from the substrate and isolation anti-collapse structures located between every two adjacent interconnection layers. The interconnection layer comprises an insulating medium layer and at least two conductive structures which penetrate through the insulating medium layer and are arranged at intervals in the direction parallel to the substrate. The isolation anti-collapse structure comprises one or more supporting structures which penetrate through the insulating dielectric layer and are located in a gap between every two adjacent conductive structures, and an isolation dielectric layer which covers the interconnection layer and is connected with the supporting structures. The electrical performance and the structural stability of the semiconductor interconnection structure and the electronic equipment can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor interconnect structure and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of semiconductor technology, electronic devices are moving towards miniaturization, light weight, high performance and multi-function. The process nodes of semiconductor manufacturing are constantly breaking through, and chip integration and chip performance are also increasing rapidly. However, with the increase in the number of metal connection layers in the semiconductor interconnect structure, the distance between adjacent wires is also shrinking. Therefore, when electronic signals are transmitted between metal connections with a large number of layers, resistance-capacitance delay (RC Delay) is easily generated, which seriously reduces the response speed of the semiconductor interconnect structure. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide a semiconductor interconnect structure and a manufacturing method thereof, and an electronic device, which can effectively improve the electrical performance and structural stability of the semiconductor interconnect structure and the electronic device.

[0004] In order to achieve the above-mentioned objectives, in a first aspect, some embodiments of the present disclosure provide a semiconductor interconnect structure, which is located above the device functional area of ​​the substrate, and includes: a plurality of interconnect layers stacked in a direction away from the substrate, and an isolation and collapse prevention structure located between each two adjacent interconnect layers. The interconnect layer includes an insulating dielectric layer and at least two conductive structures that penetrate the insulating dielectric layer and are spaced apart in a direction parallel to the substrate. The isolation and collapse prevention structure includes: one or more supporting structures that penetrate the insulating dielectric layer and are located in the interval between each two adjacent conductive structures, and an isolation dielectric layer that covers the interconnect layer and connects the supporting structures.

[0005] In some embodiments of the present disclosure, the dielectric constant of the isolation dielectric layer is smaller than the dielectric constant of the insulating dielectric layer. The dielectric constant of the support structure is smaller than or equal to the dielectric constant of the isolation dielectric layer.

[0006] In some embodiments of the present disclosure, an air gap unit is enclosed inside the support structure.

[0007] In some other embodiments of the present disclosure, an isolation structure is enclosed inside the support structure, and the dielectric constant of the isolation structure is smaller than the dielectric constant of the isolation dielectric layer.

[0008] In some embodiments of the present disclosure, the support structure comprises an arched support structure, which comprises: a bottom wall support layer, a bridge wall support layer disposed on the bottom wall support layer and arranged in an arched shape, and an air gap unit disposed in an arched space formed by the bottom wall support layer and the bridge wall support layer.

[0009] In some embodiments of the present disclosure, the isolation medium layer is a first isolation layer; the bottom wall support layer, the bridge wall support layer and the first isolation layer are integrally formed.

[0010] In some other embodiments of the present disclosure, the isolation medium layer includes a first isolation layer and a second isolation layer stacked. The bridge wall support layer includes: a side bridge wall support layer located on the bottom wall support layer, and a top bridge wall support layer closed and connected to the side bridge wall support layer. The bottom wall support layer, the side bridge wall support layer and the first isolation layer are integrally formed. The top bridge wall support layer and the second isolation layer are integrally formed.

[0011] In a second aspect, some embodiments of the present disclosure provide a method for manufacturing a semiconductor interconnect structure, which is used to manufacture the semiconductor interconnect structure in some of the above embodiments. The method for manufacturing the semiconductor interconnect structure comprises: providing a substrate, the substrate having a device functional area; alternatingly forming multiple interconnect layers and multiple isolation and collapse prevention structures above the device functional area of ​​the substrate. The interconnect layer comprises an insulating dielectric layer and at least two conductive structures that penetrate the insulating dielectric layer and are spaced apart in a direction parallel to the substrate; the isolation and collapse prevention structure comprises: one or more supporting structures that penetrate the insulating dielectric layer and are located in the interval between each two adjacent conductive structures, and an isolation dielectric layer that covers the interconnect layer and connects the supporting structures.

[0012] In some embodiments of the present disclosure, forming an interconnection layer and an isolation and anti-collapse structure may include the following steps.

[0013] A sacrificial protrusion is formed to form a pseudo-support structure.

[0014] An insulating dielectric layer covering the sacrificial protrusion and a conductive structure penetrating the insulating dielectric layer and located beside the sacrificial protrusion in a direction parallel to the substrate are formed.

[0015] The insulating dielectric layer is etched to form an opening, wherein the opening exposes the top of the sacrificial protrusion.

[0016] The sacrificial protrusion is removed based on the opening to form a supporting structure accommodating groove.

[0017] A bottom wall support layer conformally covering the inner wall of the support structure accommodating groove and a side bridge wall support layer connected to the bottom wall support layer are formed, as well as a first isolation layer covering the top surfaces of the insulating medium layer and the conductive structure and connecting the side bridge wall support layer.

[0018] A top bridge wall supporting layer filling the opening to close the connecting side bridge wall supporting layers and a second insulating layer covering the first insulating layer are formed.

[0019] Accordingly, in the embodiment of the present disclosure, the isolation medium layer includes a first isolation layer and a second isolation layer. The support structure includes a bottom wall support layer, a side bridge wall support layer, a top bridge wall support layer, and an air gap unit formed by the bottom wall support layer, the side bridge wall support layer, and the top bridge wall support layer enclosing the support structure accommodating groove.

[0020] In some other embodiments of the present disclosure, forming an interconnection layer and an isolation and anti-collapse structure may include the following steps.

[0021] A sacrificial protrusion is formed to form a pseudo-support structure.

[0022] An initial insulating dielectric layer covering the sacrificial protrusion and an initial conductive structure penetrating the initial insulating dielectric layer and located beside the sacrificial protrusion in a direction parallel to the substrate are formed.

[0023] The initial insulating dielectric layer and the initial conductive structure are ground until the top of the sacrificial protrusion is exposed to form an insulating dielectric layer and a conductive structure.

[0024] The sacrificial protrusion is removed to form a supporting structure accommodating groove.

[0025] A bottom wall support layer conformally covering the inner wall of the support structure accommodating groove and a bridge wall support layer sealing and connecting the bottom wall support layer are formed, as well as a first isolation layer covering the top surfaces of the insulating medium layer and the conductive structure and connecting the bridge wall support layer.

[0026] Correspondingly, in the embodiment of the present disclosure, the isolation medium layer is the first isolation layer. The support structure includes a bottom wall support layer, a bridge wall support layer, and an air gap unit formed by the bottom wall support layer and the bridge wall support layer enclosing the support structure accommodating groove.

[0027] In some embodiments of the present disclosure, the method for manufacturing a semiconductor interconnect structure further includes: before closing the support structure receiving groove to form the air gap unit, filling the support structure receiving groove with an isolation material, and forming an isolation structure replacing the air gap unit with the isolation material.

[0028] In a third aspect, some embodiments of the present disclosure provide an electronic device, comprising: a semiconductor interconnect structure as described in any of the above embodiments; or a semiconductor interconnect structure prepared using a manufacturing method as described in any of the above embodiments.

[0029] The embodiments of the present disclosure may or at least have the following advantages:

[0030] The semiconductor interconnect structure provided by the embodiment of the present disclosure has an isolation and anti-collapse structure between every two adjacent interconnect layers, and a support structure and an isolation dielectric layer are provided in the isolation and anti-collapse structure. This not only facilitates the three-dimensional stacking of the interconnect layers through the support of the support structure to the interconnect layers and prevents the collapse of the semiconductor interconnect structure, but also reduces the parasitic capacitance in the semiconductor interconnect structure by reducing the dielectric constant of the isolation and anti-collapse structure, effectively improving the RC delay of the semiconductor interconnect structure, thereby improving the electrical performance and structural stability of the semiconductor interconnect structure and electronic equipment.

[0031] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a schematic structural diagram of a semiconductor interconnect structure provided in some embodiments;

[0034] Figure 2 A schematic structural diagram of another semiconductor interconnect structure provided in some embodiments;

[0035] Figure 3 for Figure 2 A schematic diagram of a stress analysis of an isolation and collapse prevention structure in a semiconductor interconnect structure is shown;

[0036] Figure 4 is a schematic structural diagram of another semiconductor interconnect structure provided in some embodiments;

[0037] Figure 5 is a schematic structural diagram of another semiconductor interconnect structure provided in some embodiments;

[0038] Figure 6 is a schematic structural diagram of another semiconductor interconnect structure provided in some embodiments;

[0039] Figure 7 is a flow chart of a method for manufacturing a semiconductor interconnect structure provided in some embodiments;

[0040] Figure 8 is a schematic structural diagram of a substrate provided in some embodiments;

[0041] Fig. 9 A schematic diagram of a structure obtained after forming a sacrificial protrusion provided in some embodiments;

[0042] Fig.10 A schematic structural diagram of a structure obtained after forming a first interconnection layer provided in some embodiments;

[0043] Fig.11 A schematic diagram of a structure obtained after an opening is formed to expose a top of a sacrificial protrusion provided in some embodiments;

[0044] Fig.12 A schematic diagram of a structure obtained after a support structure accommodating groove is formed in some embodiments;

[0045] Fig.13 A schematic diagram of a structure obtained after depositing a first isolation material provided in some embodiments;

[0046] Fig.14 A schematic diagram of a structure obtained after depositing a second isolation material provided in some embodiments;

[0047] Fig.15 A schematic structural diagram of a structure obtained after forming a second interconnection layer and a corresponding isolation and collapse prevention structure provided in some embodiments;

[0048] Fig.16 A flowchart of a method for manufacturing a semiconductor interconnect structure provided in some other embodiments;

[0049] Fig.17 A schematic diagram of a structure obtained after forming an initial insulating dielectric layer and an initial conductive structure provided in some other embodiments;

[0050] Fig.18 A schematic diagram of a structure obtained after forming an insulating dielectric layer and a conductive structure provided in some other embodiments;

[0051] Fig.19 A schematic diagram of a structure obtained after forming a supporting structure accommodating groove provided in some other embodiments;

[0052] Fig. 20 A schematic diagram of a structure obtained after depositing a first isolation material provided in some other embodiments;

[0053] Fig.21 A schematic diagram of a structure obtained after forming a second interconnection layer and a corresponding isolation and collapse prevention structure provided in some other embodiments;

[0054] Fig. 22A schematic structural diagram of a structure obtained after forming a plurality of air gap units in an isolation and collapse prevention structure provided in still other embodiments;

[0055] Fig.23 It is a structural schematic diagram of a structure obtained after forming multiple isolation structures in an isolation and collapse prevention structure provided in some other embodiments.

[0056] Description of reference numerals:

[0057] 1-substrate, 2-buffer layer, 3-sacrificial protrusion, 4-first interconnection layer, 41-first insulating dielectric layer, 42-first conductive structure, 4A-initial first interconnection layer, 41A-initial first insulating dielectric layer, 42A-initial first conductive structure, 5-isolation and anti-collapse structure, 51-support structure, 511-bottom wall support layer, 512-bridge wall support layer, 512a-side bridge arm support layer, 512b top bridge wall support layer, 513-air gap unit, 514-isolation structure, 52-isolation dielectric layer, 521 and 521'-first isolation layer, 522-second isolation layer, 6-second interconnection layer, 61-second insulating dielectric layer, 62-second conductive structure, K1-opening, S1 and S2-support structure accommodating grooves. DETAILED DESCRIPTION

[0058] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0060] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0061] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0062] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] At present, as the number of metal wiring layers in semiconductor interconnect structures increases, the distance between adjacent wires is also shrinking. Therefore, when electronic signals are transmitted between metal wiring layers with a large number of layers, resistance-capacitance delay (RC Delay) is easily generated, which seriously reduces the response speed of the semiconductor interconnect structure.

[0064] Based on this, the embodiments of the present disclosure provide a semiconductor interconnect structure and a manufacturing method thereof, and an electronic device, which can effectively improve the electrical performance of the semiconductor interconnect structure and the electronic device.

[0065] See also Figure 1 The semiconductor interconnect structure provided by some embodiments of the present disclosure is located above the device functional area of ​​the substrate 1, and includes: a plurality of interconnect layers (for example, a first interconnect layer 4) stacked in a direction away from the substrate 1, and an isolation and collapse prevention structure 5 located between each two adjacent interconnect layers. Figure 1 Only one interconnection layer is used as an example for illustration, but it can be understood that the interconnection layer and the isolation and anti-collapse structure 5 can be three-dimensionally stacked in a direction perpendicular to the substrate 1, and the embodiment of the present disclosure does not limit the number of stacked layers.

[0066] For example, the substrate 1 may be a semiconductor substrate. The semiconductor substrate includes but is not limited to a silicon substrate. For example, the semiconductor substrate may also include a silicon germanium (SiGe) substrate, a silicon on insulator (SOI) substrate, a III / V semiconductor substrate, or a II / VI semiconductor substrate.

[0067] For example, Figure 1As shown in , a buffer layer 2 covering the device functional area can be provided on the substrate 1 to isolate and protect the device functional area. The buffer layer 2 is formed of insulating materials such as silicon oxide. The device functional area can be selected and set to match the needs, and the embodiments of the present disclosure are not limited to this.

[0068] In some embodiments, please refer to Figure 1 The interconnection layer (eg, the first interconnection layer 4 ) includes an insulating dielectric layer (eg, the first insulating dielectric layer 41 ) and at least two conductive structures (eg, the first conductive structure 42 ) penetrating the insulating dielectric layer and spaced apart in a direction parallel to the substrate 1 .

[0069] By way of example, the conductive structure is a metal wire, and for example, a metal stack such as Al—Cu—Co may be used as the metal wire.

[0070] In some embodiments, please refer to Figure 1 The isolation and collapse prevention structure 5 includes: one or more support structures 51 penetrating the insulating dielectric layer and located in the interval between each two adjacent conductive structures, and an isolation dielectric layer 52 covering the interconnection layer and connecting the support structures 51 .

[0071] For example, the dielectric constant of the isolation dielectric layer 52 is less than the dielectric constant of the insulating dielectric layer in the corresponding interconnect layer, and the dielectric constant of the support structure 51 is less than or equal to the dielectric constant of the isolation dielectric layer 52. Here, the dielectric constant of the support structure 51 refers to its overall dielectric constant, for example, the overall dielectric constant including the support layer and the corresponding closed structure (such as the air gap unit or the isolation structure) in the support layer.

[0072] For example, the dielectric constant of the isolation dielectric layer 52 can be reduced by reducing the polarity of the material or adding a pore-forming agent to make the material loose and porous.

[0073] Illustratively, the height of the support structure 51 is less than or equal to the thickness of the insulating dielectric layer in the corresponding interconnect layer.

[0074] In the disclosed embodiment, an isolation and collapse prevention structure 5 is provided between every two adjacent interconnection layers, a support structure 51 and an isolation dielectric layer 52 are provided in the isolation and collapse prevention structure 5, and the dielectric constant of the isolation dielectric layer 52 is made smaller than the dielectric constant of the insulating dielectric layer, and the dielectric constant of the support structure 51 is smaller than or equal to the dielectric constant of the isolation dielectric layer 52. This not only facilitates the three-dimensional stacking of the interconnection layers through the support effect of the support structure 51 on the interconnection layers and prevents the semiconductor interconnection structure from collapsing, but also reduces the parasitic capacitance in the semiconductor interconnection structure through the isolation and collapse prevention structure 5 having a dielectric constant smaller than that of the insulating dielectric layer, effectively improving the RC delay of the semiconductor interconnection structure, thereby improving the electrical performance and structural stability of the semiconductor interconnection structure and electronic equipment.

[0075] In some embodiments, please refer to Figure 1 An air gap unit 513 is enclosed inside the supporting structure 51 .

[0076] Accordingly, the support structure 51 is located in the interval between two corresponding adjacent conductive structures (eg, the first conductive structure 42 ), which can be manifested as: the orthographic projections of the air gap unit 513 and the conductive structure (eg, the first conductive structure 42 ) on the substrate 1 do not overlap.

[0077] For example, when the distance between two adjacent conductive structures is relatively large, for example, greater than a target threshold (which can be set selectively according to specific matching requirements), the number of air gap units 513 can be set to be multiple to match the distance between the two adjacent conductive structures.

[0078] It is worth mentioning that, in some embodiments of the present disclosure, the cross-sectional size of the air gap unit 513 gradually decreases along a direction away from the substrate 1 .

[0079] Here, the cross-sectional dimensions of the air gap unit 513 gradually decrease, which can be expressed as: the cross-sectional dimensions of the air gap unit 513 in a single direction gradually decrease or the cross-sectional area gradually decreases; and the gradually decreasing manner can also be a constant gradient decrease or a gradual decrease in an arithmetic progression. The embodiments of the present disclosure do not specifically limit this.

[0080] By way of example, the air gap unit 513 includes but is not limited to being a hemispherical air gap.

[0081] In some embodiments of the present disclosure, please refer to Figure 2 The support structure 51 includes an arched support structure, which includes a bottom wall support layer 511, a bridge wall support layer 512 disposed on the bottom wall support layer 511 and arranged in an arched shape, and an air gap unit 513 located in the arched space formed by the bottom wall support layer 511 and the bridge wall support layer 512.

[0082] For some possible implementations, please continue to refer to Figure 2 , the isolation medium layer 52 is only the first isolation layer 521. The bottom wall support layer 511 and the bridge wall support layer 512 of the support structure 51 can be integrally formed with the first isolation layer 521. In this way, it is helpful to simplify the preparation process of the isolation and anti-collapse structure 5 and to improve the structural stability of the isolation and anti-collapse structure 5.

[0083] In the embodiment of the present disclosure, the support structure 51 adopts an arch support structure, and its force analysis can refer to Figure 3 Understand. Figure 3As shown in the figure, when there is pressure above the isolation and anti-collapse structure 5, the pressure can be transmitted downward in an arch shape along the bridge wall support layer 512 of the arch support structure until it is transmitted to the bottom wall support layer 511 of the arch support structure. At this time, the bottom wall support layer 511 can generate an inward pulling force along a direction parallel to the substrate to pull the semiconductor interconnect structure inward, thereby preventing the semiconductor interconnect structure from collapsing after three-dimensional stacking of multiple interconnect layers, effectively improving the structural stability of the semiconductor interconnect structure, and further facilitating improving the reliability of the semiconductor interconnect structure.

[0084] For other possible implementations, see Figure 4 , the isolation medium layer 52 includes a first isolation layer 521 and a second isolation layer 522 which are stacked. The bridge wall support layer 512 of the support structure 51 includes: a side bridge wall support layer 512a located on the bottom wall support layer 511, and a top bridge wall support layer 512b which is closed and connected to the side bridge wall support layer 512a. Among them, the bottom wall support layer 511 and the side bridge wall support layer 512a of the support structure 51 are integrally formed with the first isolation layer 521. The top bridge wall support layer 512b of the support structure 51 is integrally formed with the second isolation layer 522. In this way, it is helpful to reduce the difficulty of preparing the isolation and anti-collapse structure 5, so as to facilitate implementation and improve production efficiency and production reliability, and it is also helpful to improve the structural stability of the isolation and anti-collapse structure 5.

[0085] For example, the first isolation layer 521 and the second isolation layer 522 are made of the same material and can be prepared based on the same deposition process.

[0086] It is worth mentioning that in some embodiments, see Figure 5 and Figure 6 An isolation structure 514 is enclosed inside the support structure 51 , and a dielectric constant of the isolation structure 514 is smaller than a dielectric constant of the isolation dielectric layer 52 .

[0087] For example, the isolation structure 514 can be prepared by filling the aforementioned air gap unit 513 with chemically stable and high-temperature resistant long-chain organic matter, such as acrylic, resin materials, etc., to ensure that the isolation structure 514 can enhance the structural strength of the isolation anti-collapse structure 5 after curing, thereby enhancing the structural strength of the semiconductor interconnect structure.

[0088] In the embodiment of the present disclosure, an isolation structure 514 is filled in the air gap unit 513, and the dielectric constant of the isolation structure 514 is made less than or equal to the dielectric constant of the isolation dielectric layer. This not only strengthens the structural strength of the semiconductor interconnect structure through the isolation structure 514, but also further reduces the parasitic capacitance between adjacent conductive structures through the isolation structure 514.

[0089] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor interconnect structure, which is used to manufacture the semiconductor interconnect structure in some of the above embodiments. The method for manufacturing a semiconductor interconnect structure includes: providing a substrate, the substrate having a device functional area; alternately forming multiple interconnect layers and multiple isolation and collapse prevention structures above the device functional area of ​​the substrate. The interconnect layer includes an insulating dielectric layer and at least two conductive structures that penetrate the insulating dielectric layer and are spaced apart in a direction parallel to the substrate. The isolation and collapse prevention structure includes: one or more supporting structures that penetrate the insulating dielectric layer and are located in the interval between each two adjacent conductive structures, and an isolation dielectric layer that covers the interconnect layer and connects the supporting structures.

[0090] For example, the dielectric constant of the isolation dielectric layer is less than that of the insulating dielectric layer; the dielectric constant of the support structure is less than or equal to that of the isolation dielectric layer. The semiconductor interconnect structure also has the technical advantages of the aforementioned semiconductor interconnect structure, which will not be elaborated here.

[0091] In order to more clearly illustrate the embodiments of the present disclosure, the following embodiments illustratively provide some possible implementations.

[0092] For some possible implementations, see Figure 7 , forming an interconnection layer and an isolation and anti-collapse structure, may include the following steps S11 to S16.

[0093] Step S11, forming a sacrificial protrusion of a pseudo-shaped support structure.

[0094] For example, see Figure 8 , providing a substrate 1, on which a buffer layer 2 covering a device functional area is formed.

[0095] See also Fig. 9 , one or more sacrificial protrusions 3 are formed on the buffer layer 2.

[0096] Optionally, the cross-sectional size of the sacrificial protrusion 3 gradually decreases in a direction away from the substrate 1 .

[0097] In some examples, the sacrificial protrusion 3 includes, but is not limited to, a hemispherical protrusion or a dome-shaped protrusion.

[0098] In some examples, the sacrificial protrusion 3 can be formed by inkjet printing or exposure and development. The material of the sacrificial protrusion 3 is not limited in the embodiment of the present disclosure, and the material of the sacrificial protrusion 3 includes but is not limited to organic materials.

[0099] Step S12, forming an insulating dielectric layer covering the sacrificial protrusion, and a conductive structure penetrating the insulating dielectric layer and located beside the sacrificial protrusion in a direction parallel to the substrate.

[0100] For example, the orthographic projections of the conductive structure and the sacrificial protrusion on the substrate do not overlap.

[0101] For example, see Fig.10 , forming a first insulating dielectric layer 41 covering the sacrificial protrusion 3, and a first conductive structure 42 penetrating the first insulating dielectric layer 41 and located beside the sacrificial protrusion 3 in a direction parallel to the substrate. The first conductive structure 42 also penetrates the buffer layer 2 and connects the device functional area of ​​the substrate 1.

[0102] Step S13, etching the insulating dielectric layer to form an opening, wherein the opening exposes the top of the sacrificial protrusion.

[0103] For example, see Fig.11 The first insulating dielectric layer 41 is etched by dry etching process to form an opening K1 , wherein the opening K1 exposes the top of the sacrificial protrusion 3 .

[0104] Step S14, removing the sacrificial protrusion based on the opening to form a supporting structure accommodating groove.

[0105] For example, see Fig.12 The sacrificial protrusion 3 can be removed by ash or development to form the support structure accommodating groove S1.

[0106] Step S15, forming a bottom wall support layer conformally covering the inner wall of the support structure accommodating groove and a side bridge wall support layer connecting the bottom wall support layer, and a first isolation layer covering the top surfaces of the insulating medium layer and the conductive structure and connecting the side bridge wall support layer.

[0107] For example, see Fig.13 A first isolation material is conformally deposited on the top surfaces of the first insulating dielectric layer 41 and the first conductive structure 42 and the inner wall of the initial air gap S1 using a deposition process to form a bottom wall support layer 511 that conformally covers the inner wall of the support structure accommodating groove S1 and a side bridge wall support layer 512a connected to the bottom wall support layer 511, as well as a first isolation layer 521 that covers the top surfaces of the first insulating dielectric layer 41 and the first conductive structure 42 and connects the side bridge wall support layer 512a.

[0108] In some examples, the first isolation layer 521 may be formed by using an atomic layer deposition (ALD) process with a high step coverage.

[0109] In some examples, the dielectric constant of the first isolation layer 521 may be lower than the dielectric constant of the first insulating medium layer 41. The dielectric constant of the first isolation layer 521 may be reduced by reducing the polarity of the material or adding a pore-forming agent to make the material loose and porous.

[0110] Step S16, forming a top bridge wall supporting layer filling the opening to close the connecting side bridge wall supporting layer, and a second insulating layer covering the first insulating layer.

[0111] For example, see Fig.14 A second isolation material is continuously deposited on the first isolation layer 521 and the side bridge wall support layer 512 a using a deposition process to form a filling opening K1 to close the top bridge wall support layer 512 b connected to the side bridge wall support layer 512 a , and a second isolation layer 522 covering the first isolation layer 521 .

[0112] It can be understood that the size of the opening K1 is relatively small, and during the deposition of the second isolation material, the second isolation material will naturally fill and seal the opening K1 in advance.

[0113] In some examples, the second isolation layer 522 and the first isolation layer 521 are made of the same material; that is, they can be made of the same material and the same manufacturing process.

[0114] Therefore, in the embodiments of the present disclosure, Fig.14 As shown, the isolation medium layer 52 of the isolation and collapse prevention structure 5 includes the first isolation layer 521 and the second isolation layer 522. The support structure 51 of the isolation and collapse prevention structure 5 includes the bottom wall support layer 511, the side bridge wall support layer 512a, the top bridge wall support layer 512b, and an air gap unit 513 formed by the bottom wall support layer 511, the side bridge wall support layer 512a, and the top bridge wall support layer 512b enclosing the support structure accommodating groove S1.

[0115] In some embodiments of the present disclosure, please refer to Fig.15 The same method can be used to continue to form a second interconnection layer 6 and a corresponding isolation and collapse prevention structure 5 on the isolation and collapse prevention structure 5, as well as more interconnection layers and corresponding isolation and collapse prevention structures. This embodiment of the disclosure will not be described in detail.

[0116] For example, Fig.15 As shown in the figure, taking the two interconnection layers on the substrate 1 as an example, the first conductive structure 42 in the first interconnection layer 4 penetrates the first insulating dielectric layer 41 and is connected to the device functional area of ​​the substrate; the second conductive structure 62 in the second interconnection layer 6 penetrates the second insulating dielectric layer 61 and the isolation and collapse prevention structure 5 located between the first interconnection layer 4 and the second interconnection layer 6, and is connected to the corresponding first conductive structure 42.

[0117] In some other embodiments of the present disclosure, please refer to Fig.16 , forming an interconnection layer and an isolation and anti-collapse structure may include the following steps S21 to S25.

[0118] Step S21, forming a sacrificial protrusion of a pseudo-shaped support structure.

[0119] Step S22, forming an initial insulating dielectric layer covering the sacrificial protrusion, and an initial conductive structure penetrating the initial insulating dielectric layer and located beside the sacrificial protrusion in a direction parallel to the substrate.

[0120] Illustratively, the orthographic projections of the initial conductive structure and the sacrificial protrusion on the substrate do not overlap.

[0121] For example, see Fig.17 , forming an initial first insulating dielectric layer 41A covering the sacrificial protrusion 3, and an initial first conductive structure 42A penetrating the initial first insulating dielectric layer 41A and located beside the sacrificial protrusion 3 in a direction parallel to the substrate. The initial first conductive structure 42A also penetrates the buffer layer 2 and connects the device functional area of ​​the substrate 1.

[0122] Step S23 , grinding the initial insulating dielectric layer and the initial conductive structure until the top of the sacrificial protrusion is exposed, thereby forming an insulating dielectric layer and a conductive structure corresponding to the interconnect layer.

[0123] For example, see Fig.18 and Fig.19 , the top surfaces of the initial first insulating dielectric layer 41A and the initial first conductive structure 42A are polished by chemical mechanical polishing until the top of the sacrificial protrusion 3 is exposed, and the first insulating dielectric layer 41 and the first conductive structure 42 are simultaneously obtained. Here, the exposed area of ​​the sacrificial protrusion 3 can be set to match the requirements, so as to perform the step of removing the sacrificial protrusion 3 later.

[0124] Step S24, removing the sacrificial protrusions to form a supporting structure accommodating groove.

[0125] For example, see Fig.19 The sacrificial protrusion 3 can be removed by ash or development to form the support structure accommodating groove S2.

[0126] Step S25, forming a bottom wall support layer conformally covering the inner wall of the support structure accommodating groove, a bridge wall support layer sealing and connecting the bottom wall support layer, and a first isolation layer covering the top surfaces of the insulating medium layer and the conductive structure and connecting the bridge wall support layer.

[0127] For example, see Fig. 20 A first isolation material is conformally deposited on the top surfaces of the first insulating dielectric layer 41 and the first conductive structure 42 and the inner wall of the support structure accommodating groove S2 using a deposition process to form a bottom wall support layer 511 that conformally covers the inner wall of the support structure accommodating groove S2 and a bridge wall support layer 512 that closes and connects the bottom wall support layer 511, as well as a first isolation layer 521' that covers the top surfaces of the first insulating dielectric layer 41 and the first conductive structure 42 and connects the bridge wall support layer 512.

[0128] In some examples, the first isolation material may be prepared by an atomic layer deposition (ALD) process with a high step coverage rate. In addition, the first isolation material may close the support structure receiving groove S2 by itself during its deposition process to obtain the air gap unit 513 .

[0129] In some examples, the dielectric constant of the first isolation material may be lower than the dielectric constant of the first insulating medium layer 41. The dielectric constant of the first isolation material may be reduced by reducing the polarity of the material or adding a pore-forming agent to make the material loose and porous.

[0130] Therefore, in the embodiments of the present disclosure, Fig. 20 As shown, the isolation medium layer 52 in the isolation and collapse prevention structure 5 is a first isolation layer 521'. The support structure 51 in the isolation and collapse prevention structure 5 includes the bottom wall support layer 511, the bridge wall support layer 512, and an air gap unit 513 formed by the bottom wall support layer 511 and the bridge wall support layer 512 enclosing the support structure accommodating groove S2.

[0131] In some embodiments of the present disclosure, please refer to Fig.21 The same method can be used to continue to form a second interconnection layer 6 and a corresponding isolation and collapse prevention structure 5 on the isolation and collapse prevention structure 5, as well as more interconnection layers and corresponding isolation and collapse prevention structures. This embodiment of the disclosure will not be described in detail.

[0132] It is worth mentioning that in some embodiments of the present disclosure, please combine Fig. 22 It is understood that if the distance between two adjacent conductive structures in the interconnect layer is large, for example, greater than a target threshold (which can be set according to specific matching requirements), multiple support structures 51 can be synchronously formed to match the distance between the two adjacent conductive structures, thereby further enhancing the structural strength and structural stability of the semiconductor interconnect structure.

[0133] Optionally, two adjacent support structures 51 along a direction parallel to the substrate 1 may be arranged with or without a gap.

[0134] In some embodiments of the present disclosure, please combine Fig.23 It is understood that the method for manufacturing the semiconductor interconnect structure further includes: before closing the support structure receiving groove to form the air gap unit, filling the support structure receiving groove with an isolation material, and forming an isolation structure replacing the air gap unit with the isolation material.

[0135] Illustratively, the dielectric constant of the isolation structure is smaller than the dielectric constant of the isolation dielectric layer.

[0136] For example, the isolation structure 514 can be made of long-chain organic matter with stable chemical properties and high temperature resistance, such as acrylic and resin materials, to ensure that the isolation structure 514 can enhance the structural strength of the isolation anti-collapse structure 5 after curing, thereby enhancing the structural strength of the semiconductor interconnection structure.

[0137] Some embodiments of the present disclosure also provide an electronic device, including: a semiconductor interconnect structure as described in any of the above embodiments; or a semiconductor interconnect structure prepared by a manufacturing method as described in any of the above embodiments. The electronic device also has the technical advantages of the above semiconductor interconnect structure, which will not be described in detail here.

[0138] For example, electronic devices include, but are not limited to, devices such as televisions, computers, mobile phones, or tablets.

[0139] For example, the electronic device includes a circuit board and a packaging structure. One or more chips are welded on the circuit board, and the semiconductor interconnection structure as described above can be used in the chip to realize signal transmission. The packaging structure can package and protect the chip. In addition, the electronic device may also include a power supply for providing an operating voltage to the chip.

[0140] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor interconnect structure, characterized in that: Located above the device functional area of ​​the substrate, it includes: a plurality of interconnection layers stacked in a direction away from the substrate, and an isolation and collapse prevention structure located between every two adjacent interconnection layers; The interconnection layer includes an insulating dielectric layer and at least two conductive structures penetrating the insulating dielectric layer and spaced apart in a direction parallel to the substrate; The isolation and collapse prevention structure includes: one or more support structures penetrating the insulating dielectric layer and located in the interval between each two adjacent conductive structures, and an isolation dielectric layer covering the interconnection layer and connecting the support structures.

2. The semiconductor interconnect structure according to claim 1, wherein: The dielectric constant of the isolation dielectric layer is smaller than the dielectric constant of the insulating dielectric layer; the dielectric constant of the support structure is smaller than or equal to the dielectric constant of the isolation dielectric layer.

3. The semiconductor interconnect structure according to claim 1, wherein: An air gap unit is enclosed inside the supporting structure; Alternatively, an isolation structure is enclosed inside the support structure, and the dielectric constant of the isolation structure is smaller than the dielectric constant of the isolation dielectric layer.

4. The semiconductor interconnect structure according to claim 1, wherein: The support structure comprises an arched support structure; The arch support structure includes: a bottom wall support layer, a bridge wall support layer located on the bottom wall support layer and arranged in an arch shape, and an air gap unit located in the arch space formed by the bottom wall support layer and the bridge wall support layer.

5. The semiconductor interconnect structure according to claim 4, wherein: The isolation medium layer is a first isolation layer; the bottom wall support layer, the bridge wall support layer and the first isolation layer are integrally formed; Or, the isolation dielectric layer includes a first isolation layer and a second isolation layer which are stacked; The bridge wall support layer includes: a side bridge wall support layer located on the bottom wall support layer, and a top bridge wall support layer closed and connected to the side bridge wall support layer; wherein the bottom wall support layer, the side bridge wall support layer and the first isolation layer are integrally formed; and the top bridge wall support layer and the second isolation layer are integrally formed.

6. A method for manufacturing a semiconductor interconnect structure, characterized in that: Providing a substrate, wherein the substrate has a device functional area; A multi-layer interconnection layer and a multi-layer isolation and collapse prevention structure are alternately formed above the device functional area of ​​the substrate; the interconnection layer includes an insulating dielectric layer and at least two conductive structures penetrating the insulating dielectric layer and spaced apart in a direction parallel to the substrate; The isolation and collapse prevention structure includes: one or more support structures penetrating the insulating dielectric layer and located in the interval between each two adjacent conductive structures, and an isolation dielectric layer covering the interconnection layer and connecting the support structures.

7. The method for manufacturing a semiconductor interconnect structure according to claim 6, wherein: Forming the interconnection layer and the isolation and anti-collapse structure comprises: forming a sacrificial protrusion shaped like the support structure; forming an insulating dielectric layer covering the sacrificial protrusion, and the conductive structure penetrating the insulating dielectric layer and located beside the sacrificial protrusion in a direction parallel to the substrate; Etching the insulating dielectric layer to form an opening, wherein the opening exposes the top of the sacrificial protrusion; Removing the sacrificial protrusion based on the opening to form a supporting structure accommodating groove; Forming a bottom wall support layer conformally covering the inner wall of the support structure accommodating groove and a side bridge wall support layer connected to the bottom wall support layer, and a first isolation layer covering the top surfaces of both the insulating medium layer and the conductive structure and connecting the side bridge wall support layer; forming a top bridge wall supporting layer filling the opening to close and connect the side bridge wall supporting layers, and a second insulating layer covering the first insulating layer; Wherein, the isolation dielectric layer includes the first isolation layer and the second isolation layer; The support structure includes the bottom wall support layer, the side bridge wall support layer, the top bridge wall support layer, and an air gap unit formed by the bottom wall support layer, the side bridge wall support layer, and the top bridge wall support layer closing the support structure accommodating groove.

8. The method for manufacturing a semiconductor interconnect structure according to claim 6, wherein: Forming the interconnection layer and the isolation and anti-collapse structure comprises: forming a sacrificial protrusion shaped like the support structure; forming an initial insulating dielectric layer covering the sacrificial protrusion, and an initial conductive structure penetrating the initial insulating dielectric layer and located beside the sacrificial protrusion in a direction parallel to the substrate; Grinding the initial insulating dielectric layer and the initial conductive structure until the top of the sacrificial protrusion is exposed to form the insulating dielectric layer and the conductive structure; Removing the sacrificial protrusion to form a supporting structure accommodating groove; Forming a bottom wall support layer conformally covering the inner wall of the support structure accommodating groove, a bridge wall support layer sealing and connecting the bottom wall support layer, and a first isolation layer covering the top surfaces of both the insulating medium layer and the conductive structure and connecting the bridge wall support layer; Wherein, the isolation medium layer is the first isolation layer; The support structure includes the bottom wall support layer, the bridge wall support layer, and an air gap unit formed by the bottom wall support layer and the bridge wall support layer closing the support structure accommodating groove.

9. The method for manufacturing a semiconductor interconnect structure according to claim 7 or 8, characterized in that: Also includes: Before the support structure receiving groove is closed to form the air gap unit, an isolation material is filled in the support structure receiving groove, and the isolation material forms an isolation structure replacing the air gap unit.

10. An electronic device, characterized in that: include: The semiconductor interconnect structure according to any one of claims 1 to 5; Or, a semiconductor interconnect structure prepared by the manufacturing method according to any one of claims 6 to 8.

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