Electronic package and fabrication method thereof
By using a combination of thermal conductivity chips and circuit structures and electronic components in semiconductor packages, the problem of insufficient heat dissipation and electrical performance in the prior art is solved, and more efficient heat dissipation and electrical performance improvements are achieved.
Patent Information
- Application Number
- CN202311150746.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-30
- Filing Date
- 2023-09-07
- Publication Date
- 2025-02-28
AI Technical Summary
There are shortcomings in existing semiconductor packages when taking into account both heat dissipation and electrical performance, and it is difficult to improve heat dissipation and electrical performance at the same time to meet the needs of future electronic products.
The combination of thermal conductivity chips and circuit structures and electronic components is adopted to electrically connect the conductive columns through the conductive perforation of the thermal conductivity chip to increase the heat conduction effect, and other chips are connected to the thermal conductivity chip to improve the electrical performance.
It effectively improves the heat dissipation effect of electronic components and enhances the electrical performance of electronic packages. It can take into account both the heat dissipation needs and electrical performance without requiring a large amount of additional cost.
Smart Images
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Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor device, in particular to an electronic package and a manufacturing method thereof. Background Art
[0002] As the demand for electronic products in terms of functions and processing speed increases, semiconductor chips, as the core components of electronic products, need to have higher density electronic components and electronic circuits, which means that semiconductor chips will generate more heat energy during operation.
[0003] In order to quickly dissipate the heat energy into the atmosphere, Figure 1 As shown, the manufacturing method of the conventional semiconductor package 1 is to first place the semiconductor chip 11 on the package substrate 10, and then form the package layer 12 on the package substrate 10 to cover the semiconductor chip 11. Then, the heat sink 14 (heat sink or heat spreader) is combined with the semiconductor chip 11 and the package layer 12 (with poor heat conduction effect) through the heat conductive layer 13 to dissipate the heat energy generated by the semiconductor chip 11 through the heat conductive layer 13 and the heat sink 14, wherein the heat conductive layer 13 can be a thermal interface material (TIM) or backside metal. In addition, a plurality of conductive elements 15 can be arranged under the package substrate 10 for connection to an external circuit board.
[0004] However, although the thermal conductive layer 13 formed on the composite surface formed by the semiconductor chip 11 and the packaging layer 12 can achieve a good heat dissipation effect, the heat sink 14 is arranged on the packaging substrate 10, and a plurality of conductive elements 15 are arranged on the lower side of the packaging substrate 10. Then, the electrical performance of the semiconductor package 1 is limited by the number of chips between the heat sink 14 and the conductive elements 15.
[0005] Therefore, how to achieve good heat dissipation of the semiconductor package 1 while increasing the electrical performance of the semiconductor package 1 to meet future product requirements has become an urgent issue to be solved in the current industry. Summary of the invention
[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a circuit structure having a circuit layer and a first side and a second side opposite to each other; an electronic component disposed on the first side of the circuit structure and electrically connected to the circuit layer; and a thermally conductive chip disposed on the electronic component, so that the electronic component is sandwiched between the circuit structure and the thermally conductive chip.
[0007] The electronic package as mentioned above further includes a plurality of conductive pillars disposed between the first side of the circuit structure and the heat conductive chip and electrically connected to the circuit layer.
[0008] As in the aforementioned electronic package, the heat conductive chip has a plurality of conductive through-holes, and the plurality of conductive through-holes are electrically connected to the circuit layer via the plurality of conductive pillars.
[0009] As in the aforementioned electronic package, the electronic component is disposed on the first side of the circuit structure via a plurality of conductive bumps.
[0010] As in the aforementioned electronic package, it further includes a packaging layer disposed between the first side of the circuit structure and the heat-conducting chip to cover the electronic element and the plurality of conductive pillars.
[0011] As in the aforementioned electronic package, the electronic component is disposed on the first side of the circuit structure via a plurality of conductive bumps, and a bottom glue covering the plurality of conductive bumps is formed between the electronic component and the first side of the circuit structure.
[0012] As in the aforementioned electronic package, the electronic component is disposed on the first side of the circuit structure via a plurality of conductive bumps, and a packaging layer covering the plurality of conductive bumps, the electronic component and the plurality of conductive pillars is formed between the thermal conductive chip and the first side of the circuit structure.
[0013] As in the aforementioned electronic package, the second side of the circuit structure is configured with at least one functional element and at least one conductive element.
[0014] As in the aforementioned electronic package, a heat dissipation material is disposed between the heat conductive chip and the electronic element.
[0015] As in the aforementioned electronic package, at least one functional element is disposed on the heat conductive chip.
[0016] The present invention also provides a method for manufacturing an electronic package, comprising: providing a heat-conducting chip, an electronic component and a circuit structure, wherein the circuit structure has a circuit layer and a first side and a second side opposite to each other; and arranging the electronic component between the first side of the circuit structure and the heat-conducting chip so that the electronic component is electrically connected to the circuit layer.
[0017] As in the aforementioned method for manufacturing an electronic package, the heat conductive chip has a plurality of conductive through holes.
[0018] The method for manufacturing the electronic package as mentioned above further includes forming a plurality of conductive pillars on the thermal conductive chip so that the plurality of conductive pillars are electrically connected to the plurality of conductive through holes.
[0019] In the manufacturing method of the electronic package as mentioned above, the electronic component is first arranged on the first side of the circuit structure via a plurality of conductive bumps, and then a plurality of conductive pillars are arranged on the first side of the circuit structure to electrically connect the circuit layer, and at the same time the thermal conductive chip is placed on the electronic component.
[0020] As in the aforementioned method for manufacturing the electronic package, the method further includes forming a primer between the electronic component and the first side of the circuit structure to cover the plurality of conductive bumps.
[0021] The method for manufacturing the electronic package as described above further includes forming a packaging layer between the first side of the circuit structure and the heat-conducting chip to cover the electronic element, the plurality of conductive pillars and the bottom glue.
[0022] In the aforementioned method for manufacturing an electronic package, the electronic component having a plurality of conductive bumps is disposed on the heat conductive chip.
[0023] The method for manufacturing the electronic package as described above also includes forming a packaging layer on the thermally conductive chip to cover the electronic element, the plurality of conductive pillars and the plurality of conductive bumps, and exposing the end surfaces of the plurality of conductive pillars and the end surfaces of the plurality of conductive bumps to the packaging layer.
[0024] As in the aforementioned method for manufacturing an electronic package, a plurality of conductive pillars and the plurality of conductive bumps are placed on the first side of the circuit structure, and the circuit layer is electrically connected to the plurality of conductive pillars and the plurality of conductive bumps.
[0025] The method for manufacturing the electronic package as mentioned above further includes disposing at least one functional element and at least one conductive element on the second side of the circuit structure.
[0026] As in the aforementioned method for manufacturing the electronic package, a heat dissipation material is disposed between the heat conductive chip and the electronic element.
[0027] As in the aforementioned method for manufacturing an electronic package, at least one functional element is disposed on the heat conductive chip.
[0028] In summary, the electronic package and its manufacturing method of the present invention can increase the heat dissipation effect of the electronic components by stacking the heat-conducting chip on the packaging layer and the electronic components. In addition, the heat-conducting chip can also be connected to other chips, so the electrical performance of the electronic package can be increased. The electronic package and its manufacturing method of the present invention can be completed with existing processes, machines and materials, without a large amount of additional cost expenditure, and can take into account both the heat dissipation requirements and the electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.
[0030] FIG. 2A to FIG. 2DIt is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.
[0031] FIG. 3A to FIG. 3D FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to another embodiment of the present invention.
[0032] Main component symbols
[0033] 1 Semiconductor Package
[0034] 10 Package substrate
[0035] 11. Semiconductor Chip
[0036] 12 Encapsulation layer
[0037] 13. Thermal Conductive Layer
[0038] 14 Heat sink
[0039] 15 Conductive element
[0040] 2,3 Electronic packaging
[0041] 20 Line structure
[0042] 20a First side
[0043] 20b Second side
[0044] 201 Dielectric layer
[0045] 202 Line Layer
[0046] 21 Electronic components
[0047] 21a Action surface
[0048] 21b Non-active surface
[0049] 22 Conductive bumps
[0050] 23 Primer
[0051] 24 Heat dissipation material
[0052] 25 Thermal Conductive Chip
[0053] 25a First side
[0054] 25b Second side
[0055] 251 Conductive Perforation
[0056] 252 Pad
[0057] 26 Conductive Column
[0058] 27 Encapsulation layer
[0059] 28a First functional element
[0060] 28b Second functional element
[0061] 29 Conductive element
[0062] 3a Encapsulation module. DETAILED DESCRIPTION
[0063] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0064] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "first", and "second" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.
[0065] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.
[0066] like Figure 2A As shown, a circuit structure 20 and at least one electronic component 21 are provided, and the electronic component 21 is disposed on the circuit structure 20 .
[0067] The circuit structure 20 has a first side 20a and a second side 20b opposite to each other, and includes at least one dielectric layer 201 and a circuit layer 202 combined with the dielectric layer 201. For example, the material forming the circuit layer 202 may be copper, and the material forming the dielectric layer 201 may be polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials, and the circuit layer 202 and the dielectric layer 201 may be formed by a redistribution layer (RDL) process.
[0068] The electronic component 21 can be an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite to each other.
[0069] In this embodiment, a plurality of conductive bumps 22 such as copper pillars, solder balls, etc. may be formed on the active surface 21a of the electronic component 21, and a heat dissipation material 24 may be formed on the inactive surface 21b of the electronic component 21, wherein the heat dissipation material 24 may be, for example, a thermal interface material (TIM) or a backside metal, such as a high thermal conductivity metal glue material, a solder material, or a metal material (which may be a multi-layer metal material). Next, the electronic component 21 is flip-chip bonded to the first side 20a of the circuit structure 20 via the plurality of conductive bumps 22, so that the electronic component 21 is electrically connected to the circuit layer 202. Afterwards, a primer 23 is formed between the electronic component 21 and the first side 20a of the circuit structure 20 to cover the conductive bumps 22.
[0070] like Figure 2B As shown, a heat-conducting chip 25 is also provided. The heat-conducting chip 25 has a first side 25a and a second side 25b opposite to each other, and includes a plurality of conductive through-holes 251 and a plurality of pads 252. The conductive through-holes 251 may be conductive through-silicon vias (TSVs) that penetrate the heat-conducting chip 25. The pads 252 are formed on the first side 25a and the second side 25b, respectively, and some of the plurality of pads 252 are connected to opposite ends of the conductive through-holes 251. Then, a plurality of conductive pillars 26 (such as copper pillars) are formed on the plurality of pads 252 on the first side 25a of the heat-conducting chip 25, so that the plurality of conductive pillars 26 are electrically connected to the plurality of conductive through-holes 251.
[0071] In this embodiment, the thermal conductive chip 25 is a silicon base thermal die, which may or may not have electrical functions. In addition, non-electrical thermal conductive silicon vias (not shown) may also be arranged in the thermal conductive chip 25, which are only used to connect the conductive pillars 26 for heat conduction.
[0072] It should be understood that the above Figure 2A The process shown is similar to Figure 2B The processes shown are not in any particular order and can be performed first according to the needs. Figure 2A The process or first Figure 2B process, or simultaneously Figure 2A and Figure 2B process.
[0073] like Figure 2CAs shown, a plurality of conductive posts 26 together with a heat-conducting chip 25 are disposed on the first side 20a of the circuit structure 20, so that the plurality of conductive posts 26 are electrically connected to the circuit layer 202, and a heat dissipation material 24 is disposed between the first side 25a of the heat-conducting chip 25 and the non-active surface 21b of the electronic component 21 to increase the heat conduction effect.
[0074] like Figure 2D As shown, a packaging layer 27 is formed between the first side 20a of the circuit structure 20 and the first side 25a of the heat-conducting chip 25 to cover the electronic component 21, a plurality of conductive pillars 26, the bottom glue 23 and the heat dissipation material 24. In this embodiment, the material forming the packaging layer 27 is an insulating material, such as an epoxy packaging colloid. Afterwards, at least one first functional element 28a (such as an active chip or a passive element) and a plurality of conductive elements 29 (such as solder balls) electrically connected to the circuit layer 202 can be arranged on the second side 20b of the circuit structure 20, and at least one second functional element 28b can be selectively connected to the second side 25b of the heat-conducting chip 25 to enhance the electrical function (such as an active chip or a passive element), thereby obtaining the electronic package 2 of the present invention, and in the subsequent process, the electronic package 2 can be connected to an electronic device (not shown) such as a circuit board through the plurality of conductive elements 29.
[0075] In one embodiment, the Figure 2A In the process of forming the heat dissipation material 24 on the non-active surface 21b of the electronic component 21, Figure 2C In the manufacturing process, the first side 25a of the heat conductive chip 25 will be directly attached to the inactive surface 21b of the electronic component 21 (not shown).
[0076] FIG. 3A to FIG. 3D FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an electronic package according to another embodiment of the present invention. FIG. 3A to FIG. 3D The technical content described is the same as the aforementioned FIG. 2A to FIG. 2D The part will not be repeated.
[0077] like Figure 3AAs shown, a heat-conducting chip 25 is provided. The heat-conducting chip 25 has a first side 25a and a second side 25b opposite to each other, and includes a plurality of conductive through-holes 251 (such as conductive through-silicon vias (TSV) for short) and a plurality of pads 252, wherein the plurality of conductive through-holes 251 penetrate the heat-conducting chip 25, and the plurality of pads 252 are respectively formed on the first side 25a and the second side 25b, and part of the plurality of pads 252 are connected to the opposite ends of the conductive through-holes 251. Then, a plurality of conductive pillars 26 (such as copper pillars) are formed on the plurality of pads 252 on the first side 25a of the heat-conducting chip 25, so that the plurality of conductive pillars 26 are electrically connected to the plurality of conductive through-holes 251. In addition, non-electrical thermally conductive through-silicon vias (not shown) may also be arranged in the heat-conducting chip 25, which are only used to connect the conductive pillars 26 for heat conduction.
[0078] like Figure 3B As shown, an electronic component 21 having an opposite active surface 21a and an inactive surface 21b is provided, a plurality of conductive bumps 22 such as copper pillars, solder balls, etc. are formed on the active surface 21a, and a heat dissipation material 24 is formed on the inactive surface 21b, wherein the heat dissipation material 24 is a thermal interface material (TIM) or backside metal, such as a high thermal conductivity metal glue material, solder material or metal material (which can be a multi-layer metal material). In this embodiment, the electronic component 21 is connected to the first side 25a of the thermal conductive chip 25 through the heat dissipation material 24.
[0079] In one embodiment, the process of forming the heat dissipation material 24 on the inactive surface 21 b of the electronic component 21 may be omitted. In this case, the inactive surface 21 b of the electronic component 21 is attached to the first side 25 a of the thermal conductive chip 25 .
[0080] like Figure 3C As shown, a packaging layer 27 is formed on the first side 25a of the heat-conducting chip 25 and the active surface 21a of the electronic element 21 to cover the electronic element 21, a plurality of conductive pillars 26, a plurality of conductive bumps 22 and the heat dissipation material 24 to form a packaging module 3a. In this embodiment, the material forming the packaging layer 27 is an insulating material, such as an epoxy packaging colloid, which can be formed by molding, lamination or coating.
[0081] Furthermore, the packaging layer 27 may first completely cover the conductive bumps 22 and the conductive pillars 26 , and then perform a flattening process on the top surface of the packaging layer 27 by grinding or the like, so that the end surfaces of the conductive bumps 22 and the conductive pillars 26 are exposed from the packaging layer 27 .
[0082] like Figure 3DAs shown, a circuit structure 20 is also provided. The circuit structure 20 has a first side 20a and a second side 20b opposite to each other, and includes at least one dielectric layer 201 and a circuit layer 202 combined with the dielectric layer 201. In the present embodiment, the aforementioned packaging module 3a is placed on the first side 20a of the circuit structure 20, and a plurality of conductive pillars 26 and a plurality of conductive bumps 22 are electrically connected to the circuit layer 202. Afterwards, at least one first functional element 28a (such as an active chip or a passive element) and a plurality of conductive elements 29 (such as solder balls) electrically connected to the circuit layer 202 can be configured on the second side 20b of the circuit structure 20, and at least one second functional element 28b can be selectively placed on the second side 25b of the thermal conductive chip 25 to enhance the electrical function, thereby obtaining the electronic package 3 of the present invention, and in the subsequent process, the electronic package 3 can be placed on an electronic device such as a circuit board (not shown) through a plurality of conductive elements 29. Another method of making Figure 3D The structure is Figure 3C After a planarization process is performed on the top surface of the packaging layer 27 by grinding or the like, a patterning process is continued to form stacked dielectric layers 201 and circuit layers 202 one by one to form the circuit structure 20.
[0083] The present invention also provides an electronic package 2, 3, which includes a circuit structure 20, an electronic component 21, multiple conductive bumps 22, a thermal conductive chip 25, multiple conductive columns 26, a packaging layer 27, at least one functional element (such as a first functional element 28a and a second functional element 28b) and multiple conductive elements 29.
[0084] The circuit structure 20 has a first side 20 a and a second side 20 b opposite to each other, and includes at least one dielectric layer 201 and a circuit layer 202 combined with the dielectric layer 201 .
[0085] The electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other. A plurality of conductive bumps 22 such as copper pillars and solder balls are formed on the active surface 21a, and a heat dissipation material 24 is formed on the inactive surface 21b. The electronic component 21 is flip-chip bonded to the first side 20a of the circuit structure 20 via the plurality of conductive bumps 22, so that the electronic component 21 is electrically connected to the circuit layer 202. In one embodiment, the heat dissipation material 24 may be omitted from being formed on the inactive surface 21b.
[0086] The thermal conductive chip 25 may be a silicon-based thermal chip having a first side 25a and a second side 25b opposite to each other, and including a plurality of conductive through holes 251 and a plurality of pads 252, wherein the plurality of conductive through holes 251 penetrate the thermal conductive chip 25, and the plurality of pads 252 are respectively formed on the first side 25a and the second side 25b and connected to opposite ends of the conductive through holes 251. The first side 25a of the thermal conductive chip 25 is connected to the inactive surface 21b of the electronic component 21 via the heat dissipation material 24. Alternatively, the heat dissipation material 24 may be omitted, so that the first side 25a of the thermal conductive chip 25 is connected to the inactive surface 21b of the electronic component 21.
[0087] The plurality of conductive pillars 26 are formed between the first side 20 a of the circuit structure 20 and the first side 25 a of the thermal conductive chip 25 , and electrically connect the circuit layer 202 and the plurality of pads 252 , and the plurality of conductive through-holes 251 are electrically connected to the circuit layer 202 via the plurality of conductive pillars 26 .
[0088] The packaging layer 27 is formed between the first side 20 a of the circuit structure 20 and the first side 25 a of the heat conducting chip 25 to cover the electronic component 21 and the plurality of conductive pillars 26 .
[0089] In one embodiment, an underfill 23 covering the plurality of conductive bumps 22 is formed between the active surface 21 a of the electronic element 21 and the first side 20 a of the circuit structure 20 , and the packaging layer 27 covers the underfill 23 at the same time.
[0090] In another embodiment, the base glue 23 is not formed between the active surface 21 a of the electronic component 21 and the first side 20 a of the circuit structure 20 , but a packaging layer 27 is formed so that the packaging layer 27 can cover a plurality of conductive bumps 22 at the same time.
[0091] The first functional element 28a (such as an active chip or a passive element) and a plurality of conductive elements 29 (such as solder balls) can be disposed on the second side 20b of the circuit structure 20 and electrically connected to the circuit layer 202 for being placed in an electronic device such as a circuit board. In addition, at least one second functional element 28b can be placed on the second side 25b of the heat conductive chip 25 to enhance the electrical function.
[0092] In summary, the electronic package and its manufacturing method of the present invention stacks the heat-conducting chip on the packaging layer and the electronic component so that the heat generated by the operation of the electronic component can be transferred to the outside through the heat-conducting chip (such as the conductive through hole), thereby increasing the heat dissipation effect of the electronic component. In addition, other chips can be placed on the heat-conducting chip to increase the electrical performance of the electronic package. In addition, the electronic package and its manufacturing method of the present invention can be completed with existing processes, machines and materials, without a large amount of additional cost expenditure, and can take into account both heat dissipation requirements and electrical performance.
[0093] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.
Claims
1. An electronic package, comprising: A circuit structure having a circuit layer and a first side and a second side opposite to each other; An electronic component is disposed on the first side of the circuit structure and electrically connected to the circuit layer; as well as The heat-conducting chip is arranged on the electronic element, and the electronic element is sandwiched between the circuit structure and the heat-conducting chip.
2. The electronic package of claim 1, wherein: The electronic package also includes a plurality of conductive pillars disposed between the first side of the circuit structure and the heat conductive chip and electrically connected to the circuit layer.
3. The electronic package of claim 2, wherein: The heat-conducting chip has a plurality of conductive through-holes, and the plurality of conductive through-holes are electrically connected to the circuit layer via the plurality of conductive pillars.
4. The electronic package of claim 1, wherein: The electronic component is arranged on the first side of the circuit structure via a plurality of conductive bumps.
5. The electronic package of claim 2, wherein: The electronic package also includes a packaging layer disposed between the first side of the circuit structure and the heat-conducting chip to cover the electronic element and the plurality of conductive pillars.
6. The electronic package of claim 1, wherein: The electronic component is arranged on the first side of the circuit structure via a plurality of conductive bumps, and a bottom glue covering the plurality of conductive bumps is formed between the electronic component and the first side of the circuit structure.
7. The electronic package of claim 2, wherein: The electronic component is arranged on the first side of the circuit structure via a plurality of conductive bumps, and a packaging layer covering the plurality of conductive bumps, the electronic component and the plurality of conductive pillars is formed between the heat conductive chip and the first side of the circuit structure.
8. The electronic package of claim 1, wherein: At least one functional element and at least one conductive element are disposed on the second side of the circuit structure.
9. The electronic package of claim 1, wherein: A heat dissipation material is arranged between the heat-conducting chip and the electronic element.
10. The electronic package of claim 1, wherein: At least one functional element is disposed on the heat-conducting chip.
11. A method for manufacturing an electronic package, comprising: A heat-conducting chip, an electronic component and a circuit structure are provided, wherein the circuit structure has a circuit layer and a first side and a second side opposite to each other; as well as The electronic component is arranged between the first side of the circuit structure and the heat-conducting chip, and the electronic component is electrically connected to the circuit layer.
12. The method for manufacturing an electronic package according to claim 11, wherein: The heat-conducting chip has a plurality of conductive through holes.
13. The method for manufacturing an electronic package according to claim 12, wherein: The manufacturing method also includes forming a plurality of conductive pillars on the heat conductive chip so that the plurality of conductive pillars are electrically connected to the plurality of conductive through holes.
14. The method for manufacturing an electronic package according to claim 13, wherein: The manufacturing method first arranges the electronic component on the first side of the circuit structure via a plurality of conductive bumps, then arranges a plurality of conductive pillars on the first side of the circuit structure to electrically connect the circuit layer, and simultaneously places the heat conductive chip on the electronic component.
15. The method for manufacturing an electronic package according to claim 14, wherein: The manufacturing method further comprises forming a base glue between the electronic element and the first side of the circuit structure to cover the plurality of conductive bumps.
16. The method for manufacturing an electronic package according to claim 15, wherein: The manufacturing method further includes forming a packaging layer between the first side of the circuit structure and the heat-conducting chip to cover the electronic element, the plurality of conductive pillars and the bottom glue.
17. The method for manufacturing an electronic package according to claim 13, wherein: The manufacturing method arranges the electronic component with a plurality of conductive bumps on the heat-conducting chip.
18. The method for manufacturing an electronic package according to claim 17, wherein: The manufacturing method also includes forming a packaging layer on the heat-conducting chip to cover the electronic element, the plurality of conductive columns and the plurality of conductive bumps, and making the end surfaces of the plurality of conductive columns and the end surfaces of the plurality of conductive bumps exposed to the packaging layer.
19. The method for manufacturing an electronic package according to claim 18, wherein: The manufacturing method places a plurality of conductive pillars and the plurality of conductive bumps on the first side of the circuit structure, and enables the circuit layer to electrically connect the plurality of conductive pillars and the plurality of conductive bumps.
20. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method also includes configuring at least one functional element and at least one conductive element on the second side of the circuit structure.
21. The method for manufacturing an electronic package according to claim 11, wherein: A heat dissipation material is arranged between the heat-conducting chip and the electronic element.
22. The method for manufacturing an electronic package according to claim 11, wherein: At least one functional element is disposed on the heat-conducting chip.