Low-power-consumption power switch control circuit
By controlling the conduction and turn-off of the second MOS tube in the power switch control circuit, the voltages at both ends of the resistor are equal, the problem of high power consumption when the existing power switch circuit is turned on is solved, and low power consumption and high energy efficiency power switch control is achieved.
Patent Information
- Application Number
- CN202411539862.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-28
AI Technical Summary
The existing power switching circuit will generate high power consumption when the switching device is turned on, mainly due to the on-resistance of the circuit.
A low-power power switch control circuit is adopted, the circuit includes a first MOS tube, a second MOS tube, a third MOS tube, and a resistor one and a resistor two connected in series between the second MOS tube and the third MOS tube. By controlling the conduction and turn-off of the second MOS tube, the voltages at both resistor one and resistor two are equal, thereby avoiding the generation of additional power consumption.
The circuit does not generate additional power consumption when switching, improving overall energy efficiency, and is suitable for battery-powered devices or applications that have strict requirements on energy efficiency, extending the device's usage time and improving user satisfaction.
Smart Images
Figure CN119543592A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of power supplies, and in particular to a low-power consumption power switch control circuit. Background Art
[0002] The power switch control circuit is a circuit used to control the power on and off in the power system. Its main function is to connect or disconnect the current, thereby controlling the working state of the circuit or equipment. The power switch can be mechanical, such as relays, contactors, switches, etc., or semiconductor.
[0003] like Figure 1 The power switch circuit of the prior art shown includes a transistor Q4, a resistor R7 and a resistor R8. The transistor Q4 is used as a switch. The resistors R7 and R8 are connected to the collector of the transistor Q4 to limit the current or divide the voltage to protect the components from being damaged by excessive current. Under normal circumstances, the transistor Q4 is closed and no current passes through the resistors R7 and R8. When the circuit needs to be turned on, the base of the transistor Q4 is made to obtain sufficient voltage, and the transistor Q4 will be turned on.
[0004] The power switch circuit of the prior art has some obvious defects: when the switch device is turned on, the current flowing through the component will generate high power consumption, which mainly comes from the on-resistance of the circuit. For example, in the circuit of the prior art mentioned above, when the transistor Q4 is turned on, the current can flow to the ground through the resistor R7 and the resistor R8, so additional power consumption will be generated when the current passes. Power consumption will affect the efficiency and heat dissipation requirements of the circuit, and is an important factor that needs to be considered in circuit design, which needs to be properly managed and controlled during design. Summary of the invention
[0005] In view of the above-mentioned defects of the prior art, the present invention provides a low-power consumption power switch control circuit, which can ensure that when the power switch is turned on, the on-resistance does not generate additional power consumption.
[0006] In order to achieve the above object, the technical solution adopted by the present invention is: A low-power power switch control circuit comprises: a first MOS tube, a second MOS tube, a third MOS tube, and a resistor 1 and a resistor 2 connected in series between the second MOS tube and the third MOS tube; the resistor 1 and the resistor 2 are connected to the gate of the first MOS tube; the first MOS tube is connected in series between an input end and an output end and is used to control the on and off of a power supply; the source of the second MOS tube is connected to the input end, and the gate thereof is connected to a second control signal end; the third MOS tube is grounded, and the gate thereof is connected to the first control signal end; The first control signal terminal and the second control signal terminal adjust the levels, and when the first MOS tube is turned on, the second MOS tube is controlled to be turned off, so that the voltages across the resistor 1 and the resistor 2 as a whole are equal.
[0007] The first MOS tube is the main switch element, and its conduction and cutoff control the on and off of the power supply. Resistor 1 and resistor 2 are on-resistances, which are used to limit current or divide voltage and protect components from damage by excessive current. The conduction or cutoff of the first MOS tube determines the state of the output end. When the first MOS tube is cut off, the output end is 0V, which means that no current flows through the load, so no power consumption is generated. The first control signal end and the second control signal end adjust the level to control the second MOS tube to be cut off while realizing the conduction of the first MOS tube, so that the voltages at both ends of resistor 1 and resistor 2 in the circuit are equal, thereby no additional power consumption is generated.
[0008] Preferably, the first MOS tube and the second MOS tube are PMOS tubes; and the third MOS tube is an NMOS tube.
[0009] By using PMOS transistors as the first and second MOS transistors, and NMOS transistors as the third MOS transistors, the specific characteristics of these devices can be used to optimize circuit performance. PMOS transistors are turned on when the source-drain voltage is positive, while NMOS transistors are turned on when the gate-source voltage is positive. This configuration allows the circuit to operate under different voltage polarities while providing lower on-resistance and fast switching speed.
[0010] Preferably, a fourth MOS tube is provided in the circuit between the gate of the second MOS tube and the second control signal terminal; the fourth MOS tube is an NMOS tube; the gate of the second MOS tube is connected to the output terminal; wherein, when the first control signal terminal outputs a high level and the second control signal terminal is a low level, the third MOS tube is turned on, the second MOS tube is turned off, and the first MOS tube is turned on.
[0011] When the first control signal terminal outputs a high level and the second control signal terminal is a low level, the fourth MOS tube is cut off, and the gate voltage of the second MOS tube is equal to the output terminal voltage. Since the input terminal voltage is approximately equal to the output terminal voltage, the second MOS tube is cut off, which is equivalent to introducing a high impedance in the circuit, preventing the current from flowing through the second MOS tube. Even if the first MOS tube is turned on, the current cannot form a closed loop through the second MOS tube, and the resistors 1 and 2 will not consume additional power.
[0012] Preferably, a resistor three is connected in series in the circuit between the gate of the second MOS tube and the drain of the fourth MOS tube; and a resistor five is connected in series between the gate of the second MOS tube and the output end.
[0013] A resistor 3 is connected in series between the gate of the second MOS tube and the second control signal terminal, and a resistor 5 is connected in series between the gate of the second MOS tube and the output terminal, which is used to limit current, divide voltage or stabilize the gate voltage, thereby controlling the conduction state of the second MOS tube and protecting the circuit. This configuration helps prevent the gate voltage from being too high or the current from being too large, thereby protecting the MOS tube from damage.
[0014] Preferably, a resistor four is connected in series between the gate of the third MOS tube and the first control signal terminal.
[0015] Connecting resistor 4 in series between the gate of the third MOS tube and the first control signal terminal helps control the conduction speed of the third MOS tube and reduce the current spike during switching, thereby protecting the circuit and improving stability. This configuration can reduce electromagnetic interference and power supply noise in the circuit and improve the overall performance and reliability of the circuit.
[0016] Preferably, a resistor six is connected in series between the gate of the fourth MOS tube and the second control signal terminal.
[0017] A resistor 6 is connected in series between the gate of the fourth MOS tube and the second control signal terminal, which can limit the current flowing into the gate of the fourth MOS tube to prevent excessive current from damaging the gate of the fourth MOS tube. The resistor 6 can help match the output impedance of the signal source at the second control signal terminal with the input impedance of the gate of the fourth MOS tube to reduce signal reflection and interference. The resistor 6 can also stabilize the working point of the fourth MOS tube to prevent a large fluctuation in the working state of the fourth MOS tube due to a slight change in the input signal.
[0018] Preferably, the first control signal terminal and the second control signal terminal are both microcontroller pins.
[0019] Using microcontroller pins as the control signal source allows the circuit to interface directly with a microcontroller or other digital circuits, simplifying circuit design and increasing integration.
[0020] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The circuit of the present invention controls the conduction and cutoff of the second MOS tube so that the voltages across resistors 1 and 2 are balanced, and no additional power consumption is generated. By reducing unnecessary power consumption, the circuit improves the overall energy efficiency and provides a more energy-efficient switching circuit for battery-powered devices or applications with strict requirements on energy efficiency. By reducing unnecessary power consumption, the use time of the device can be directly extended, and user satisfaction can be improved. The circuit can be integrated into power management modules of various applications with strict requirements on energy efficiency, providing support for more efficient energy utilization.
[0021] 2. For power-sensitive devices, such as lithium-ion battery products, by reducing the extra power consumption generated by the circuit, more peripherals can be added to the product when customers need to open new functions. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 is a circuit diagram of the prior art; Figure 2 This is a circuit diagram of Example 1.
[0023] in: Q1, first MOS tube; Q2, second MOS tube; N1, third MOS tube; N2, fourth MOS tube; Vin, input end; Vout, output end; Vin_CTRL1, first control signal end; Vin_CTRL2, second control signal end; R1, resistor one; R2, resistor two; R3, resistor three; R4, resistor four; R5, resistor five; R6, resistor six. DETAILED DESCRIPTION
[0024] In order to make the technical means, creative features, objectives and effects of the invention easier to understand, the invention is further described with reference to specific diagrams. However, the invention is not limited to the following implementation cases.
[0025] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.
[0026] Embodiment 1: like Figure 2A low-power switch control circuit shown in the figure comprises: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor N1, and a resistor R1 and a resistor R2 connected in series between the second MOS transistor Q2 and the third MOS transistor N1; the resistor R1 and the resistor R2 are connected to the gate of the first MOS transistor Q1; the first MOS transistor Q1 is connected in series between the input terminal Vin and the output terminal Vout and is used to control the on and off of the power supply; the source of the second MOS transistor Q2 is connected to the input terminal Vin, and the gate thereof is connected to the second control signal terminal Vin_CTRL2; the third MOS transistor N1 is grounded and the gate thereof is connected to the first control signal terminal Vin_CTRL1; wherein the first control signal terminal Vin_CTRL1 and the second control signal terminal Vin_CTRL2 control the second MOS transistor Q2 to be turned off when the first MOS transistor Q1 is turned on by adjusting the level, so that the voltages at both ends of the resistor R1 and the resistor R2 as a whole are equal.
[0027] The first MOS tube Q1 is the main switch element, and its conduction and cutoff control the on and off of the power supply. Resistor 1 R1 and resistor 2 R2 are on-resistances, which are used to limit current or divide voltage and protect components from damage by excessive current. The conduction or cutoff of the first MOS tube Q1 determines the state of the output terminal Vout. When the first MOS tube Q1 is cut off, the output terminal Vout is 0, which means that no current flows through the load, so no power consumption is generated. The first control signal terminal Vin_CTRL1 and the second control signal terminal Vin_CTRL2 adjust the level to control the second MOS tube Q2 to be cut off while realizing the conduction of the first MOS tube Q1, so that the voltages at both ends of the resistor 1 R1 and the resistor 2 R2 in the circuit are equal, so that no additional power consumption is generated.
[0028] In this embodiment, the first MOS transistor Q1 and the second MOS transistor Q2 are PMOS transistors of model "RZR040P01TL"; the third MOS transistor N1 is an NMOS transistor of model "RTR0N03TL". A fourth MOS transistor N2 is provided in the circuit between the gate of the second MOS transistor Q2 and the second control signal terminal Vin_CTRL2, and the fourth MOS transistor N2 is an NMOS transistor of model "RTR0N03TL"; the gate of the second MOS transistor Q2 is connected to the output terminal Vout; wherein, when the first control signal terminal Vin_CTRL1 outputs a high level and the second control signal terminal Vin_CTRL2 is a low level, the third MOS transistor N1 is turned on, the second MOS transistor Q2 is turned off, and the first MOS transistor Q1 is turned on.
[0029] By using PMOS transistors as the first MOS transistor Q1 and the second MOS transistor Q2, and NMOS transistors as the third MOS transistor N1, the specific characteristics of these devices can be used to optimize circuit performance. The PMOS transistor is turned on when the source-drain voltage is positive, while the NMOS transistor is turned on when the gate-source voltage is positive. This configuration allows the circuit to operate under different voltage polarities while providing lower on-resistance and fast switching speed.
[0030] When the first control signal terminal Vin_CTRL1 outputs a high level and the second control signal terminal Vin_CTRL2 is a low level, the fourth MOS tube N2 is cut off, and the gate voltage of the second MOS tube Q2 is equal to the output terminal Vout voltage. Since the input terminal Vin voltage is approximately equal to the output terminal Vout voltage, the second MOS tube Q2 is cut off, which is equivalent to introducing a high impedance in the circuit, preventing the current from flowing through the second MOS tube Q2. Even if the first MOS tube Q1 is turned on, the current cannot form a closed loop through the second MOS tube Q2, and the resistor R1 and the resistor R2 will not consume additional power.
[0031] The control logic of this embodiment is as follows: Case 1: the second control signal terminal Vin_CTRL2 is at a low level of 0V, and the first control signal terminal Vin_CTRL1 is at a high level of 3.3V.
[0032] The second MOS tube Q2 is turned off: the fourth MOS tube N2 is turned off, and the gate voltage of the second MOS tube Q2 is equal to the output terminal Vout voltage. For the PMOS tube, when the gate voltage is equal to the source voltage, the PMOS tube is turned off, that is, not conducting.
[0033] The third MOS tube N1 is turned on: when the first control signal terminal Vin_CTRL1 is 3.3V, the gate voltage of the third MOS tube N1 is pulled up to 3.3V through the resistor R4. For the NMOS tube, when the gate voltage is higher than the source voltage (here grounded, the source voltage is 0V), the NMOS tube is turned on, that is, the current is allowed to flow from the drain to the source.
[0034] The first MOS transistor Q1 is turned on: since the third MOS transistor N1 is turned on, for the first MOS transistor Q1, when the gate voltage is lower than the source voltage, the first MOS transistor Q1 is turned on, allowing current to flow from the source to the drain.
[0035] The output terminal Vout outputs the voltage of the input terminal Vin: since the first MOS tube Q1 is turned on, the voltage of the output terminal Vout is pulled up to a voltage close to the voltage of the input terminal Vin.
[0036] Case 2: The second control signal terminal Vin_CTRL2 is at a high level of 3.3V, and the first control signal terminal Vin_CTRL1 is at a low level of 0V The second MOS tube Q2 is turned on: the fourth MOS tube N2 is turned on. For the PMOS tube, when the gate voltage is lower than the source voltage, the PMOS tube is turned on, that is, the current is allowed to flow from the drain to the source.
[0037] The third MOS tube N1 is turned off: when the first control signal terminal Vin_CTRL1 is 0 V, the gate voltage of the third MOS tube N1 is pulled down to 0 V. For the NMOS tube, when the gate voltage is equal to the source voltage (here grounded, 0 V), the NMOS tube is turned off.
[0038] The first MOS transistor Q1 is turned off: since the third MOS transistor N1 is turned off, the gate of the first MOS transistor Q1 is connected to the input terminal Vin through the resistor R1, and the gate voltage of the first MOS transistor Q1 is maintained at the voltage of the input terminal Vin. For the first MOS transistor Q1, when the gate voltage is equal to the source voltage, the first MOS transistor Q1 is turned off, that is, it is not conducting.
[0039] The output terminal Vout does not output voltage: since the first MOS tube Q1 is cut off, the output terminal Vout does not output voltage, that is, the voltage of the output terminal Vout is isolated and will not be affected by the input terminal Vin.
[0040] Preferably, a resistor R3 is connected in series in the circuit between the gate of the second MOS transistor Q2 and the drain of the fourth MOS transistor N2; a resistor R5 is connected in series between the gate of the second MOS transistor Q2 and the output terminal Vout. A resistor R4 is connected in series between the gate of the third MOS transistor N1 and the first control signal terminal Vin_CTRL1. A resistor R6 is connected in series between the gate of the fourth MOS transistor N2 and the second control signal terminal Vin_CTRL2.
[0041] A resistor R3 is connected in series between the gate of the second MOS transistor Q2 and the second control signal Vin_CTRL2, and a resistor R5 is connected in series between the gate of the second MOS transistor Q2 and the output terminal Vout, which is used to limit current, divide voltage or stabilize the gate voltage, thereby controlling the conduction state of the second MOS transistor Q2 and protecting the circuit. This configuration helps prevent the gate voltage from being too high or the current from being too large, thereby protecting the MOS transistor from damage.
[0042] A resistor R4 is connected in series between the gate of the third MOS tube N1 and the first control signal terminal Vin_CTRL1, which helps to control the conduction speed of the third MOS tube N1 and reduce the current spike during switching, thereby protecting the circuit and improving stability. This configuration can reduce electromagnetic interference and power supply noise in the circuit and improve the overall performance and reliability of the circuit.
[0043] A resistor R6 is connected in series between the gate of the fourth MOS tube N2 and the second control signal Vin_CTRL2, which can limit the current flowing into the gate of the fourth MOS tube N2, and prevent the gate of the fourth MOS tube N2 from being damaged by excessive current. The resistor R6 can help match the output impedance of the second control signal Vin_CTRL2 signal source with the input impedance of the gate of the fourth MOS tube N2, and reduce signal reflection and interference. The resistor R6 can also stabilize the working point of the fourth MOS tube N2, and prevent the working state of the fourth MOS tube N2 from fluctuating greatly due to slight changes in the input signal.
[0044] In this embodiment, the first control signal terminal Vin_CTRL1 and the second control signal terminal Vin_CTRL2 are both microcontroller pins, and their effective levels are high level 3.3V and low level 0V. The input terminal Vin voltage is a wide range voltage, and its voltage effective value is 2-24V, that is, the circuit is effective when the input terminal Vin voltage is 2-24V. 24V depends on the model of the P-Mos tube used, and the effective range of voltage of different P-Mos tube models varies slightly.
[0045] The application of this circuit in communication modules. Due to the differences in communication modules, our company's communication modules can be used in two ways. One is the power-off mode at ordinary times, and the power is supplied only when in use. The other mode is the PSM mode (pulse skipping mode, a working mode used in a switching power converter). In this mode, the communication module is always powered and remains connected to the base station. If a traditional circuit is used, the second mode will generate an additional 2-10uA of power consumption, but this will not happen when using this circuit.
[0046] In summary, the circuit of the present invention controls the conduction and cutoff of the second MOS tube Q2 so that the voltage across the resistor 1 R1 and the resistor 2 R2 is balanced, and no additional power consumption is generated. By reducing unnecessary power consumption, the circuit improves the overall energy efficiency and provides a more energy-saving switching circuit for battery-powered devices or applications with strict requirements on energy efficiency. By reducing unnecessary power consumption, the use time of the device can be directly extended and the user satisfaction can be improved. It can be integrated into the power management module of various applications with strict requirements on energy efficiency to provide support for more efficient energy utilization.
Claims
1. A low power consumption power switch control circuit, characterized in that: The invention comprises: a first MOS tube (Q1), a second MOS tube (Q2), a third MOS tube (N1), and a resistor 1 (R1) and a resistor 2 (R2) connected in series between the second MOS tube (Q2) and the third MOS tube (N1); the resistor 1 (R1) and the resistor 2 (R2) are connected to the gate of the first MOS tube (Q1); the first MOS tube (Q1) is connected in series between an input end (Vin) and an output end (Vout) and is used to control the on and off of a power supply; the source of the second MOS tube (Q2) is connected to the input end (Vin), and its gate is connected to a second control signal end (Vin_CTRL2); the third MOS tube (N1) is grounded, and its gate is connected to the first control signal end (Vin_CTRL1); The first control signal terminal (Vin_CTRL1) and the second control signal terminal (Vin_CTRL2) adjust the level so that when the first MOS tube (Q1) is turned on, the second MOS tube (Q2) is controlled to be turned off, so that the voltages across the resistor 1 (R1) and the resistor 2 (R2) are equal.
2. The low power consumption power switch control circuit according to claim 1, characterized in that: The first MOS tube (Q1) and the second MOS tube (Q2) are PMOS tubes; and the third MOS tube (N1) is an NMOS tube.
3. The low power consumption power switch control circuit according to claim 2, characterized in that: A fourth MOS tube (N2) is provided in the circuit between the gate of the second MOS tube (Q2) and the second control signal terminal (Vin_CTRL2); the fourth MOS tube (N2) is an NMOS tube; the gate of the second MOS tube (Q2) is connected to the output terminal (Vout); wherein, when the first control signal terminal (Vin_CTRL1) outputs a high level and the second control signal terminal (Vin_CTRL2) is a low level, the third MOS tube (N1) is turned on, the second MOS tube (Q2) is turned off, and the first MOS tube (Q1) is turned on.
4. The low power consumption power switch control circuit according to claim 3, characterized in that: A resistor three (R3) is connected in series in the circuit between the gate of the second MOS tube (Q2) and the drain of the fourth MOS tube (N2); and a resistor five (R5) is connected in series between the gate of the second MOS tube (Q2) and the output end (Vout).
5. The low power consumption power switch control circuit according to claim 3, characterized in that: A resistor four (R4) is connected in series between the gate of the third MOS tube (N1) and the first control signal terminal (Vin_CTRL1).
6. The low power consumption power switch control circuit according to claim 3, characterized in that: A resistor six (R6) is connected in series between the gate of the fourth MOS tube (N2) and the second control signal terminal (Vin_CTRL2).
7. The low power consumption power switch control circuit according to any one of claims 1 to 6, characterized in that: The first control signal terminal (Vin_CTRL1) and the second control signal terminal (Vin_CTRL2) are both microcontroller pins.