Class D power amplifier circuit for realizing high voltage resistance by adopting low-voltage device and control method

Abstract

The invention discloses a D-type power amplifier circuit for realizing high voltage resistance by adopting a low-voltage device and a control method. The D-type power amplifier circuit comprises an MOS (Metal Oxide Semiconductor) tube module, a non-overlapping control module, a bias voltage generation module, a bias voltage buffer module, a PMOS (P-channel Metal Oxide Semiconductor) driving control module and an NMOS (N-channel Metal Oxide Semiconductor) driving control module, the non-overlapping control module outputs a non-overlapping control P signal and a non-overlapping control N signal; the bias voltage generation module is used for generating a bias signal output by the PMOS power tube; the bias voltage buffer module is connected with the grid electrode of the second NMOS tube, and the bias voltage buffer module is used for converting the bias signal voltage into a driving voltage signal to control the grid electrode of the second NMOS tube and providing a driving control signal for the PMOS driving control module; the PMOS driving control module is used for performing grid control on the first PMOS tube; and the NMOS driving control module is used for performing grid control on the first NMOS tube. A high-voltage-resistant D-type power amplifier can be realized by adopting a low-voltage device, the circuit damage risk is reduced, and the chip manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of class D power amplifiers, and in particular to a class D power amplifier circuit and a control method for achieving high voltage resistance by using low voltage devices. Background Art

[0002] In electronic products, the signal usually needs to be amplified before it can drive the next level of circuit to work. For example, in an audio playback system, the audio signal is amplified before being connected to the speaker. The module that performs power amplification is usually called an amplifier module. Common types of amplifiers include Class A, Class B, Class AB and Class D. Class D amplifiers have the characteristics of high efficiency and small size.

[0003] In a system-level chip, processors, storage, peripherals, signal processing modules and power amplifiers are usually integrated into one chip to simplify the number of board-level chips and peripheral components. In CMOS integrated circuit design, devices have a voltage range, and exceeding the voltage range will cause damage to the integrated circuit device. Voltage damage to CMOS devices is usually caused by gate-source breakdown and gate-drain breakdown. For example, the maximum operating voltage of the core device is 1.32V, and the maximum operating voltage of the IO device is 3.63V; and the power amplifier module requires a very high output power, so it is generally powered directly by an external power supply, and the voltage is usually 5V. The maximum voltage of the gate-source voltage and gate-drain voltage of the driving tube of the Class D power amplifier circuit is the module power supply voltage. When the power supply of the circuit is greater than 3.63V, the circuit is at risk of damage. The voltage range of integrated circuit devices is strongly related to the manufacturing process. If a higher operating voltage needs to be supported, a new manufacturing process needs to be adopted, thereby increasing the chip manufacturing cost. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a class D power amplifier circuit and control method that uses low-voltage devices to achieve high-voltage resistance, which can use low-voltage devices to achieve high-voltage resistance class D power amplifiers, reduce circuit damage risks, and reduce chip manufacturing costs.

[0005] On the one hand, an embodiment of the present invention provides a class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance, including a MOS tube module, a non-overlapping control module, a bias voltage generating module, a bias voltage buffer module, a PMOS drive control module and an NMOS drive control module; the MOS tube module includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the source of the first PMOS tube is connected to the drain of the second PMOS tube, the source of the first NMOS tube NM0 is connected to the ground, and the drain of the first NMOS tube is connected to the drain of the second NMOS tube; the input of the non-overlapping control module is a PA_DIN signal, the PA_DIN signal is a digital signal modulated by PWM, the non-overlapping control module delays the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal; the bias voltage The generating module is used to generate a bias signal output by the PMOS power tube to avoid the gate-source and gate-drain of the MOS tube module being greater than the rated voltage; the bias voltage buffer module is connected to the gate of the second NMOS tube, and the bias voltage buffer module is used to convert the bias signal voltage into a driving voltage signal to control the gate of the second NMOS tube, and provide a driving control signal to the PMOS driving control module; the input of the PMOS driving control module is a non-overlapping control P signal, the PMOS driving control module is connected to the gate of the first PMOS tube, and the PMOS driving control module is used to perform gate control on the first PMOS tube; the input of the NMOS driving control module is a non-overlapping control N signal, the NMOS driving control module is connected to the gate of the first NMOS tube, and the NMOS driving control module is used to perform gate control on the first NMOS tube.

[0006] According to some embodiments of the present invention, the non-overlapping control module includes multiple buffers, which perform delay processing on the PA_DIN signal and output non-overlapping control P signals and non-overlapping control N signals. The non-overlapping control P signal is output by performing an OR operation on the PA_DIN signal and the PA_DLY delay signal, and the non-overlapping control N signal is output by performing an AND operation on the PA_DIN signal and the PA_DLY delay signal. The PA_DLY delay signal is a delayed signal of the PA_DIN signal.

[0007] According to some embodiments of the present invention, the bias voltage generating module includes a first bias NMOS tube, a second bias NMOS tube, a third bias NMOS tube, a first bias PMOS tube, a second bias PMOS tube and a third bias PMOS tube, the gate and drain of the first bias PMOS tube are connected to the source of the second bias PMOS tube, the gate and drain of the second bias PMOS tube are connected to the source of the third bias PMOS tube, the gate and drain of the third bias PMOS tube are connected to the source of the first bias NMOS tube, the drain is connected to the gate of the first bias NMOS tube connected to the second resistor, the second bias NMOS tube and the third bias NMOS tube are connected to form a current mirror structure, when the power supply voltage VCC5 is greater than 3.3V, the voltage higher than 3.3V is borne by the first bias PMOS tube, the second bias PMOS tube and the third bias PMOS tube, the first bias NMOS tube is a protection tube to ensure that the output of the power supply voltage VCC5-3.3 is not greater than 3.3V.

[0008] According to some embodiments of the present invention, the bias voltage buffer module includes a first buffer NMOS tube, a second buffer NMOS tube, a third buffer NMOS tube, a fourth buffer NMOS tube, a first buffer PMOS tube, a second buffer PMOS tube, a third buffer PMOS tube and a fourth buffer PMOS tube, the source of the first buffer NMOS tube is connected to the drain of the second buffer NMOS tube, the source and gate of the second buffer NMOS tube are connected to the drain of the third buffer NMOS tube, the drain of the first buffer PMOS tube is connected to the source of the second buffer PMOS tube, the drain of the second buffer PMOS tube is connected to the source of the third buffer PMOS tube, and the third buffer PMOS tube is connected to the drain of the third buffer NMOS tube. The gate of the fourth buffer PMOS tube is connected to the gate of the fourth buffer PMOS tube, the drain of the fourth buffer PMOS tube is connected to the source of the fourth buffer PMOS tube, the first buffer NMOS tube and the second buffer NMOS tube form a first differential amplifier, the voltage generated by the first differential amplifier at the VBN terminal is VCC5-3.3+VGS, the first buffer PMOS tube and the second buffer PMOS tube form a second differential amplifier, the voltage generated by the second differential amplifier at the VBP terminal is VCC5-3.3-VGS, the fourth buffer NMOS tube and the fourth buffer PMOS tube form a source follower, and the source follower makes the output protection control P signal voltage VCC5-3.3.

[0009] According to some embodiments of the present invention, the PMOS drive control module includes a first drive NMOS tube, a second drive NMOS tube, a third drive NMOS tube, a fourth drive NMOS tube, a fifth drive NMOS tube, a sixth drive NMOS tube, a first drive PMOS tube, a second drive PMOS tube, a third drive PMOS tube, a fourth drive PMOS tube, a fifth drive PMOS tube and a sixth drive PMOS tube. When the non-overlapping control P signal is high, the third drive NMOS tube and the fourth drive NMOS tube will pull the protection control E signal down to VCC5-3.3V. When the third drive PMOS tube is turned on, the drive control P signal outputs VCC5. When the non-overlapping control P signal is low, the fifth drive NMOS tube and the sixth drive NMOS tube will pull the drive control P signal down to VCC5-3.3V.

[0010] According to some embodiments of the present invention, the NMOS drive control module includes a plurality of inverters, and the plurality of inverters are used to amplify the drive signal step by step.

[0011] According to some embodiments of the present invention, the PMOS drive control module PA_VDRVP outputs a PMOS drive control signal. When the first PMOS tube is turned on, the output of the PMOS drive control signal is no greater than VCC5-3.3V to protect the gate-source voltage of the first PMOS tube from being greater than 3.3V.

[0012] According to some embodiments of the present invention, the bias voltage buffer module outputs a PMOS protection control signal. When the second PMOS tube is turned on, the output of the PMOS protection control signal is VCC5-3.3V to protect the gate-source voltage of the second PMOS tube from being greater than 3.6V.

[0013] According to some embodiments of the present invention, the second NMOS tube is connected to a first resistor, a first end of the first resistor is connected to the gate of the second NMOS tube, and the other end of the first resistor R1 is connected to a voltage power supply for protecting the gate-drain voltage of the first NMOS tube from being greater than 3.3V.

[0014] On the other hand, an embodiment of the present invention provides a method for controlling a class D power amplifier that can withstand high voltage by using a low voltage device, comprising: The non-overlapping control module performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal; The bias voltage generation module generates a bias signal output by the PMOS power tube; The bias voltage buffer module converts the bias signal into a driving voltage signal to control the gate of the second NMOS tube, and provides a driving control signal to the PMOS driving control module; The PMOS drive control module performs gate control on the first PMOS tube; The NMOS drive control module performs gate control on the first NMOS tube; The gates of the first PMOS tube and the first NMOS tube are controlled so that the gate-to-drain voltage is not greater than the withstand voltage range.

[0015] The embodiments of the present invention have at least the following beneficial effects: The present invention provides a class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance, including a MOS tube module, a non-overlapping control module, a bias voltage generation module, a bias voltage buffer module, a PMOS drive control module, and an NMOS drive control module. A VCC5-3.3V reference voltage is generated by the bias voltage generation module, and the signal load capacity is enhanced by the bias voltage buffer module to generate a protection control P signal for controlling the second NMOS tube. The PMOS drive control module performs gate control on the first PMOS tube, and the NMOS drive control module performs gate control on the first NMOS tube; the gate of the second NMOS tube is clamped by the power supply voltage VCC3. By stacking multiple PMOS tubes and NMOS tubes and controlling the gate of each MOS tube to ensure that the gate-source voltage and the gate-drain voltage are not greater than its withstand voltage range, a class D power amplifier that can withstand high voltage can be achieved by using low-voltage devices, reducing the risk of circuit damage and reducing chip manufacturing costs.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the circuit structure of a class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to an embodiment of the present invention; Figure 2 for Figure 1 The working timing diagram of the class D power amplifier circuit shown; Figure 3 for Figure 1 A schematic diagram of the circuit structure of a non-overlapping control module of a class D power amplifier circuit is shown; Figure 4 for Figure 1 A schematic diagram of the circuit structure of a bias voltage generating module of a class D power amplifier circuit is shown; Figure 5 for Figure 1 A schematic diagram of the circuit structure of a bias voltage buffer module of a class D power amplifier circuit is shown; Figure 6 for Figure 1 A schematic diagram of the circuit structure of a PMOS drive control module of a class D power amplifier circuit is shown; Figure 7 for Figure 1 A schematic diagram of the circuit structure of an NMOS drive control module of a class D power amplifier circuit is shown; Figure 8 The present invention is a flowchart of a method for controlling a high-voltage-resistant class-D power amplifier using low-voltage devices according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0020] In the description of the present invention, "several" means one or more, "multiple" means more than two, greater than, less than, and exceeding are understood as not including the number itself, and "above", "below", and "within" are understood as including the number itself. If there is a description of "first", "second", etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] In the description of the present invention, unless otherwise clearly defined, words such as “set”, “install”, “connect” and “connected” should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above words in the present invention based on the specific content of the technical solution.

[0022] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments.

[0023] Please refer to Figure 1 and Figure 2The present embodiment discloses a class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance, including a MOS tube module, a non-overlap control module PA_NONLAP, a bias voltage generation module PA_VBGEN, a bias voltage buffer module PA_VBBUF, a PMOS drive control module PA_VDRVP and an NMOS drive control module PA_VDRVN. The MOS tube module includes a first PMOS tube PM0, a second PMOS tube PM1, a first NMOS tube NM0 and a second NMOS tube NM1, the source of the first PMOS tube is connected to the drain of the second PMOS tube, the source of the first NMOS tube NM0 is connected to the ground, and the drain of the first NMOS tube NM0 is connected to the drain of the second NMOS tube NM1; the input of the non-overlapping control module PA_NONLAP is the PA_DIN signal, which is a digital signal modulated by PWM. The non-overlapping control module PA_NONLAP delays the PA_DIN signal and outputs a non-overlapping control P signal NONLAPP and a non-overlapping control N signal NONLAPN; the bias voltage generating module PA_VBGEN is used to generate a bias signal VCC5-3.3 output by the PMOS power tube to avoid the gate source and gate drain of the MOS tube module being greater than the rated voltage; the bias voltage buffer module PA_VBBUF is connected The gate of the second NMOS tube NM1, the bias voltage buffer module PA_VBBUF is used to convert the bias signal VCC5-3.3 voltage into a voltage signal with driving capability to control the gate of the second NMOS tube NM1, and provide the PMOS drive control module with a control signal of driving capability; the input of the PMOS drive control module PA_VDRVP is the non-overlapping control P signal NONLAPP, the PMOS drive control module PA_VDRVP is connected to the gate of the first PMOS tube PM0, and the PMOS drive control module PA_VDRVP is used to perform gate control on the first PMOS tube PM0; the input of the NMOS drive control module PA_VDRVN is the non-overlapping control N signal NONLAPN, the NMOS drive control module PA_VDRVN is connected to the gate of the first NMOS tube NM0, and the NMOS drive control module PA_VDRVN is used to perform gate control on the first NMOS tube NM0.

[0024] Please refer to Figure 3The non-overlapping control module PA_NONLAP includes multiple buffers, which delay the PA_DIN signal and output the non-overlapping control P signal NONLAPP and the non-overlapping control N signal NONLAPN. The non-overlapping control P signal NONLAPP is output by performing an OR operation on the PA_DIN signal and the PA_DLY delay signal, and the non-overlapping control N signal NONLAPN is output by performing an AND operation on the PA_DIN signal and the PA_DLY delay signal, and the PA_DLY delay signal is a delayed signal of the PA_DIN signal. The non-overlapping control module PA_NONLAP generates two non-overlapping signals, which can prevent the PMOS power tube and the NMOS power tube from being turned on at the same time.

[0025] Please refer to Figure 4 The bias voltage generating module PA_VBGEN includes a first bias NMOS tube NM10, a second bias NMOS tube NM11, a third bias NMOS tube NM12, a first bias PMOS tube PM10, a second bias PMOS tube PM11, a third bias PMOS tube PM12 and a second resistor R11. The gate and drain of the first bias PMOS tube PM10 are connected to the source of the second bias PMOS tube PM11, the gate and drain of the second bias PMOS tube PM11 are connected to the source of the third bias PMOS tube PM12, and the third bias PMOS tube PM10 is connected to the source of the third bias PMOS tube PM11. The gate and drain of 2 are connected to the source of the first bias NMOS tube PM10, the drain is connected to the gate of the first bias NMOS tube PM10 connected to the second resistor R11, the second bias NMOS tube NM11 and the third bias NMOS tube NM12 are connected to form a current mirror structure. When the power supply voltage VCC5 is greater than 3.3V, the voltage higher than 3.3V is borne by the first bias PMOS tube PM0, the second bias PMOS tube PM1 and the third bias PMOS tube PM2. The first bias NMOS tube NM0 is a protection tube to ensure that the output of VCC5-3.3 is not greater than 3.3V.

[0026] Please refer to Figure 5The bias voltage buffer module PA_VBBUF includes a first buffer NMOS tube NM20, a second buffer NMOS tube NM21, a third buffer NMOS tube NM22, a fourth buffer NMOS tube NM23, a first buffer PMOS tube PM20, a second buffer PMOS tube PM21, a third buffer PMOS tube PM22 and a fourth buffer PMOS tube PM23. The source of the first buffer NMOS tube NM20 is connected to the drain of the second buffer NMOS tube NM21, the source and gate of the second buffer NMOS tube NM21 are connected to the drain of the third buffer NMOS tube NM22, the drain of the first buffer PMOS tube PM20 is connected to the source of the second buffer PMOS tube PM21, the drain of the second buffer PMOS tube PM21 is connected to the source of the third buffer PMOS tube PM22, and the third buffer PMOS tube PM23 is connected to the drain of the third buffer NMOS tube NM22. The gate of the buffer PMOS tube PM22 is connected to the gate of the fourth buffer PMOS tube PM23, the drain of the fourth buffer PMOS tube PM23 is connected to the source of the fourth buffer PMOS tube PM23, the first buffer NMOS tube NM20 and the second buffer NMOS tube NM21 form a first differential amplifier, the voltage generated by the first differential amplifier at the VBN terminal is VCC5-3.3+VGS, the first buffer PMOS tube PM20 and the second buffer PMOS tube PM21 form a second differential amplifier, the voltage generated by the second differential amplifier at the VBP terminal is VCC5-3.3-VGS, the fourth buffer NMOS tube NM23 and the fourth buffer PMOS tube PM23 form a source follower, the source follower makes the output voltage of the PMOS protection control signal VPRCP be VCC5-3.3.

[0027] Please refer to Figure 6The PMOS driving control module PA_VDRVP includes a first driving NMOS transistor NM30, a second driving NMOS transistor NM31, a third driving NMOS transistor NM32, a fourth driving NMOS transistor NM33, a fifth driving NMOS transistor NM34, a sixth driving NMOS transistor NM35, a first driving PMOS transistor PM30, a second driving PMOS transistor PM31, a third driving PMOS transistor PM32, a fourth driving PMOS transistor PM33, a fifth driving PMOS transistor PM34 and a sixth driving PMOS transistor PM35, wherein the non-overlapping control PB signal NONLAPP_B is overlapped with the non-overlapping control P signal NONLAPP corresponds; when the non-overlap control P signal NONLAPP is high, the third drive NMOS tube NM32 and the fourth drive NMOS tube NM33 will pull the protection control E signal VPRE down to VCC5-3.3V, and when the fifth drive PMOS tube PM34 is turned on, the drive control signal VDRVP outputs VCC5, and when the non-overlap control P signal NONLAPP is low, the non-overlap control PB signal NONLAPP_B is high, and the fifth drive NMOS tube NM34 and the sixth drive NMOS tube NM35 will pull the drive control signal VDRVP down to VCC5-3.3V.

[0028] Please refer to Figure 7 The NMOS drive control module PA_VDRVN includes a plurality of inverters, and the plurality of inverters are used to amplify the drive signal step by step.

[0029] Please refer to Figure 1 and Figure 2 The PMOS drive control module PA_VDRVP outputs a PMOS drive control signal VDRVP. When the first PMOS tube PM0 is turned on, the output of the PMOS drive control signal VDRVP is not greater than VCC5-3.3V to protect the gate-source voltage of the first PMOS tube PM0 from being greater than 3.3V.

[0030] Please refer to Figure 1 and Figure 2 The bias voltage buffer module PA_VBBUF outputs a PMOS protection control signal VPRCP. When the second PMOS tube PM1 is turned on, the output of the PMOS protection control signal VPRCP is VCC5-3.3V to protect the gate-source voltage of the second PMOS tube PM1 from being greater than 3.6V.

[0031] Please refer to Figure 1 and Figure 2 The second NMOS tube NM1 is connected to a first resistor R1, a first end of the first resistor R1 is connected to the gate of the second NMOS tube NM1, and the other end of the first resistor R1 is connected to a voltage power supply VCC3 to protect the gate-drain voltage of the first NMOS tube NM0 from being greater than 3.3V.

[0032] Please refer to Figure 8 This embodiment also provides a class D power amplifier control method for implementing a high-voltage resistant class D power amplifier circuit using low-voltage devices, which mainly includes steps S101 to S106: S101 , a non-overlap control module PA_NONLAP performs delay processing on a PA_DIN signal and outputs a non-overlap control P signal NONLAPP and a non-overlap control N signal NONLAPN.

[0033] S102, the bias voltage generating module PA_VBGEN generates a bias signal VCC5-3.3 output by the PMOS power tube.

[0034] S103 , the bias voltage buffer module converts the bias signal VCC5-3.3 into a driving voltage signal to control the gate of the second NMOS transistor NM1 , and provides a driving control signal to the PMOS driving control module.

[0035] S104 , the PMOS driving control module performs gate control on the first PMOS transistor PM0 .

[0036] S105 . The NMOS driving control module PA_VDRVN controls the gate of the first NMOS transistor NM0 .

[0037] S106 , controlling the gates of the first PMOS transistor PM0 and the first NMOS transistor NM0 so that the gate-to-drain voltage is not greater than a withstand voltage range.

[0038] Please refer to Figure 1, a VCC5-3.3V reference voltage is generated through the bias voltage generation module PA_VBGEN, and the signal load capacity is enhanced through the bias voltage buffer module PA_VBBUF to generate a PMOS protection control signal VPRCP for controlling the second NMOS tube PM1. The control signal of the first PMOS tube PM0 is generated by the PMOS drive control module PA_VDRVP. The gate of the second NMOS tube NM1 is clamped by the power supply voltage VCC3. In order to protect the gate-source voltage of the power first PMOS tube PM0 from being greater than 3.3V, the drive control P signal VDRVP outputs a minimum of VCC5-3.3V when the first PMOS tube PM0 is turned on. In order to protect the gate-source power supply of the second PMOS tube PM1 from being greater than 3.6V, the PMOS protection control signal VPRCP outputs a fixed VCC5-3.3V. In order to protect the gate-drain voltage of the first NMOS tube NM0 from being greater than 3.3V, the NMOS protection control signal VPRCN outputs a fixed 3.3V. The NMOS drive control module PA_VDRVN drives the first NMOS tube NM0. If the output signal PA_OUT is to output a low level, the NMOS drive control module PA_VDRVN drives VDRVN to high. At this time, the first NMOS tube NM0 is turned on and the second NMOS tube NM1 is normally open. Then the output signal PA_OUT is driven to a low level. On the contrary, if the output signal PA_OUT is to output a high level, the NMOS drive control module PA_VDRVN drives the drive control N signal VDRVN to low. At this time, the first NMOS tube NM0 is turned off and the second NMOS tube NM1 is normally open. Then the output signal PA_OUT is controlled by the first PMOS tube PM0 and the second PMOS tube PM1 to output a high level. By stacking multiple PMOS tubes and NMOS tubes and controlling the gate of each MOS tube to ensure that the gate-source voltage and the gate-drain voltage are not greater than its withstand voltage range, a high-voltage-resistant Class D power amplifier can be realized using low-voltage devices, reducing the risk of circuit damage and reducing chip manufacturing costs.

[0039] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A class D power amplifier circuit that uses low voltage devices to achieve high voltage resistance, characterized in that: include: A MOS tube module, the MOS tube module comprising a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the source of the first PMOS tube being connected to the drain of the second PMOS tube, the source of the first NMOS tube being connected to the ground, and the drain of the first NMOS tube being connected to the drain of the second NMOS tube; A non-overlapping control module, wherein the input of the non-overlapping control module is a PA_DIN signal, wherein the PA_DIN signal is a digital signal modulated by PWM, and the non-overlapping control module performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal; A bias voltage generating module, the bias voltage generating module is used to generate a bias signal to prevent the gate source and gate drain of the MOS tube module from being greater than the rated voltage; A PMOS drive control module, the input of which is a non-overlapping control P signal, the PMOS drive control module is connected to the gate of the first PMOS tube, and the PMOS drive control module is used to perform gate control on the first PMOS tube; A bias voltage buffer module, the bias voltage buffer module is connected to the gate of the second NMOS tube, the bias voltage buffer module is used to convert the bias signal into a driving voltage signal to control the gate of the second NMOS tube, and provide a driving control signal to the PMOS driving control module; An NMOS drive control module, the input of which is a non-overlapping control N signal, the NMOS drive control module is connected to the gate of the first NMOS tube, and the NMOS drive control module is used to control the gate of the first NMOS tube.

2. The class D power amplifier circuit that uses low voltage devices to achieve high voltage resistance according to claim 1, characterized in that: The non-overlapping control module includes multiple buffers, which delay the PA_DIN signal and output non-overlapping control P signals and non-overlapping control N signals. The non-overlapping control P signal is output by performing an OR operation on the PA_DIN signal and the PA_DLY delay signal, and the non-overlapping control N signal is output by performing an AND operation on the PA_DIN signal and the PA_DLY delay signal. The PA_DLY delay signal is a delayed signal of the PA_DIN signal.

3. The class D power amplifier circuit that uses low voltage devices to achieve high voltage resistance according to claim 1, characterized in that: The bias voltage generating module includes a first bias NMOS tube, a second bias NMOS tube, a third bias NMOS tube, a first bias PMOS tube, a second bias PMOS tube, a third bias PMOS tube and a second resistor. The gate and drain of the first bias PMOS tube are connected to the source of the second bias PMOS tube, the gate and drain of the second bias PMOS tube are connected to the source of the third bias PMOS tube, the gate and drain of the third bias PMOS tube are connected to the source of the first bias NMOS tube, the drain is connected to the gate of the first bias NMOS tube and connected to the second resistor, the second bias NMOS tube and the third bias NMOS tube are connected to form a current mirror structure, when the power supply voltage VCC5 is greater than 3.3V, the voltage higher than 3.3V is borne by the first bias PMOS tube, the second bias PMOS tube and the third bias PMOS tube, the first bias NMOS tube is a protection tube to ensure that the output of the power supply voltage VCC5-3.3 is not greater than 3.3V.

4. The class D power amplifier circuit that uses low voltage devices to achieve high voltage resistance according to claim 1, characterized in that: The bias voltage buffer module includes a first buffer NMOS tube, a second buffer NMOS tube, a third buffer NMOS tube, a fourth buffer NMOS tube, a first buffer PMOS tube, a second buffer PMOS tube, a third buffer PMOS tube and a fourth buffer PMOS tube, the source of the first buffer NMOS tube is connected to the drain of the second buffer NMOS tube, the source and gate of the second buffer NMOS tube are connected to the drain of the third buffer NMOS tube, the drain of the first buffer PMOS tube is connected to the source of the second buffer PMOS tube, the drain of the second buffer PMOS tube is connected to the source of the third buffer PMOS tube, and the gate of the third buffer PMOS tube is connected to the The gate of the fourth buffer PMOS tube, the drain of the fourth buffer PMOS tube is connected to the source of the fourth buffer PMOS tube, the first buffer NMOS tube and the second buffer NMOS tube form a first differential amplifier, the voltage generated by the first differential amplifier at the VBN terminal is VCC5-3.3+VGS, the first buffer PMOS tube and the second buffer PMOS tube form a second differential amplifier, the voltage generated by the second differential amplifier at the VBP terminal is VCC5-3.3-VGS, the fourth buffer NMOS tube and the fourth buffer PMOS tube form a source follower, and the source follower makes the output voltage VPRCP be VCC5-3.

3.

5. The class D power amplifier circuit using low voltage devices to achieve high voltage resistance according to claim 1, characterized in that: The PMOS drive control module includes a first drive NMOS tube, a second drive NMOS tube, a third drive NMOS tube, a fourth drive NMOS tube, a fifth drive NMOS tube, a sixth drive NMOS tube, a first drive PMOS tube, a second drive PMOS tube, a third drive PMOS tube, a fourth drive PMOS tube, a fifth drive PMOS tube and a sixth drive PMOS tube. When the non-overlapping control P signal is high, the third drive NMOS tube and the fourth drive NMOS tube will pull the protection control E signal down to VCC5-3.3V. When the fifth drive PMOS tube is turned on, the drive control signal outputs VCC5. When the non-overlapping control P signal is low, the fifth drive NMOS tube and the sixth drive NMOS tube will pull the drive control signal down to VCC5-3.3V.

6. The class D power amplifier circuit using low voltage devices to achieve high voltage resistance according to claim 1, characterized in that: The NMOS drive control module includes a plurality of inverters, and the plurality of inverters are used to amplify the drive signal step by step.

7. The class D power amplifier circuit using low voltage devices to achieve high voltage resistance according to claim 1, characterized in that: The PMOS drive control module PA_VDRVP outputs a PMOS drive control signal. When the first PMOS tube is turned on, the output of the PMOS drive control signal is no greater than VCC5-3.3V to protect the gate-source voltage of the first PMOS tube from being greater than 3.3V.

8. The class D power amplifier circuit using low voltage devices to achieve high voltage resistance according to claim 7, characterized in that: The bias voltage buffer module outputs a PMOS protection control signal. When the second PMOS tube is turned on, the output of the PMOS protection control signal is VCC5-3.3V to protect the gate-source voltage of the second PMOS tube PM1 from being greater than 3.6V.

9. The class D power amplifier circuit using low voltage devices to achieve high voltage resistance according to claim 8, characterized in that: The second NMOS tube is connected to a first resistor, a first end of the first resistor is connected to the gate of the second NMOS tube, and the other end of the first resistor is connected to a voltage power supply VCC3 to protect the gate-drain voltage of the first NMOS tube from being greater than 3.3V.

10. A method for controlling a Class D power amplifier with high voltage resistance using low voltage devices, characterized in that: A class D power amplifier circuit that uses low-voltage devices to achieve high-voltage resistance according to any one of claims 1 to 9, comprising: The non-overlapping control module performs delay processing on the PA_DIN signal and outputs a non-overlapping control P signal and a non-overlapping control N signal; The bias voltage generating module generates a bias signal; The bias voltage buffer module converts the bias signal into a driving voltage signal to control the gate of the second NMOS tube, and provides a driving control signal to the PMOS driving control module; The PMOS drive control module performs gate control on the first PMOS tube; The NMOS drive control module PA_VDRVN performs gate control on the first NMOS tube; The gates of the first PMOS tube and the first NMOS tube are controlled so that the gate-to-drain voltage is not greater than the withstand voltage range.

Images