Phase frequency detector with double reset paths

Abstract

The invention provides a phase frequency detector with double reset paths, and the phase frequency detector comprises a trigger circuit which carries out the phase frequency detection of a received reference clock and a feedback clock, outputs an output signal with phase difference information, and controls the level of the output signal according to two paths of first reset signals and two paths of second reset signals; the first reset circuit generates an inverted reference clock and an inverted feedback clock respectively under the action of the reference clock and the feedback clock, and generates the two paths of first reset signals under the action of the output signal; and the second reset circuit generates a first path of second reset signal under the action of the inverted reference clock and the feedback clock, and generates a second path of second reset signal under the action of the reference clock and the inverted feedback clock. According to the phase frequency detector provided by the invention, a phase discrimination dead zone and a phase discrimination blind zone are solved, the phase discrimination range is [-2pi, 2pi], and the performance of a phase-locked loop can be improved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a frequency detector and phase detector with double reset paths used in a phase-locked loop. Background Art

[0002] In communication systems, phase-locked loops are used to generate high-precision clocks or local oscillator signals. Among them, the phase frequency detector (PFD) is the core module of the phase-locked loop. Its main function is to detect the frequency difference and phase difference between the reference clock and the feedback clock output by the divider. The phase detection dead zone and phase detection blind zone of the phase frequency detector determine the frequency capture range, locking time, phase detection accuracy, frequency tracking performance and other indicators of the phase-locked loop. The phase detection dead zone is due to the output signal (UP and DN) with phase difference information output by the phase frequency detector is not enough for the charge pump module in the phase-locked loop to work normally, resulting in the degradation of the frequency tracking performance and phase detection accuracy of the phase-locked loop. The phase detection blind zone is due to the phase frequency detector failing to respond to the rising edge of the clock signal during the reset process, and then outputting an output signal with incorrect phase difference information, resulting in the degradation of the frequency capture range, locking time and other performance of the phase-locked loop.

[0003] As the data transmission rate of communication systems continues to increase, higher performance requirements are placed on phase-locked loops, including wider frequency capture range, faster frequency locking speed, better frequency tracking performance, etc. Therefore, it is particularly important to design high-performance phase frequency detectors. Summary of the invention

[0004] In view of the above problems in the prior art, the present invention proposes a frequency detector with dual reset paths, which mainly solves the problem that the existing frequency detector has a phase detection dead zone and a phase detection blind zone, and is difficult to meet the actual application requirements.

[0005] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0006] The present application provides a frequency detector and phase detector with dual reset paths, comprising: a trigger circuit, which performs frequency detection and phase detection on a received reference clock and a feedback clock, outputs an output signal with phase difference information, and controls the level of the output signal according to two first reset signals and two second reset signals; wherein the phase difference information is used to characterize the phase difference between the reference clock and the feedback clock; a first reset circuit, which generates an inverted reference clock and an inverted feedback clock respectively under the action of the reference clock and the feedback clock, and generates the two first reset signals under the action of the output signal; and a second reset circuit, which generates a first second reset signal under the action of the inverted reference clock and the feedback clock, and generates a second second reset signal under the action of the reference clock and the inverted feedback clock.

[0007] In one embodiment of the present application, the trigger circuit includes two parallel trigger sub-circuits, one of which is connected to the feedback clock and generates a discharge signal under the action of a first reset signal corresponding to the feedback clock and the first-path second reset signal; the other trigger sub-circuit is connected to the reference clock and generates a charging signal under the action of a first reset signal corresponding to the reference clock and the second-path second reset signal, and the discharge signal and the charging signal constitute the output signal.

[0008] In one embodiment of the present application, the trigger subcircuit for generating the discharge signal includes a first NMOS tube, a second NMOS tube, a sixth NMOS tube, a first PMOS tube, and a fourth PMOS tube; the gate of the first NMOS tube is connected to the feedback clock, the drain of the first NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the fourth PMOS tube, the gate of the sixth NMOS tube, and the first second reset signal, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to the source of the sixth NMOS tube and is grounded, the gate of the second NMOS tube is respectively connected to the gate of the first PMOS tube and the first reset signal corresponding to the feedback clock, the source of the first PMOS tube is connected to the source of the fourth PMOS tube and is connected to the power supply voltage, and the drain of the fourth PMOS tube is connected to the drain of the sixth NMOS tube as an output end to output the discharge signal.

[0009] In one embodiment, the trigger subcircuit for generating the charging signal includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, and a third PMOS tube; the gate of the third NMOS tube is connected to the reference clock, the drain of the third NMOS tube is respectively connected to the drain of the second PMOS tube, the gate of the third PMOS tube, the gate of the fifth NMOS tube, and the second second reset signal, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is connected to the source of the fifth NMOS tube and is grounded, the gate of the fourth NMOS tube is respectively connected to the gate of the second PMOS tube and the first reset signal corresponding to the reference clock, the source of the second PMOS tube is connected to the source of the third PMOS tube and is connected to the power supply voltage, and the drain of the third PMOS tube is connected to the drain of the fifth NMOS tube as an output end to output the charging signal.

[0010] In an embodiment of the present application, the first reset circuit includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a first inverter, a second inverter, a first delay device, and a second delay device;

[0011] The gate of the ninth PMOS tube is connected to the feedback clock and the input end of the first inverter respectively, the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube, the source of the ninth PMOS tube is connected to the source of the eleventh PMOS tube and is connected to the power supply voltage, the gate of the tenth PMOS tube, the gate of the seventh NMOS tube, the gate of the twelfth NMOS tube, and the output end of the second delayer are connected to each other; the drain of the tenth PMOS tube is connected to the drain of the seventh NMOS tube to output the first reset signal corresponding to the feedback clock; the source of the seventh NMOS tube is connected to the first reset signal of the seventh NMOS tube respectively; The drain of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, and the gate of the eighth NMOS tube is connected to the output end of the second inverter to access the inverted reference clock; the source of the eighth NMOS tube is respectively connected to the source of the ninth NMOS tube, the source of the eleventh NMOS tube, and the source of the twelfth NMOS tube and is grounded; the gate of the ninth NMOS tube, the output end of the first delay device, the gate of the twelfth PMOS tube, and the gate of the tenth NMOS tube are connected to each other; the output end of the first inverter outputs the inverted feedback clock; the input end of the first delay device is connected to the discharge signal;

[0012] The gate of the eleventh PMOS tube is connected to the reference clock and the input end of the second inverter respectively, the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube, the drain of the twelfth PMOS tube is connected to the drain of the tenth NMOS tube and the first reset signal corresponding to the reference clock, the source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube and the drain of the twelfth NMOS tube respectively, the gate of the eleventh NMOS tube is connected to the inverted feedback clock, the output end of the second inverter is connected to the inverted reference clock, and the input end of the second delay device is connected to the charging signal.

[0013] In one embodiment of the present application, the second reset circuit includes two parallel reset sub-circuits, one of which generates the first second reset signal under the action of the feedback clock and the inverted reference clock; and the other reset sub-circuit generates the second second reset signal under the action of the reference clock and the inverted feedback clock.

[0014] In one embodiment of the present application, the second reset circuit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the fifth PMOS tube and the sixth PMOS tube constitute one reset sub-circuit, and the seventh PMOS tube and the eighth PMOS tube constitute another reset sub-circuit; the gate of the fifth PMOS tube is connected to the inverted reference clock, the drain of the fifth PMOS tube is connected to the first second reset signal, the source of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, the gate of the sixth PMOS tube is connected to the feedback clock, the source of the sixth PMOS tube is connected to the source of the seventh PMOS tube and connected to the power supply voltage, the gate of the seventh PMOS tube is connected to the reference clock, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, the gate of the eighth PMOS tube is connected to the inverted feedback clock, and the drain of the eighth PMOS tube is connected to the second second reset signal.

[0015] In one embodiment of the present application, the first inverter and the second inverter have the same circuit structure, and the first inverter includes a first transistor and a second transistor, wherein the drain of the first transistor is connected to the drain of the second transistor as the output end of the first inverter, the source of the first transistor is connected to the power supply voltage, and the source of the second transistor is grounded; the gate of the first transistor is connected to the gate of the second transistor as the input end of the first inverter, wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0016] In one embodiment of the present application, the first delay device and the second delay device have the same circuit structure, and the first delay device includes: at least two inverters connected in series.

[0017] In an embodiment of the present application, the phase detection range of the frequency and phase detector includes [-2π, 2π].

[0018] As described above, the frequency detector and phase detector with dual reset paths proposed in the present application has the following beneficial effects.

[0019] The present application controls the first reset circuit and the second reset circuit to generate corresponding reset signals according to the phase difference between the reference clock signal and the feedback clock signal, thereby solving the problem of phase detection dead zone in the traditional phase frequency detector and improving the phase detection accuracy and frequency tracking performance of the phase-locked loop; triggering the second reset circuit by the inverted feedback clock and the inverted reference clock, and then directly resetting the output signal, thereby optimizing the phase detection blind zone of the traditional phase frequency detector and expanding the phase detection range, which will reduce the frequency locking time of the phase-locked loop and expand the capture frequency range. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the architecture of a phase frequency detector with dual reset paths in an embodiment of the present application.

[0021] Figure 2 The present invention is a schematic diagram of a circuit structure of a phase frequency detector with dual reset paths in an embodiment of the present application.

[0022] Figure 3 Schematic diagram of the circuit structure of an inverter in one embodiment of the present application.

[0023] Figure 4 Schematic diagram of the circuit structure of a delay device in one embodiment of the present application.

[0024] Figure 5 This is a schematic diagram of the circuit structure of a traditional frequency detector and phase detector.

[0025] Figure 6 The diagram is a schematic diagram of a phase detection characteristic curve of a frequency detector and phase detector with dual reset paths in one embodiment of the present application.

[0026] Description of Figure Numbers:

[0027] N1-first NMOS tube; N2-second NMOS tube; N3-third NMOS tube; N4-fourth NMOS tube; N5-fifth NMOS tube; N6-sixth NMOS tube; N7-seventh NMOS tube; N8-eighth NMOS tube; N9-ninth NMOS tube; N10-tenth NMOS tube; N11-eleventh NMOS tube; N12-twelfth NMOS tube; P1-first PMOS tube; P2-second PMOS tube; P3-third PMOS tube; P4-fourth PMOS tube; P5-fifth PMOS tube; P6-sixth PMOS tube; P7-seventh PMOS tube; P8-eighth PMOS tube; P9-ninth PMOS tube; P10-tenth PMOS tube Tube; P11-eleventh PMOS tube; P12-twelfth PMOS tube; FBCLK-feedback clock; REFCLK-reference clock; FBCLK_N-inverted feedback clock; REFCLK_N-inverted reference clock; INV1-first inverter; INV2-second inverter; TD1-first delay; TD2-second delay; VDD-power supply voltage; GND-ground; DN-discharge signal; UP-charge signal; IP1-first transistor; IN1-second transistor; RST21-first second reset signal; RST22-second second reset signal; RST11-first reset signal corresponding to feedback clock; RST12-first reset signal corresponding to reference clock. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0030] See also Figure 1 , Figure 1 The schematic diagram of the structure of a frequency detector with dual reset paths in an embodiment of the present application. The frequency detector provided in the embodiment of the present application includes: a trigger circuit, which performs frequency detection and phase detection on the received reference clock and feedback clock, outputs an output signal with phase difference information, and controls the level of the output signal according to two first reset signals and two second reset signals; wherein the phase difference information is used to characterize the phase difference between the reference clock REFCLK and the feedback clock FBCLK; a first reset circuit, which generates an inverted reference clock REFCLK_N and an inverted feedback clock FBCLK_N respectively under the action of the reference clock REFCLK and the feedback clock FBCLK, and generates two first reset signals under the action of the output signal; a second reset circuit, which generates a first second reset signal RST21 under the action of the inverted reference clock REFCLK_N and the feedback clock FBCLK, and generates a second second reset signal RST22 under the action of the reference clock REFCLK and the inverted feedback FBCLK_N clock.

[0031] In one embodiment, the trigger circuit is used to perform frequency and phase discrimination on the received reference clock REFCLK and feedback clock FBCLK, and to control the high and low levels of the output signal according to the first reset signal and the second reset signal; the first reset circuit is used to output the first reset signal to the trigger circuit according to the received reference clock REFCLK, the feedback clock FBCLK and the output signal of the trigger circuit, and at the same time output clock signals with opposite phases to the reference clock REFCLK and the feedback clock FBCLK, i.e., the inverted reference clock REFCLK_N and the inverted feedback clock FBCLK_N, respectively, to the second reset circuit; the second reset circuit is used to output the second reset signal to the trigger circuit according to the received reference clock REFCLK, the feedback clock FBCLK and the clock signal output by the first reset circuit; the trigger circuit is connected to the first reset circuit and the second reset circuit through the reference clock REFCLK and the feedback clock FBCLK, the trigger circuit is connected to the first reset circuit through the output signal and the first reset signal, the first reset circuit is connected to the second reset circuit through the clock signal with opposite phase, and the second reset circuit is connected to the trigger circuit through the second reset signal. The trigger circuit, the first reset circuit and the second reset circuit are composed of an N-type metal oxide semiconductor (N Metal Oxide Semiconductor, NMOS) tube and a P-type metal oxide semiconductor (P Metal Oxide Semiconductor, PMOS) tube.

[0032] In one embodiment, the trigger circuit includes two parallel trigger sub-circuits, one of which is connected to the feedback clock FBCLK, and generates a discharge signal DN under the action of the first reset signal RST11 and the first second reset signal RST21 corresponding to the feedback clock; the other trigger sub-circuit is connected to the reference clock REFCLK, and generates a charging signal UP under the action of the first reset signal RST12 and the second second reset signal RST22 corresponding to the reference clock, and the discharge signal DN and the charging signal UP constitute the output signal.

[0033] See also Figure 2 , Figure 2The circuit structure diagram of the frequency detector and phase detector with dual reset paths in one embodiment of the present application is shown in FIG. In one embodiment, the circuit structures of the two parallel trigger sub-circuits are the same. Specifically, the trigger circuit includes: a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, and a fourth PMOS tube P4; the gate of the first NMOS tube N1 is connected to the feedback clock FBCLK, the drain of the first NMOS tube N1 is respectively connected to the drain of the first PMOS tube P1, the gate of the fourth PMOS tube P4, the gate of the sixth NMOS tube N6, and the first second reset signal RST21, the source of the first NMOS tube N1 is connected to the drain of the second NMOS tube N2, the source of the second NMOS tube N2 is respectively connected to the source of the fourth NMOS tube N4, the source of the fifth NMOS tube N5, and the source of the sixth NMOS tube N6 and connected to GND, the gate of the second NMOS tube N2 is respectively connected to the gate of the first PMOS tube P1, the feedback clock FBCLK pair The first PMOS tube P1 is connected to the source of the second PMOS tube P2, the source of the third PMOS tube P3, and the source of the fourth PMOS tube P4 and connected to the power supply voltage VDD, the drain of the fourth PMOS tube P4 is connected to the drain of the sixth NMOS tube N6 and controls the discharge signal DN; the gate of the third NMOS tube N3 is connected to the reference clock REFCLK, the drain of the third NMOS tube N3 is connected to the drain of the second PMOS tube P2, the gate of the third PMOS tube P3, the gate of the fifth NMOS tube N5, and the second reset signal RST22, the source of the third NMOS tube N3 is connected to the drain of the fourth NMOS tube N4, the gate of the fourth NMOS tube N4 is connected to the gate of the second PMOS tube P2 and the first reset signal RST12 corresponding to the reference clock REFCLK, the drain of the fifth NMOS tube N5 is connected to the drain of the third PMOS tube P3 and controls the charging signal UP.

[0034] In one embodiment, the first reset circuit includes a first reset circuit, including a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a first inverter INV1, a second inverter INV2, a first delay device TD1, and a second delay device TD2; the gate of the ninth PMOS tube P9 is respectively connected to the feedback clock FBCLK and the input end of the first inverter INV1, and the drain of the ninth PMOS tube P9 is connected to the feedback clock FBCLK and the input end of the first inverter INV1. The source of the tenth PMOS tube P10 is connected, the source of the ninth PMOS tube P9 is connected to the source of the eleventh PMOS tube P11 and is connected to the power supply voltage VDD, the gate of the tenth PMOS tube P10, the gate of the seventh NMOS tube N7, the gate of the twelfth NMOS tube N12, and the output end of the second delay device TD2 are connected to each other; the drain of the tenth PMOS tube P10 is connected to the drain of the seventh NMOS tube N7 to output the first reset signal RST11 corresponding to the feedback clock; the source of the seventh NMOS tube N7 is respectively connected to the drain of the eighth NMOS tube N8 and the drain of the ninth NMOS tube N9, the gate of the eighth NMOS tube N8 is connected to the second inverter IN The output end of V2 is connected to access the inverted reference clock REFCLK_N; the source of the eighth NMOS tube N8 is respectively connected to the source of the ninth NMOS tube N9, the source of the eleventh NMOS tube N11, and the source of the twelfth NMOS tube N12 and grounded GND, the gate of the ninth NMOS tube N9, the output end of the first delay device TD1, the gate of the twelfth PMOS tube P12, and the gate of the tenth NMOS tube N10 are connected to each other; the output end of the first inverter INV1 outputs the inverted feedback clock FBCLK_N; the input end of the first delay device TD1 is connected to the discharge signal DN; the gate of the eleventh PMOS tube P11 is respectively connected to the reference clock REFCLK, the second The input end of the inverter INV2 is connected, the drain of the eleventh PMOS tube P11 is connected to the source of the twelfth PMOS tube P12, the drain of the twelfth PMOS tube P12 is connected to the drain of the tenth NMOS tube N10 and the first reset signal RST12 corresponding to the reference clock, the source of the tenth NMOS tube N10 is respectively connected to the drain of the eleventh NMOS tube N11 and the drain of the twelfth NMOS tube N12, the gate of the eleventh NMOS tube N11 is connected to the inverted feedback clock FBCLK_N, the output end of the second inverter INV2 is connected to the inverted reference clock REFCLK_N, and the input end of the second delay device TD2 is connected to the charging signal UP.

[0035] In one embodiment, the second reset circuit includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7 and an eighth PMOS transistor P8, wherein the fifth PMOS transistor P5 and the sixth PMOS transistor P6 form one reset sub-circuit, and the seventh PMOS transistor P7 and the eighth PMOS transistor P8 form another reset sub-circuit; the gate of the fifth PMOS transistor P5 is connected to the inverted reference clock REFCLK_N, the drain of the fifth PMOS transistor P5 is connected to the first second reset signal RST21, and the source of the fifth PMOS transistor P5 is connected to the reverse reference clock REFCLK_N. The drain of the sixth PMOS tube P6 is connected, the gate of the sixth PMOS tube P6 is connected to the feedback clock FBCLK, the source of the sixth PMOS tube P6 is connected to the source of the seventh PMOS tube P7 and is connected to the power supply voltage VDD, the gate of the seventh PMOS tube P7 is connected to the reference clock REFCLK, the drain of the seventh PMOS tube P7 is connected to the source of the eighth PMOS tube P8, the gate of the eighth PMOS tube P8 is connected to the inverted feedback clock FBCLK_N, and the drain of the eighth PMOS tube P8 is connected to the second reset signal RST22.

[0036] See also Figure 3 , Figure 3 Schematic diagram of the circuit structure of the inverter in one embodiment of the present application. The circuit structure of the first inverter INV1 is the same as that of the second inverter INV2. The first inverter INV1 includes a first transistor IP1 and a second transistor IN1, wherein the drain of the first transistor IP1 is connected to the drain of the second transistor IN1 as the output end of the first inverter INV1, the source of the first transistor IP1 is connected to the power supply voltage VDD, and the source of the second transistor IN1 is grounded GND; the gate of the first transistor IP1 is connected to the gate of the second transistor IN1 as the input end of the first inverter INV1. Specifically, the first transistor IP1 can be a PMOS transistor, and the second transistor IN1 can be an NMOS transistor. In the second inverter INV2, the drain of the PMOS tube is connected to the drain of the NMOS tube as the output end, the source of the PMOS tube is connected to VDD, the source of the NMOS tube is grounded GND, and the gates of the PMOS tube and the NMOS tube are connected as the input end.

[0037] See also Figure 4 , Figure 4 Schematic diagram of the circuit structure of a delay device in an embodiment of the present application. The first delay device TD1 has the same circuit structure as the second delay device TD2, and the first delay device TD1 includes: at least two inverters connected in series. Figure 4 Only the structure of two inverters (INV3 and INV4) connected in series is used as an example. Multiple inverters can also be used according to the actual delay requirements. The number of inverters constituting the delay device is not limited here. The inverter here is Figure 3 The inverter structure is shown.

[0038] The working principle of the phase frequency detector provided in the embodiment of the present application can be expressed as follows: the phase frequency detector is divided into a trigger circuit, a first reset circuit and a second reset circuit. The trigger circuit captures the rising edge of the reference clock REFCLK and the feedback clock FBCLK and outputs an output signal with phase difference information; the first reset circuit is used in the interval [-π,π] between the phase difference of the reference clock REFCLK and the feedback clock FBCLK, and the pulse width of the output signal (UP and DN) can be increased through the delay device, which solves the phase detection dead zone of the traditional phase frequency detector; the second reset circuit is used in the interval [-2π,-π] and [π,2π] between the phase difference, and the output signal is directly reset by triggering the clock signal, which optimizes the phase detection blind zone of the traditional phase frequency detector and expands the phase detection range to [-2π,2π]. This will reduce the frequency locking time of the phase-locked loop and expand the capture frequency range.

[0039] See also Figure 5 and Figure 6 , Figure 5 It is a schematic diagram of the circuit structure of a traditional frequency and phase detector; Figure 6 FIG. 1 is a schematic diagram of a phase detection characteristic curve of a frequency detector and a phase detector with dual reset paths in an embodiment of the present application. Figure 5 As shown in the figure, the traditional phase frequency detector structure consists of a trigger circuit and a reset circuit. The input D port of the D flip-flop in the trigger circuit is connected to a high level, and the CLK terminal is connected to the reference clock and the feedback clock respectively. The D flip-flop adopts edge triggering. When the outputs of the two D flip-flops are both high, the trigger state is reset through the AND gate and the delay circuit. The problems of this circuit structure are phase detection dead zone and phase detection blind zone, which will significantly affect the loop characteristics such as reference spurious and locking time of the phase-locked loop system. The phase detection dead zone is specifically when the phase difference between the reference clock signal and the feedback clock signal is too small, so that the pulse width of the output signal of the phase frequency detector is very small, and there are parasitic capacitances at each node in the circuit. The pulse signal cannot reach a high level and thus the charge pump cannot work normally, which eventually causes the phase-locked loop to fail to lock. This phase difference is called the phase detection dead zone. The phase detection blind zone is specifically when the reset signal resets the D flip-flop, the D flip-flop cannot recognize the rising edge of the clock, resulting in the loss of the clock edge, so that the phase frequency detector outputs an erroneous phase pulse signal. The phase difference in the above situation is called the phase detection blind zone. The phase range of the frequency detector with blind area is [-2π+T B ,2π-T B ], T B is the phase detection blind area, T B =2πT R / T REF , T R is the reset time of the frequency detector, T REFis the clock period of the reference clock signal. The reset time T of the frequency detector and phase detector in the figure R Expressed as: T R =

[0040] T Q +T A +T DELAY , where T Q is the time required to reset the D flip-flop, T A is the transmission time of the signal through the AND gate, T DELAY The time required for the signal to pass through the delay circuit. A common method to overcome the dead zone is to increase the delay T of the delay circuit. DELAY , so that the pulse signal output by the frequency detector can turn on the switch of the charge pump. R In the expression, time T DELAY Increase, reset time T R The phase blind area of ​​the PFD is increased. Usually, the phase blind area of ​​the frequency detector is first satisfied during design. Figure 6 As shown, in the embodiment of the present application, under the five process angles of the manufacturing process, the phase-locked loop characteristic curve passes through the zero point and the phase-locked loop range is [-2π, 2π], that is, there is no phase-locked loop dead zone and phase-locked loop blind zone, which will improve the performance of the phase-locked loop, including a wider frequency capture range, a faster frequency locking speed, and better frequency tracking performance.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A frequency detector with dual reset paths, characterized in that: include: A trigger circuit, which performs frequency and phase discrimination on the received reference clock and feedback clock, outputs an output signal with phase difference information, and controls the level of the output signal according to two first reset signals and two second reset signals; wherein the phase difference information is used to characterize the phase difference between the reference clock and the feedback clock; A first reset circuit, which generates an inverted reference clock and an inverted feedback clock respectively under the action of the reference clock and the feedback clock, and generates the two first reset signals under the action of the output signal; The second reset circuit generates a first second reset signal under the action of the inverted reference clock and the feedback clock, and generates a second second reset signal under the action of the reference clock and the inverted feedback clock.

2. The phase frequency detector with dual reset paths according to claim 1, characterized in that: The trigger circuit includes two parallel trigger sub-circuits, one of which is connected to the feedback clock and generates a discharge signal under the action of a first reset signal corresponding to the feedback clock and the first-path second reset signal; the other trigger sub-circuit is connected to the reference clock and generates a charge signal under the action of a first reset signal corresponding to the reference clock and the second-path second reset signal, and the discharge signal and the charge signal constitute the output signal.

3. The phase frequency detector with dual reset paths according to claim 2, characterized in that: The trigger subcircuit for generating the discharge signal includes a first NMOS tube, a second NMOS tube, a sixth NMOS tube, a first PMOS tube, and a fourth PMOS tube; The gate of the first NMOS tube is connected to the feedback clock, the drain of the first NMOS tube is respectively connected to the drain of the first PMOS tube, the gate of the fourth PMOS tube, the gate of the sixth NMOS tube, and the first second reset signal, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to the source of the sixth NMOS tube and is grounded, the gate of the second NMOS tube is respectively connected to the gate of the first PMOS tube and the first reset signal corresponding to the feedback clock, the source of the first PMOS tube is connected to the source of the fourth PMOS tube and is connected to the power supply voltage, and the drain of the fourth PMOS tube is connected to the drain of the sixth NMOS tube as an output end to output the discharge signal.

4. The phase frequency detector with dual reset paths according to claim 2, characterized in that: The trigger subcircuit for generating the charging signal includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, and a third PMOS tube; The gate of the third NMOS tube is connected to the reference clock, the drain of the third NMOS tube is respectively connected to the drain of the second PMOS tube, the gate of the third PMOS tube, the gate of the fifth NMOS tube, and the second reset signal of the second path, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is connected to the source of the fifth NMOS tube and is grounded, the gate of the fourth NMOS tube is respectively connected to the gate of the second PMOS tube and the first reset signal corresponding to the reference clock, the source of the second PMOS tube is connected to the source of the third PMOS tube and is connected to the power supply voltage, and the drain of the third PMOS tube is connected to the drain of the fifth NMOS tube as an output end to output the charging signal.

5. The phase frequency detector with dual reset paths according to claim 2, characterized in that: The first reset circuit includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a first inverter, a second inverter, a first delay device and a second delay device; The gate of the ninth PMOS tube is connected to the feedback clock and the input end of the first inverter respectively, the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube, the source of the ninth PMOS tube is connected to the source of the eleventh PMOS tube and connected to the power supply voltage, the gate of the tenth PMOS tube, the gate of the seventh NMOS tube, the gate of the twelfth NMOS tube, and the output end of the second delayer are connected to each other; the drain of the tenth PMOS tube is connected to the drain of the seventh NMOS tube to output the first reset signal corresponding to the feedback clock; the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube and the drain of the ninth NMOS tube respectively, and the gate of the eighth NMOS tube is connected to the output end of the second inverter to access the inverted reference clock; The source of the eighth NMOS tube is respectively connected to the source of the ninth NMOS tube, the source of the eleventh NMOS tube, and the source of the twelfth NMOS tube and is grounded; the gate of the ninth NMOS tube, the output end of the first delay device, the gate of the twelfth PMOS tube, and the gate of the tenth NMOS tube are connected to each other; the output end of the first inverter outputs the inverted feedback clock; the input end of the first delay device is connected to the discharge signal; The gate of the eleventh PMOS tube is connected to the reference clock and the input end of the second inverter respectively, the drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube, the drain of the twelfth PMOS tube is connected to the drain of the tenth NMOS tube and the first reset signal corresponding to the reference clock, the source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube and the drain of the twelfth NMOS tube respectively, the gate of the eleventh NMOS tube is connected to the inverted feedback clock, the output end of the second inverter is connected to the inverted reference clock, and the input end of the second delay device is connected to the charging signal.

6. The phase frequency detector with dual reset paths according to claim 2, characterized in that: The second reset circuit includes two parallel reset sub-circuits, one of which generates the first-path second reset signal under the action of the feedback clock and the inverted reference clock; the other reset sub-circuit generates the second-path second reset signal under the action of the reference clock and the inverted feedback clock.

7. The phase frequency detector with dual reset paths according to claim 6, characterized in that: The second reset circuit comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the fifth PMOS tube and the sixth PMOS tube form one reset sub-circuit, and the seventh PMOS tube and the eighth PMOS tube form another reset sub-circuit; The gate of the fifth PMOS tube is connected to the inverted reference clock, the drain of the fifth PMOS tube is connected to the first second reset signal, the source of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, the gate of the sixth PMOS tube is connected to the feedback clock, the source of the sixth PMOS tube is connected to the source of the seventh PMOS tube and connected to the power supply voltage, the gate of the seventh PMOS tube is connected to the reference clock, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, the gate of the eighth PMOS tube is connected to the inverted feedback clock, and the drain of the eighth PMOS tube is connected to the second second reset signal.

8. The phase frequency detector with dual reset paths according to claim 5, characterized in that: The circuit structure of the first inverter is the same as that of the second inverter. The first inverter includes a first transistor and a second transistor, wherein the drain of the first transistor is connected to the drain of the second transistor as the output end of the first inverter, the source of the first transistor is connected to the power supply voltage, and the source of the second transistor is grounded; the gate of the first transistor is connected to the gate of the second transistor as the input end of the first inverter, wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

9. The phase frequency detector with dual reset paths according to claim 5, characterized in that: The circuit structure of the first delay device is the same as that of the second delay device. The first delay device includes: at least two inverters connected in series.

10. The phase frequency detector with dual reset paths according to claim 1, characterized in that: The phase detection range of the frequency detector includes [-2π, 2π].

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