Comparator and single-slope analog-to-digital converter

Abstract

The embodiment of the invention discloses a comparator and a single-slope analog-to-digital converter, and is characterized in that a first input sampling module is connected between the non-inverting input end of the comparator and a comparison module, and a second input sampling module is connected between the inverting input end of the comparator and the comparison module; after the first input sampling module and the second input sampling module sample the input voltage, the sampled voltage is scaled. When the comparator is applied to the single-slope analog-to-digital converter, the input voltage range of the rail-to-rail analog-to-digital converter can be reduced to a range which can be received by a comparison module, the linearity of the comparator is improved, and the linearity of the single-slope analog-to-digital converter is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to a comparator and a single-slope analog-to-digital converter. Background Art

[0002] The single slope analog-to-digital converter is a common analog-to-digital converter structure, which is widely used in low-speed and low-power fields such as image sensing and temperature detection.

[0003] Linearity is one of the core design specifications of a single-slope ADC. When a larger input voltage range is required for the ADC, linearity often becomes a design difficulty and a bottleneck for conversion accuracy. Summary of the invention

[0004] The present invention provides a comparator and a single-slope analog-to-digital converter, so as to improve the linearity under the premise of ensuring a larger input voltage range of the analog-to-digital converter.

[0005] According to one aspect of the present invention, there is provided a comparator, comprising: a non-inverting input terminal, an inverting input terminal, a first input sampling module, a second input sampling module and a comparison module;

[0006] The input end of the first input sampling module is electrically connected to the in-phase input end, and the output end of the first input sampling module is electrically connected to the first internal input end of the comparison module; the first input sampling module is used to divide the first input voltage of the in-phase input end and output it to the first internal input end;

[0007] The input end of the second input sampling module is electrically connected to the inverting input end, and the output end of the second input sampling module is electrically connected to the second internal input end of the comparison module; the second input sampling module is used to divide the second input voltage of the inverting input end and output it to the second internal input end;

[0008] The comparison module is used for outputting a comparison result according to the voltages of the first internal input terminal and the second internal input terminal.

[0009] Optionally, the first input sampling module includes a first sampling capacitor and a first voltage-dividing capacitor, the first sampling capacitor and the first voltage-dividing capacitor are connected in series between the in-phase input terminal and the first power supply terminal, and a common connection terminal of the first sampling capacitor and the first voltage-dividing capacitor is electrically connected to the first internal input terminal;

[0010] The second input sampling module includes a second sampling capacitor and a second voltage-dividing capacitor, which are connected in series between the inverting input terminal and the first power supply terminal, and a common connection terminal of the second sampling capacitor and the second voltage-dividing capacitor is electrically connected to the second internal input terminal.

[0011] Optionally, a first voltage division ratio corresponding to the first input sampling module is different from a second voltage division ratio corresponding to the second input sampling module;

[0012] Wherein, the first voltage division ratio is equal to the ratio of the first voltage division capacitor to the sum of the first voltage division capacitor and the first sampling capacitor;

[0013] The second voltage division ratio is equal to the ratio of the second voltage division capacitor to the sum of the second voltage division capacitor and the second sampling capacitor.

[0014] Optionally, the capacitance values ​​of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values ​​of the first voltage-dividing capacitor and the second voltage-dividing capacitor are not equal.

[0015] Optionally, the comparison module includes a comparison unit, a limiting unit and an output unit;

[0016] The comparison unit is electrically connected to the first internal input terminal and the second internal input terminal respectively, and is used to output a first intermediate comparison voltage through the internal comparison output terminal according to the voltages of the first internal input terminal and the second internal input terminal;

[0017] The limiting unit is electrically connected to the internal comparison output terminal and the second power supply terminal respectively, and is used to output the second intermediate comparison voltage through the limiting output terminal according to the first intermediate comparison voltage and the voltage of the second power supply terminal, so as to limit the voltage amplitude range of the second intermediate comparison voltage;

[0018] The output unit is electrically connected to the amplitude limiting output terminal, and is used for outputting a corresponding comparison result according to the second intermediate comparison voltage.

[0019] Optionally, the limiting unit includes a first transistor and a first capacitor, the gate of the first transistor is electrically connected to the second power supply terminal, the first electrode of the first transistor is electrically connected to the internal comparison output terminal, and the second electrode of the first transistor is electrically connected to the second power supply terminal;

[0020] The first end of the first capacitor is electrically connected to the first electrode and the limiting output end of the first transistor respectively, and the second end of the first capacitor is electrically connected to the first power supply end respectively;

[0021] The voltage of the first power supply terminal is lower than the voltage of the second power supply terminal.

[0022] According to another aspect of the present invention, a single-slope analog-to-digital converter is provided, comprising the comparator according to any embodiment of the present invention.

[0023] Optionally, the single slope analog-to-digital converter further includes a ramp generator and a reference voltage generating module;

[0024] The output end of the ramp generator is electrically connected to the in-phase input end, and the ramp generator is used to generate a ramp signal; the output end of the reference voltage generating module is electrically connected to the inverting input end, and the reference voltage generating module is used to generate a reference voltage, and the voltage value of the reference voltage is fixed.

[0025] Optionally, the ramp generator includes a counter and a digital-to-analog converter, and the counter is used to generate a step signal according to an input clock signal;

[0026] The digital-to-analog converter is electrically connected to the counter and is used to generate a corresponding ramp signal according to the step signal;

[0027] The comparator is also used to output the comparison result to the counter.

[0028] Optionally, the reference voltage generating module includes a multi-way selection unit, and the multi-way selection unit is used to select one of at least two analog voltages as the reference voltage.

[0029] The comparator and single-slope analog-to-digital converter of the embodiment of the present invention connects a first input sampling module between the in-phase input terminal of the comparator and the comparison module, and connects a second input sampling module between the inverting input terminal of the comparator and the comparison module, so that the first input sampling module and the second input sampling module can implement sampling of the input voltage and then scale the sampled voltage. When the comparator is applied to the single-slope analog-to-digital converter, the input voltage range of the rail-to-rail analog-to-digital converter can be reduced to the range that the comparison module can receive, thereby improving the linearity of the comparator, and further improving the linearity of the single-slope analog-to-digital converter.

[0030] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic structural diagram of a comparator provided by an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of the structure of another comparator provided by an embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of the structure of another comparator provided by an embodiment of the present invention;

[0035] Figure 4 is a structural schematic diagram of a single-slope analog-to-digital converter provided by an embodiment of the present invention;

[0036] Figure 5It is the waveform diagram of the ramp signal and the reference voltage;

[0037] Figure 6 is a schematic structural diagram of another single-slope analog-to-digital converter provided by an embodiment of the present invention;

[0038] Figure 7 It is the voltage waveform of one quantization cycle of a single slope analog-to-digital converter. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] Figure 1 is a schematic diagram of a comparator provided by an embodiment of the present invention, with reference to Figure 1The comparator includes: an in-phase input terminal INP, an inverting input terminal INN, a first input sampling module 110, a second input sampling module 120 and a comparison module 130; the input terminal of the first input sampling module 110 is electrically connected to the in-phase input terminal INP, and the output terminal of the first input sampling module 110 is electrically connected to the first internal input terminal INP-IN of the comparison module 130; the first input sampling module 110 is used to divide the first input voltage of the in-phase input terminal INP and output it to the first internal input terminal INP-IN; the input terminal of the second input sampling module 120 is electrically connected to the inverting input terminal INN, and the output terminal of the second input sampling module 120 is electrically connected to the second internal input terminal INN-IN of the comparison module 130; the second input sampling module 120 is used to divide the second input voltage of the inverting input terminal INN and output it to the second internal input terminal INN-IN; the comparison module 130 is used to output a comparison result according to the voltages of the first internal input terminal INP-IN and the second internal input terminal INN-IN.

[0042] Among them, the first input sampling module 110 can sample the first input voltage of the in-phase input terminal INP, and output it to the first internal input terminal INP-IN of the comparison module 130 after voltage division. The second input sampling module 120 can sample the second input voltage of the inverting input terminal INN, and output it to the second internal input terminal INN-IN of the comparison module 130 after voltage division. The first input sampling module 110 divides the first input voltage so that the voltage input to the first internal input terminal INP-IN of the comparison module 130 is less than the first input voltage; the second input sampling module 120 divides the second input voltage so that the voltage input to the second internal input terminal INN-IN of the comparison module 130 is less than the second input voltage.

[0043] The comparison module 130 can compare the voltages of the first internal input terminal INP-IN and the second internal input terminal INN-IN, and obtain the comparison result and output it through the output terminal OVPOUT of the comparator. Among them, the comparison module 130 can include multiple transistors. In some optional embodiments of the present invention, the comparison module 130 can be implemented by a circuit that implements the comparison function in the prior art. Due to the limitation of transistor characteristics, the acceptable input voltage range of the comparison module 130 is limited. In this embodiment, after the first input voltage is sampled by the first input sampling module 110, the first input voltage is scaled; after the second input voltage is sampled by the second input sampling module 120, the second input voltage is scaled, so that the voltage range actually input to the comparison module 130 is smaller than the voltage range of the external input to the comparator, so that the voltage input to the comparison module 130 is within the range that the transistor can receive. When the comparator is applied to a single-slope analog-to-digital converter, the input voltage range of the rail-to-rail analog-to-digital converter can be reduced to the range that the comparison module 130 can receive, thereby improving the linearity of the comparator and thus improving the linearity of the single-slope analog-to-digital converter.

[0044] The comparator of this embodiment connects a first input sampling module between the in-phase input terminal of the comparator and the comparison module, and connects a second input sampling module between the inverting input terminal of the comparator and the comparison module, so that the first input sampling module and the second input sampling module can sample the input voltage and then scale the sampled voltage. When the comparator is applied to a single-slope analog-to-digital converter, the input voltage range of the rail-to-rail analog-to-digital converter can be reduced to a range that the comparison module can receive, thereby improving the linearity of the comparator and further improving the linearity of the single-slope analog-to-digital converter.

[0045] Figure 2 is a schematic diagram of the structure of another comparator provided by an embodiment of the present invention, referring to Figure 2 Optionally, the first input sampling module 110 includes a first sampling capacitor C1 and a first voltage-dividing capacitor C2, the first sampling capacitor C1 and the first voltage-dividing capacitor C2 are connected in series between the in-phase input terminal INP and the first power supply terminal AVSS, and the common connection terminal of the first sampling capacitor C1 and the first voltage-dividing capacitor C2 is electrically connected to the first internal input terminal INP-IN; the second input sampling module 120 includes a second sampling capacitor C3 and a second voltage-dividing capacitor C4, the second sampling capacitor C3 and the second voltage-dividing capacitor C4 are connected in series between the inverting input terminal INN and the first power supply terminal AVSS, and the common connection terminal of the second sampling capacitor C3 and the second voltage-dividing capacitor C4 is electrically connected to the second internal input terminal INN-IN.

[0046] Among them, the first sampling capacitor C1 is used to sample the first input voltage. Since the first voltage-dividing capacitor C2 divides the voltage with the first sampling capacitor C1, the voltage at the common connection end of the first sampling capacitor C1 and the first voltage-dividing capacitor C2 is less than the first input voltage. By setting the first input sampling module 110 to include the first sampling capacitor C1 and the first voltage-dividing capacitor C2, the first input voltage input to the in-phase input terminal INP can be scaled, so that the voltage input to the comparison module 130 through the first internal input terminal INP-IN is reduced relative to the first input voltage. The second sampling capacitor C3 is used to sample the second input voltage. Since the second voltage-dividing capacitor C4 and the second sampling capacitor C3 divide the voltage, the voltage at the common connection end of the second sampling capacitor C3 and the second voltage-dividing capacitor C4 is less than the second input voltage. By setting the second input sampling module 120 to include the second sampling capacitor C3 and the second voltage-dividing capacitor C4, the second input voltage input to the in-phase input terminal INP can be scaled, so that the voltage input to the comparison module 130 through the second internal input terminal INN-IN is reduced relative to the second input voltage. In this way, a relatively large input voltage range externally input to the comparator can be scaled to a range acceptable to the comparison module 130 .

[0047] On the basis of the above technical solution, optionally, the first voltage division ratio corresponding to the first input sampling module 110 is different from the second voltage division ratio of the second input sampling module 120; wherein the first voltage division ratio is equal to the ratio of the first voltage division capacitor C2 to the sum of the first voltage division capacitor C2 and the first sampling capacitor C1; and the second voltage division ratio is equal to the ratio of the second voltage division capacitor C4 to the sum of the second voltage division capacitor C4 and the second sampling capacitor C3.

[0048] Specifically, when the comparator is applied to a single-slope analog-to-digital converter, one of the comparator's in-phase input terminal INP and inverting input terminal INN is connected to a ramp signal, and the other is connected to a fixed voltage. By setting the first voltage division ratio corresponding to the first input sampling module 110 to be different from the voltage division ratio corresponding to the second input sampling module 120, that is, the comparator's in-phase input terminal INP and inverting input terminal INN use asymmetric capacitor voltage division, so that the first input sampling module 110 and the second input sampling module 120 can achieve different scaling factors, so that when the comparison module 130 makes a comparison, only the middle part with the best linearity in the full-swing ramp signal is used, thereby further improving the linearity and avoiding the influence of the linearity difference between the two end parts of the ramp signal on the linearity of the analog-to-digital converter.

[0049] In some optional embodiments of the present invention, the capacitance values ​​of the first sampling capacitor C1 and the second sampling capacitor C3 are equal, and the capacitance values ​​of the first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C4 are not equal.

[0050] The first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C4 may each include at least one fixed capacitor. Figure 2 Schematically shows a situation where the first voltage-dividing capacitor C2 includes a fixed capacitor and the second voltage-dividing capacitor C4 includes two parallel fixed capacitors, wherein the capacitance value of the fixed capacitor of the first voltage-dividing capacitor C2 and each fixed capacitor of the second voltage-dividing capacitor C4 may be equal.

[0051] Figure 3 is a schematic diagram of the structure of another comparator provided by an embodiment of the present invention, referring to Figure 3 Optionally, the comparison module includes a comparison unit 131, a limiting unit 132 and an output unit 133; the comparison unit 131 is electrically connected to the first internal input terminal INP-IN and the second internal input terminal INN-IN respectively, and is used to output a first intermediate comparison voltage through the internal comparison output terminal OUT1 according to the voltage of the first internal input terminal INP-IN and the second internal input terminal INN-IN; the limiting unit 132 is electrically connected to the internal comparison output terminal OUT1 and the second power supply terminal AVDD respectively, and is used to output a second intermediate comparison voltage through the limiting output terminal OUT2 according to the voltage of the first intermediate comparison voltage and the second power supply terminal AVDD, so as to limit the voltage amplitude range of the second intermediate comparison voltage; the output unit 133 is electrically connected to the limiting output terminal OUT2, and is used to output a corresponding comparison result according to the second intermediate comparison voltage.

[0052] The comparison unit 131 can realize the comparison function of the voltage of the first internal input terminal INP-IN and the voltage of the second internal input terminal INN-IN. The comparison unit 131 can be realized by using a circuit with a comparison function in the prior art. Figure 3 The structure that the comparison unit 131 includes a cascode amplifier is exemplarily shown. The comparison unit 131 outputs a first intermediate comparison voltage through the internal comparison output terminal OUT1 according to the voltages of the first internal input terminal INP-IN and the second internal input terminal INN-IN. Exemplarily, when the voltage of the first internal input terminal INP-IN is greater than the voltage of the second internal input terminal INN-IN, the first intermediate comparison voltage output by the internal comparison output terminal OUT1 of the comparison unit 131 is a high level voltage; when the voltage of the first internal input terminal INP-IN is less than the voltage of the second internal input terminal INN-IN, the first intermediate comparison voltage output by the internal comparison output terminal OUT1 of the comparison unit 131 is a low level voltage.

[0053] Specifically, since the output amplitude of the existing comparator is affected by the input signal, different input signals will cause different output amplitudes. When the difference in the input signal is large, the difference in the output signal will also be large, so that the delay of the comparator is related to the input signal. In a single-slope analog-to-digital converter, the output result of the comparator will be fed back to the counter. Under different input signals, the difference in the output delay of the comparator will deteriorate the linearity of the single-slope analog-to-digital converter. In this embodiment, by setting the limiting unit 132 to be connected to the internal comparison output terminal OUT1 of the comparison unit 131, the limiting unit 132 can limit the amplitude of the second intermediate comparison voltage, reduce the nonlinearity caused by the difference in the output amplitude of the comparator, further improve the linearity of the comparator, and then improve the linearity of the single-slope analog-to-digital converter.

[0054] The comparator further includes an output unit 133, which is electrically connected to the limit output terminal OUT2 of the limit unit 132 and can output a comparison result according to the second intermediate comparison voltage. Optionally, the output unit 133 can include a two-stage inverter.

[0055] On the basis of the above technical solution, optionally, the limiting unit 132 includes a first transistor T1 and a first capacitor C1, the gate of the first transistor T1 is electrically connected to the second power supply terminal AVDD, the first electrode of the first transistor T1 is electrically connected to the internal comparison output terminal OUT1, and the second electrode of the first transistor T1 is electrically connected to the second power supply terminal AVDD; the first end of the first capacitor C1 is electrically connected to the first electrode of the first transistor T1 and the limiting output terminal OUT2, respectively, and the second end of the first capacitor C1 is electrically connected to the first power supply terminal AVSS, respectively; the voltage of the first power supply terminal AVSS is less than the voltage of the second power supply terminal AVDD.

[0056] Optionally, the first transistor T1 is an NMOS, the first pole is the source, and the second pole is the drain. When the first intermediate comparison voltage output by the comparison unit 131 is a high level voltage, the first transistor T1 is turned off. When the first intermediate comparison voltage output by the comparison unit 131 is a low level voltage, the first transistor T1 is turned on, so that the source voltage of the first transistor T1 is pulled up to the difference between the voltage of the second power supply terminal AVDD and the threshold voltage of the first transistor T1. In this way, the amplitude of the second intermediate comparison voltage can be limited to the threshold voltage of the NMOS tube, reducing the nonlinearity caused by the output amplitude difference, and further improving the linearity of the comparator and the single slope analog-to-digital converter. The first capacitor C1 can make the second intermediate comparison voltage output by the limiting output terminal OUT2 of the limiting unit 132 smoother.

[0057] The embodiment of the present invention further provides a single slope analog-to-digital converter, Figure 4 is a schematic diagram of the structure of a single slope analog-to-digital converter provided by an embodiment of the present invention, with reference to Figure 4The single-slope analog-to-digital converter includes the comparator 100 of any of the above embodiments of the present invention, and has the beneficial effects of the single-slope analog-to-digital converter of any of the above embodiments of the present invention.

[0058] Continue to refer Figure 4 Optionally, the single slope analog-to-digital converter also includes a ramp generator 200 and a reference voltage generating module 300; the output end of the ramp generator 200 is electrically connected to the in-phase input terminal INP, and the ramp generator 200 is used to generate a ramp signal; the output end of the reference voltage generating module 300 is electrically connected to the inverting input terminal INN, and the reference voltage generating module 300 is used to generate a reference voltage, and the voltage value of the reference voltage is fixed.

[0059] Specifically, the ramp generator 200 generates a ramp signal and outputs it to the in-phase input terminal INP of the comparator through the output terminal. The reference voltage generating module 300 generates a fixed reference voltage and outputs it to the inverting input terminal INN of the comparator. The comparator compares the voltage of the ramp signal at the in-phase input terminal INP with the reference voltage at the inverting input terminal INN and outputs the comparison result. Figure 5 is the waveform diagram of the ramp signal and the reference voltage, refer to Figure 5 , in the initial stage, the voltage of the ramp signal 10 is less than the reference voltage 20, and the comparator will output a low level signal. The voltage of the ramp signal 10 gradually increases with time. At t0, the voltage of the ramp signal 10 is equal to the reference voltage 20. At t0, the voltage of the ramp signal 10 is greater than the reference voltage 20, and the output of the comparator flips. Among them, the ramp signal 10 includes a head end portion 101, a tail end portion 102 and a middle portion 103. The middle portion 103 is between the head end portion 101 and the tail end portion 102, and the middle portion 103 has better linearity than the head end portion 101 and the tail end portion 102. Since the comparator's in-phase input terminal INP and the inverting input terminal INN use asymmetric capacitors, different scaling multiples are achieved. Only the middle portion 103 with the best linearity in the full-swing ramp signal is used for comparison with the reference voltage 20, and the head end portion 101 and the tail end portion 102 are discarded, which can improve the linearity.

[0060] Figure 6 is a schematic diagram of the structure of another single slope analog-to-digital converter provided by an embodiment of the present invention, with reference to Figure 6 Optionally, the ramp generator 200 includes a counter 210 and a digital-to-analog converter 220, the counter 210 is used to generate a step signal according to the input clock signal; the digital-to-analog converter 220 is electrically connected to the counter 210, and is used to generate a corresponding ramp signal according to the step signal; the comparator 100 is also used to output the comparison result to the counter 210.

[0061] Specifically, as the clock period of the clock signal increases, the counter 210 can output a step signal corresponding to the clock period in a counting state, and the analog-to-digital converter 220 processes the step signal to generate a ramp signal and output it to the comparator 100 .

[0062] Continue to refer Figure 6 Optionally, the reference voltage generation module 300 includes a multi-way selection unit, which is used to select one of at least two analog voltages as the reference voltage. The multi-way selection unit may include a multi-way selection switch. Selecting one of at least two analog voltages as the reference voltage by the multi-way selection unit is conducive to increasing the input range of the analog voltage. Figure 6 Three analog inputs are schematically output, namely analog input 1, analog input 2 and analog input 3. The reference voltage generating module 300 selects the voltage of one analog input from the three analog inputs as the reference voltage output.

[0063] Optionally, the counter 210 may be a multi-state digital counter 210 . Figure 7 This is the voltage waveform of a quantization cycle of a single slope analog-to-digital converter. Figure 3-Figure 7 The working process of the single slope analog-to-digital converter includes three stages, namely, sampling stage t1, conversion stage t2 and quantization stage t3. Among them, the voltage waveform corresponding to the in-phase input terminal INP is the first curve INPV; the voltage waveform corresponding to the inverting input terminal INN is the second curve INNV; the voltage waveform corresponding to the first internal input terminal INP-IN is the third curve INP-INV; the voltage waveform corresponding to the second internal input terminal INN-IN is the fourth curve INN-INV; the voltage waveform corresponding to the output terminal of the comparator is the fifth curve OVPOUTV; the output waveform of the single slope analog-to-digital converter is the sixth curve ADCOUT.

[0064] In the sampling stage t1, the count value of the multi-state digital counter 210 is set to be unchanged, that is, the count value of the multi-state digital counter 210 will not increase with the increase of the cycle of the clock signal, and accordingly, the digital-to-analog converter 220 outputs a fixed voltage according to the unchanged count value, and accordingly, the voltage input to the non-inverting input terminal INP of the comparator 100 is a fixed voltage. The reference voltage generation module 300 selects an analog voltage through a multi-way selection unit and inputs it to the inverting input terminal INN of the comparator 100 for sampling. In the sampling stage t1, the first control signal AZ is a conduction control signal, and the second transistor T2 and the third transistor T3 in the comparator 100 are turned on, so that the voltages of the first internal input terminal INP-IN and the second internal input terminal INN-IN are equal.

[0065] In the conversion phase t2, the count value of the multi-state digital counter 210 is reset to zero, the output voltage of the digital-to-analog converter 220 is also reset to zero, and the first input voltage of the in-phase input terminal INP of the comparator 100 is 0. The first control signal AZ is a shutdown control signal, and the second transistor T2 and the third transistor T3 in the comparator 100 are turned off. The first input sampling module 110 inside the comparator 100 divides the first input voltage of the in-phase input terminal INP through the first sampling capacitor C1 and the first voltage-dividing capacitor C2, and the second input sampling module 120 divides the second input voltage of the in-phase input terminal INP through the second sampling capacitor C3 and the second voltage-dividing capacitor C4, and scales the voltage to a range acceptable to the comparison module 130. That is, the voltages of the first internal input terminal INP-IN and the second internal input terminal INN-IN can be scaled to a range acceptable to the comparison module 130. At the same time, since asymmetric voltage-dividing capacitors are used at both ends of the input differential pair of the comparator 100 , the voltage scaling capabilities are different, resulting in that only the middle part of the ramp signal with the best linearity is utilized.

[0066] Quantization stage t3, at this time, the multi-state digital counter 210 starts counting from zero, and the output end of the digital-to-analog converter 220 forms a gentle ramp signal. When the ramp signal crosses the analog input signal to be quantized, the comparator 100 flips. Since the output end of the comparison unit uses the first transistor T1 and the first capacitor C1 for limiting, the delay difference of the comparator 100 caused by different inputs is avoided. The output of the comparator 100 is fed back to the multi-state digital counter 210. At this time, the counting result of the digital counter 210 is the quantization result of the single slope analog-to-digital converter.

[0067] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0068] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A comparator, characterized in that: include: A non-inverting input terminal, an inverting input terminal, a first input sampling module, a second input sampling module and a comparison module; The input end of the first input sampling module is electrically connected to the in-phase input end, and the output end of the first input sampling module is electrically connected to the first internal input end of the comparison module; the first input sampling module is used to divide the first input voltage of the in-phase input end and output it to the first internal input end; The input end of the second input sampling module is electrically connected to the inverting input end, and the output end of the second input sampling module is electrically connected to the second internal input end of the comparison module; the second input sampling module is used to divide the second input voltage of the inverting input end and output it to the second internal input end; The comparison module is used for outputting a comparison result according to the voltages of the first internal input terminal and the second internal input terminal.

2. The comparator according to claim 1, characterized in that: The first input sampling module includes a first sampling capacitor and a first voltage-dividing capacitor, the first sampling capacitor and the first voltage-dividing capacitor are connected in series between the in-phase input terminal and the first power supply terminal, and the common connection terminal of the first sampling capacitor and the first voltage-dividing capacitor is electrically connected to the first internal input terminal; The second input sampling module includes a second sampling capacitor and a second voltage-dividing capacitor, the second sampling capacitor and the second voltage-dividing capacitor are connected in series between the inverting input terminal and the first power supply terminal, and a common connection terminal of the second sampling capacitor and the second voltage-dividing capacitor is electrically connected to the second internal input terminal.

3. The comparator according to claim 2, characterized in that A first voltage division ratio corresponding to the first input sampling module is different from a second voltage division ratio corresponding to the second input sampling module; Wherein, the first voltage division ratio is equal to the ratio of the first voltage division capacitor to the sum of the first voltage division capacitor and the first sampling capacitor; The second voltage division ratio is equal to a ratio of the second voltage division capacitor to a sum of the second voltage division capacitor and the second sampling capacitor.

4. The comparator according to claim 2, characterized in that: The capacitance values ​​of the first sampling capacitor and the second sampling capacitor are equal, and the capacitance values ​​of the first voltage-dividing capacitor and the second voltage-dividing capacitor are not equal.

5. The comparator according to any one of claims 1 to 4, characterized in that: The comparison module includes a comparison unit, a limit unit and an output unit; The comparison unit is electrically connected to the first internal input terminal and the second internal input terminal respectively, and is used to output a first intermediate comparison voltage through an internal comparison output terminal according to the voltages of the first internal input terminal and the second internal input terminal; The limiting unit is electrically connected to the internal comparison output terminal and the second power supply terminal respectively, and is used to output the second intermediate comparison voltage through the limiting output terminal according to the first intermediate comparison voltage and the voltage of the second power supply terminal, so as to limit the voltage amplitude range of the second intermediate comparison voltage; The output unit is electrically connected to the limiting output terminal, and is used for outputting a corresponding comparison result according to the second intermediate comparison voltage.

6. The comparator according to claim 5, characterized in that: The amplitude limiting unit includes a first transistor and a first capacitor, the gate of the first transistor is electrically connected to the second power supply terminal, the first electrode of the first transistor is electrically connected to the internal comparison output terminal, and the second electrode of the first transistor is electrically connected to the second power supply terminal; The first end of the first capacitor is electrically connected to the first electrode of the first transistor and the limiting output end respectively, and the second end of the first capacitor is electrically connected to the first power supply end respectively; The voltage of the first power supply terminal is lower than the voltage of the second power supply terminal.

7. A single slope analog-to-digital converter, characterized in that: The comparator comprises the comparator as claimed in any one of claims 1 to 6.

8. The single slope analog-to-digital converter according to claim 7, characterized in that: Also included are a ramp generator and a reference voltage generation module; The output end of the ramp generator is electrically connected to the in-phase input end, and the ramp generator is used to generate a ramp signal; the output end of the reference voltage generating module is electrically connected to the inverting input end, and the reference voltage generating module is used to generate a reference voltage, and the voltage value of the reference voltage is fixed.

9. The single slope analog-to-digital converter according to claim 8, characterized in that: The ramp generator includes a counter and a digital-to-analog converter, wherein the counter is used to generate a step signal according to an input clock signal; The digital-to-analog converter is electrically connected to the counter, and is used to generate a corresponding ramp signal according to the step signal; The comparator is further configured to output the comparison result to the counter.

10. The single slope analog-to-digital converter according to claim 8, characterized in that: The reference voltage generating module comprises a multi-way selection unit, and the multi-way selection unit is used to select one of at least two analog voltages as the reference voltage.

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