Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a glass layer having a first region having a first transmittance and a second region having a second transmittance different from the first transmittance; and a first wiring layer disposed on the glass layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0115182 filed on August 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Multi-chip packages including memory chips such as high bandwidth memory (HBM), processor chips such as central processing units (CPUs), graphic processing units (GPUs), and logic chips such as application-specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs) have been used to process data that has grown exponentially due to recent developments in artificial intelligence (AI) technology. Therefore, attempts have been made to use glass materials. However, the transparency of glass materials has caused problems during processes and / or inspections using light. Summary of the invention

[0004] One aspect of the present disclosure provides a printed circuit board including a glass layer.

[0005] Another aspect of the present disclosure provides a printed circuit board in which no error occurs even when a process and / or inspection using light is performed.

[0006] Another aspect of the present disclosure provides a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, a printed circuit board is provided, comprising: a glass layer having a first area and a second area, the first area having a first transmittance, the second area having a second transmittance different from the first transmittance; and a first wiring layer disposed on the glass layer.

[0008] According to another aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board comprising: a glass layer having a first region located in a central portion and a second region located in at least one of an upper side and a lower side relative to a stacking direction of the printed circuit board; and a first wiring layer disposed on the glass layer. The transmittance of the second region may be lower than the transmittance of the first region.

[0009] According to example embodiments of the present disclosure, there may be provided a printed circuit board including a glass layer.

[0010] According to example embodiments of the present disclosure, a printed circuit board in which no error occurs even when a process and / or inspection using light is performed may be provided.

[0011] According to example embodiments of the present disclosure, a printed circuit board having improved reliability may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0014] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0015] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board;

[0016] Figure 4 is a schematic cross-sectional view showing another example of a printed circuit board;

[0017] FIG. 5A to FIG. 5I is a schematic cross-sectional view illustrating an example of a method of manufacturing a printed circuit board according to an example; and

[0018] FIG. 6A to FIG. 6I is a schematic cross-sectional view illustrating an example of a method of manufacturing a printed circuit board according to another example. DETAILED DESCRIPTION

[0019] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0020] Electronic Devices

[0021] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0022] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. Such components may be connected to other electronic components to be described below via various signal lines 1090.

[0023] The chip-related components 1020 may include: memory chips (such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory)); application processor chips (such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, or microcontrollers); and logic chips (such as analog-to-digital converters or application-specific integrated circuits (ASICs)). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0024] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Wireless local area network (wireless LAN), third generation mobile communication technology (3G) protocol, fourth generation mobile communication technology (4G) protocol and fifth generation mobile communication technology (5G) protocol and any other wireless protocol and wired protocol specified after the above protocol. However, the network-related component 1030 is not limited to this, and may also include components compatible with various other wireless standards or protocols or wired standards or protocols or components that communicate according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020.

[0025] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0026] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0027] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0028] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0029] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component surface including active components and / or passive components is mounted. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0030] Printed Circuit Board

[0031] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board.

[0032] Reference Figure 3According to an example, a printed circuit board may include: a glass layer 100 having a first region 101 and a second region 102, the first region 101 having a first transmittance, and the second region 102 having a second transmittance different from the first transmittance; a first-first wiring layer 121-1 disposed on the upper surface of the glass layer 100; a first-first insulating layer 111-1 disposed on the upper surface of the glass layer 100 to cover the first-first wiring layer 121-1; a first-second wiring layer 121-2 disposed on the lower surface of the glass layer 100; and a first-second insulating layer 111-2 disposed on the lower surface of the glass layer 100 to cover the first-second wiring layer 121-2. In addition, the first region 101 may be spaced apart from the first-first wiring layer 121-1 and the first-second wiring layer 121-2.

[0033] The printed circuit board including the glass layer 100 according to the example may basically have excellent flatness, and may also have a low coefficient of thermal expansion (CTE), which may be advantageous in terms of warpage control. In particular, the printed circuit board according to the example may include the glass layer 100 as a core layer, so that warpage control may be advantageous even in the operation of stacking other insulating layers. In addition, even when the first-first insulating layer 111-1 and the second insulating layer 112 are sequentially stacked on the glass layer 100 and the first-second insulating layer 111-2 and the second insulating layer 112 are sequentially stacked on the glass layer 100, flatness may be further improved. Therefore, it may be more advantageous to form a high-density fine circuit with a fine pitch. In addition, the dielectric properties of the glass layer 100 (such as glass having a variable dielectric property with a dielectric constant (Dk) of 2.5 to 11) may reduce the number of layers of the printed circuit board and further increase the degree of freedom in design.

[0034] The printed circuit board according to the example may cause the glass layer 100 to include the first region 101 and the second region 102 having different transmittances, so that light from the upper side or the lower side of the glass layer 100 may not be transmitted through the glass layer 100. Specifically, with respect to the stacking direction along which the first-first insulating layer 111-1, the glass layer 100, and the first-second insulating layer 111-2 of the printed circuit board are stacked, the inside (central portion) of the glass layer 100 may be the first region 101, the upper side and the lower side of the glass layer 100 may be the second region 102, and the second transmittance of the second region 102 may be lower than the first transmittance of the first region 101. This may be a result of processing the upper side and the lower side of the glass layer 100 having only the first region 101 to form the second region 102 on each of the upper side and the lower side of the glass layer 100. The second region 102 may have a microstructure different from that of the first region 101, and the first region 101 and the second region 102 may have different transmittances caused by the difference between the microstructures.

[0035] exist Figure 3 , the second region 102 is shown as being formed with a regular boundary, but the present disclosure is not limited thereto. Depending on the degree of processing, the boundary may be irregular, for example, it may be uneven. In addition, the boundary of the second region 102 may be clear or unclear. The microstructure may be observed by photographing the cut section of the printed circuit board with a scanning microscope, and the region having a structure different from that of the adjacent region may be distinguished and identified. The first region 101 and the second region 102 may be distinguished from each other by their different transmittances. The second region 102 may have a transmittance lower than that of the first region 101, and may correspond to a region where light may not pass through. That is, a region having a transmittance of a specific value or less than a specific value may be referred to as the second region 102. In this case, the second transmittance of the second region 102 may preferably be 30% or less, but the present disclosure is not necessarily limited thereto. The first region 101 and the second region 102 may be distinguished from each other by a second transmittance being less than or equal to a specific percentage (e.g., 30%) of the first transmittance.

[0036] The glass layer 100 may be divided into a first area 101 and a second area 102, and the second area 102 may not transmit light, so that the influence on the wiring layer on the opposite side during automatic optical inspection (AOI) is small. When the glass layer 100 has only the first area 101, light may be transmitted through the glass layer 100. Therefore, when the light for AOI is irradiated from the upper side of the glass layer 100, the wiring layer disposed on the lower side of the glass layer 100 may be identified, so that an error is very likely to occur. That is, when AOI is performed on the upper side of the glass layer 100, it may be reasonable to only check the first-first wiring layer 121-1 disposed on the upper surface of the glass layer 100. However, the glass layer 100 may transmit light, so the first-second wiring layer 121-2 disposed on the lower surface of the glass layer 100 may be identified and may be identified as a defect. That is, when the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are formed on different surfaces, the following error may occur: the wiring layer on the lower surface is detected in the AOI performed on the upper side. When AOI is performed on the lower side, the same error may also occur. AOI is provided only as an example. When performing an inspection and / or process using light, an error may occur when the glass layer 100 has only the first area 101. For example, when forming an alignment mark to align a line pattern, the upper mark and the lower mark may be mistaken for each other, and since the glass layer 100 is transparent, various errors may occur. The printed circuit board according to the example may not be affected by such an error because the glass layer 100 has the second area 102, and the second area 102 does not transmit light or has a low transmittance. Even when the first-first insulating layer 111-1 or the first-second insulating layer 111-2 provided on the glass layer 100 is transparent, the same effect can be obtained.

[0037] The glass layer 100 may include glass (an amorphous solid). The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, the present disclosure is not limited thereto, and optional glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as the material of the glass layer 100. In addition, other additives may be further included to form glass with specific physical properties. Such additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates of such elements and other elements (e.g., calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda)), and / or magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and oxides of such elements and other elements, but the present disclosure is not limited thereto. The glass layer 100 may be understood as a material layer including glass fibers (such as glass fabrics exemplified by glass cloth) and different from material layers such as copper clad laminates (CCLs), prepregs (PPGs), etc., for example, plate glass. The glass layer 100 may be a plate glass supported by a support such as another core.

[0038] The second region 102 of the glass layer 100 may be disposed on each of the upper and lower surfaces of the glass layer 100, and may extend toward the inside of the glass layer 100. Such a configuration may be the result of performing processing on the upper and lower sides of the glass layer 100. Specifically, by irradiating the laser from the upper and lower sides of the glass layer 100, the second region 102 may be formed along the regions of the upper and lower surfaces of the glass layer 100 where the through-vias 130 are not formed. An ultrafast laser may be used as the laser, but the present disclosure is not necessarily limited thereto. The shorter the irradiation period of the laser, the more the modification of the microstructure may occur. For example, for the modification of the microstructure of the glass layer 100, a picosecond laser may be more preferred than a nanosecond laser, and a femtosecond laser may be more preferred than a picosecond laser. In this case, it may be preferred to use a bar laser rather than a spot laser to modify the microstructure over a large area. When a bar laser is used, the second region 102 may be formed relatively uniformly, and the boundary between the first region 101 and the second region 102 may be formed relatively uniformly. However, the method of processing the second region 102 of the glass layer 100 is not necessarily limited to the above method, and may include a method of injecting different materials (e.g., impurities) into the upper and lower sides of the glass layer 100 to modify the microstructure, and a method of forming the second region 102 by physically or chemically modifying the microstructure using other methods. That is, any method of modifying the microstructure of the glass layer 100 in the art may be used without limitation.

[0039] exist Figure 3, the second region 102 is illustrated as being formed on the upper and lower surfaces of the glass layer 100 and extending toward the inside of the glass layer 100, but the present disclosure is not necessarily limited thereto, and the second region 102 may be formed on one of the upper and lower surfaces of the glass layer 100. Even when the second region 102 is formed on one of the upper and lower surfaces of the glass layer 100, it is feasible when light from the upper side does not reach the lower side or light from the lower side does not reach the upper side.

[0040] The thickness of the first region 101 of the glass layer 100 may be greater than the thickness of the second region 102. The thickness of the first region 101 and the thickness of the second region 102 may be measured by photographing a cut section of the printed circuit board with a scanning microscope, and the thickness may be the average value of the thickness measured at any five points. The boundary between the second region 102 and the first region 101 may be uneven and may be rough. Therefore, the interface between the first region 101 and the second region 102 may be set using a method for measuring roughness, without being limited to the above method. That is, according to the method for measuring the centerline average roughness (Ra), the average position of the boundary between the first region 101 and the second region 102 may be measured to measure the thickness of the first region 101 and the thickness of the second region 102. Alternatively, according to the measurement method of the 10-point average roughness (Rz), the boundary of the first region 101 and the second region 102 may be set based on the deviation between the five highest points and the five lowest points relative to the average position to measure each of the thickness of the first region 101 and the thickness of the second region 102. The second region 102 can be formed by processing the glass layer 100 having the first region 101 and modifying the microstructure of the glass layer 100, so the second region 102 can correspond to a region penetrated by a processing means (such as a laser). Therefore, the thickness of the second region 102 can be less than that of the first region 101.

[0041] The glass layer 100 of the printed circuit board according to the example may include colored glass. The glass layer 100 may be processed to have a color by injecting impurities, and then the colored glass layer 100 may be used to manufacture the printed circuit board, but the present disclosure is not limited thereto. When the glass layer 100 is colored and a process and / or inspection using light is performed on the upper side, polarization may be used to control errors that may occur on the lower side. The glass layer 100 having a color may mean that both the first region 101 and the second region 102 of the glass layer 100 have a color, but the present disclosure is not limited thereto, and may mean that the glass layer 100 is processed so that only the second region 102 of the glass layer 100 has a color.

[0042] The first-first insulating layer 111-1 and the first-second insulating layer 111-2 may be disposed on the upper surface and the lower surface of the glass layer 100, respectively, and the second insulating layer 112 may be disposed on the first-first insulating layer 111-1 and the first-second insulating layer 111-2 to cover the first-first insulating layer 111-1 and the first-second insulating layer 111-2, respectively. The first-first insulating layer 111-1, the first-second insulating layer 111-2, and the second insulating layer 112 may include insulating materials (e.g., organic insulating materials), respectively. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as glass fabric, for example, glass cloth) in a thermosetting resin and / or a thermoplastic resin. For example, the insulating material may be a non-photosensitive insulating material such as Ajinomoto deposited film (ABF) or PPG, but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the insulating material may include an adhesive sheet such as a bonding sheet (BS).

[0043] The first-first insulating layer 111-1 and the first-second insulating layer 111-2 may include the same insulating material, and the second insulating layer 112 may also include the same insulating material. Specifically, the first-first insulating layer 111-1, the first-second insulating layer 111-2, and the second insulating layer 112 may preferably include ABF, but the present disclosure is not limited thereto, and may include other organic insulating materials. In addition, the present disclosure is not limited thereto, and the first-first insulating layer 111-1, the first-second insulating layer 111-2, and the second insulating layer 112 may include different materials. Since the first-first insulating layer 111-1 and the first-second insulating layer 111-2 are respectively disposed on the upper surface and the lower surface of the glass layer 100, at least a portion of the second region 102 of the glass layer 100 may be in contact with the first-first insulating layer 111-1 and / or the first-second insulating layer 111-2.

[0044] The first-first wiring layer 121-1, the first-second wiring layer 121-2, and the second wiring layer 122 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. Each wiring layer may perform various functions according to the design. For example, each wiring layer may include a signal pattern, a power pattern, a ground pattern, etc. The pattern may have various forms, such as lines, surfaces, and pads. Each of the first-first wiring layer 121-1, the first-second wiring layer 121-2, and the second wiring layer 122 may include a first metal layer 141 and a second metal layer 142 disposed on the first metal layer 141. The first metal layer 141 may include an electroless plating layer (e.g., a chemical copper plating layer) or a sputtering layer, or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer as required. The second metal layer 142 may be formed using the first metal layer 141 as a seed layer and using electrolytic plating (eg, electrolytic copper plating), and may also be formed using a metal foil (eg, copper foil).

[0045] At least a portion of the first-first wiring layer 121-1 and at least a portion of the first-second wiring layer 121-2 may be arranged to be misaligned with respect to the glass layer 100. The first-first wiring layer 121-1 and the first-second wiring layer 121-2 being arranged to be misaligned with each other may mean that a region of the upper surface of the glass layer 100 where the first-first wiring layer 121-1 is formed and a region of the lower surface of the glass layer 100 where the first-second wiring layer 121-2 is formed do not correspond to each other or are asymmetric to each other. That is, as Figure 3 As shown by the arrows, relative to the cross-sectional view of the printed circuit board, there may be an area on the upper surface of the glass layer 100 where the first-first wiring layer 121-1 is not formed, and there may be an area on the lower surface of the glass layer 100 where the first-second wiring layer 121-2 is formed corresponding to the above area, and vice versa.

[0046] When the glass layer 100 does not have the second region 102, during a process and / or inspection using light performed on the upper side of the glass layer 100, an error may occur due to the first-second wiring layer 121-2 formed on the lower surface of the glass layer 100 instead of the first-first wiring layer 121-1 formed on the upper surface of the glass layer 100. In this case, when the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are arranged symmetrically with respect to the glass layer 100, such an error may not occur. However, when the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are arranged misaligned with respect to the glass layer 100, such an error may occur. In the printed circuit board according to the example, even when the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are arranged misaligned with respect to the glass layer 100, such an error does not occur because the glass layer 100 has the second region 102. That is, the glass layer 100 may include the second region 102 having the second transmittance, thereby increasing the design freedom of the first-first wiring layer 121 - 1 disposed on the upper surface of the glass layer 100 and the first-second wiring layer 121 - 2 disposed on the lower surface of the glass layer 100 .

[0047] The through via 130 penetrating the glass layer 100 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. The through via 130 may penetrate the upper surface and the lower surface of the glass layer 100. The upper surface and the lower surface of the through via 130 may be substantially coplanar with the upper surface and the lower surface of the glass layer 100, respectively. Figure 3 , the through via 130 is shown as a filled via that passes through the upper and lower surfaces of the glass layer 100 and is filled with a metal layer, but the present disclosure is not limited thereto. The through via 130 may be a conformal via in which the metal layer is disposed along the wall surface of the via hole. The specific method of forming the through via 130 is not limited thereto. The through via 130 may perform various functions according to the design. For example, the through via 130 may include a ground via, a power via, a signal via, etc. The through via 130 may have a substantially circular shape, an elliptical shape, or a polygonal shape on a plane, but the present disclosure is not limited thereto, and in terms of ensuring close contact by increasing the specific surface area, the through via 130 may have a complex shape in which, for example, various shapes are combined into one shape on a plane. The side surface of the through via 130 may be substantially perpendicular to the upper and lower surfaces of the through via 130, but the present disclosure is not limited thereto, and as required, the through via 130 may be tapered in a cross section to have, for example, an hourglass shape or a tapered shape.

[0048] The upper and lower surfaces of the through-via 130 may be covered by the first-first wiring layer 121-1 and the first-second wiring layer 121-2, respectively. Such a configuration may be a result of forming the through-via 130, performing a planarization process of the glass layer 100 so that the upper and lower surfaces of the through-via 130 are substantially coplanar with the upper and lower surfaces of the glass layer 100, respectively, and forming the first-first wiring layer 121-1 and the first-second wiring layer 121-2. That is, the first metal layer 141 used as a seed layer for each of the first-first wiring layer 121-1 and the first-second wiring layer 121-2 may be configured to cover each of the upper and lower surfaces of the through-via 130.

[0049] The printed circuit board according to the example may further include a first via layer 131, the first via layer 131 connects the first-first wiring layer 121-1 and the second wiring layer 122 to each other, connects the first-second wiring layer 121-2 and the second wiring layer 122 to each other, and / or connects the second wiring layers 122 to each other. In this case, the first via layer 131 may penetrate at least a portion of the first-first insulating layer 111-1, at least a portion of the first-second insulating layer 111-2, and / or at least a portion of the second insulating layer 112.

[0050] The first via layer 131 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. Preferably, the metal may include copper (Cu), but the present disclosure is not limited thereto. The first via layer 131 may include a filled via in which the metal layer completely fills the via hole, but may also include a conformal via in which the metal layer is arranged along the wall surface of the via hole. The first via layer 131 may perform various functions according to the design. For example, the first via layer 131 may include a ground via, a power via, a signal via, etc. The first via layer 131 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The first via layer 131 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer as required.

[0051] In the printed circuit board according to the example, one second insulating layer 112 is shown as being stacked on each of the first-first insulating layer 111-1 and the first-second insulating layer 111-2, but the present disclosure is not limited thereto, and the second insulating layer 112 may include a plurality of insulating layers as required. That is, the second insulating layer 112 may be formed as one or more insulating layers. As a non-limiting example, the second insulating layer 112 may be disposed only on one of the first-first insulating layer 111-1 and the first-second insulating layer 111-2, and may have an asymmetric structure. In the glass layer 100 having high rigidity, warping is less likely to occur, and thus an asymmetric substrate may be realized. Since the second insulating layer 112 includes one or more insulating layers, the second wiring layer 122 may also include one or more wiring layers, and the first via layer 131 connecting the second wiring layers 122 to each other may also include one or more via layers.

[0052] The printed circuit board according to the example may also include a solder resist layer 150 disposed on the second insulating layer 112. The solder resist layer 150 may be disposed on the outermost side of the printed circuit board to protect the printed circuit board from the outside. The solder resist layer 150 may use a known solder resist. The solder resist layer 150 may include a liquid solder resist or a film type solder resist, but the present disclosure is not limited thereto. The solder resist layer 150 may use other types of insulating materials, and may include an insulating resin and a filler dispersed in the insulating resin, but may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but the present disclosure is not limited thereto. As required, the solder resist layer 150 may use other polymer materials. The solder resist layer 150 may have an opening, and at least a portion of the second wiring layer 122 may be exposed through the opening. The second wiring layer 122 exposed through the opening may be connected to a mainboard or another printed circuit board, and may also be connected to other devices such as semiconductor chips. As required, a surface treatment layer may be further formed on the pattern exposed through the opening. Optionally, metal bumps may be further formed on the patterns exposed through the openings.

[0053] The printed circuit board according to the example is not limited to Figure 3 The components shown in the figure may also include conventional components of a printed circuit board. That is, the printed circuit board according to the example may also include components that can be used by those skilled in the art.

[0054] Figure 4 is a schematic cross-sectional view showing another example of a printed circuit board.

[0055] Reference Figure 4 , a printed circuit board according to another example may be different from the printed circuit board according to the example in terms of the second region 102 of the glass layer 100 .

[0056] The second region 102 may be formed in at least a portion of the upper surface of the glass layer 100 where the first-first wiring layer 121-1 is not formed and at least a portion of the lower surface of the glass layer 100 where the first-second wiring layer 121-2 is not formed. Such a configuration may occur because an operation of processing the glass layer 100 to form the second region 102 is performed after an operation of forming the first-first wiring layer 121-1 and the first-second wiring layer 121-2. That is, with respect to the upper surface of the glass layer 100, when the first-first wiring layer 121-1 is formed and then the microstructure of the glass layer 100 is modified by performing laser processing on the upper side of the glass layer 100 to form the second region 102, the second region 102 may be formed along a region of the upper surface of the glass layer 100 where the first-first wiring layer 121-1 is not formed. With respect to the lower surface of the glass layer 100, for the same reason, the second region 102 may be formed along a region of the lower surface of the glass layer 100 where the first-second wiring layer 121-2 is not formed. That is, the second region 102 may be formed in a region other than the region where the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are formed, and may have a form as if it were engraved. In this case, the second region 102 may be provided in a region where the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are not formed, so that a portion of the first region 101 may be provided in contact with the first-first wiring layer 121-1 and the first-second wiring layer 121-2. Therefore, as Figure 4 As shown in , the second region 102 may be located on each of the upper and lower sides of the glass layer 100 , and at least a portion of the first region 101 may be located at a central portion between the upper and lower sides of the glass layer 100 .

[0057] exist Figure 4 , the second region 102 is shown to be formed vertically along the boundary of the first-first wiring layer 121-1 and the first-second wiring layer 121-2, but the present disclosure is not limited thereto. Depending on the method of processing the glass layer 100, the boundary between the first region 101 and the second region 102 may be formed in various ways. In particular, the change in the microstructure may not occur in a constant direction. In this case, a portion of the second region 102 may also penetrate into the lower portion of the first-first wiring layer 121-1 and the first-second wiring layer 121-2.

[0058] In the configuration other than the arrangement of the second region 102 , the same configuration as that of the printed circuit board according to the example is applicable to a printed circuit board according to another example, and thus repeated descriptions thereof will be omitted.

[0059] Method for manufacturing printed circuit board

[0060] FIG. 5A to FIG. 5Iis a schematic cross-sectional view illustrating an example of a method of manufacturing a printed circuit board.

[0061] Reference Figure 5A , a glass layer 100 may be prepared. The glass layer 100 may have only the first region 101, and may be in a state capable of transmitting light. The glass layer 100 may be in the form of a glass plate, or may be attached to another supporting device, such as a core or a clamp.

[0062] Reference FIG. 5B to FIG. 5D , a through via hole 130 penetrating the upper and lower surfaces of the glass layer 100 may be formed. The operation of forming the through via hole 130 in the glass layer 100 may include an operation of forming a through hole h penetrating the glass layer 100, an operation of forming a metal layer on an inner wall of the through hole h, and an operation of filling the through hole h. The operation of forming the through via hole 130 in the glass layer 100 may be performed using any known method of forming a through glass via (TGV) without limitation.

[0063] exist FIG. 5B to FIG. 5D , the through via 130 is shown as being formed only in the glass layer 100, but the present disclosure is not limited thereto. The through via 130 may extend to the upper and lower surfaces of the glass layer 100. In this case, the final operation of forming the through via 130 may further include the following operations: planarizing the upper and lower surfaces of the glass layer 100 so that the upper and lower surfaces of the glass layer 100 may be substantially coplanar with the upper and lower surfaces of the through via 130, respectively, as shown in FIG. Figure 5D In this case, the planarization process may be, but is not limited to, chemical mechanical polishing.

[0064] Reference Figure 5E , the second region 102 may be formed in the glass layer 100. The operation of forming the second region 102 may be performed by irradiating an ultrashort laser, but the present disclosure is not limited thereto. As described above in conjunction with the printed circuit board according to the example, any method capable of changing the microstructure of the glass layer 100 may be used without limitation.

[0065] Reference Figure 5F to Figure 5G , the first-first insulating layer 111-1 and the first-second insulating layer 111-2 may be formed after forming the first-first wiring layer 121-1 and the first-second wiring layer 121-2 on the glass layer 100. The first-first wiring layer 121-1 and the first-second wiring layer 121-2 may be formed using separate processes, or may be formed together in a single process. The first-first wiring layer 121-1 may be formed by an operation of forming a first metal layer 141 and an operation of forming a second metal layer 142 on the first metal layer 141, and the first-second wiring layer 121-2 may be formed by a similar method. In this case, refer to Figure 5G , AOI inspection can be performed. Figure 5G , the AOI inspection is shown as being performed on the upper side of the glass layer 100, but the present disclosure is not necessarily limited thereto, and the inspection may be performed on the lower side of the glass layer 100. However, the present disclosure is not limited thereto, and the inspection may also be performed on the lower side of the glass layer 100. Fig. 5F Operations ( Figure 5G After forming the second region 102 of the glass layer 100, light from the upper side may not be transmitted through the glass layer 100. Therefore, even when the AOI inspection is performed, an error is less likely to occur.

[0066] Reference Figure 5H , a second wiring layer 122 may be formed on the first-first insulating layer 111-1 and the first-second insulating layer 111-2, respectively, and a first via layer 131 connecting the second wiring layer 122 to the first-first wiring layer 121-1 and / or the first-second wiring layer 121-2 may be formed. The first via layer 131 and the second wiring layer 122 may be formed by forming a via hole penetrating at least a portion of the first-first insulating layer 111-1 and / or at least a portion of the first-second insulating layer 111-2, and then forming a first metal layer 141 and a second metal layer 142 in the via hole, but the present disclosure is not necessarily limited thereto. In the operation of forming the second wiring layer 122, an alignment mark may be detected to align the position where the second wiring layer 122 is to be formed. In this case, due to the second region 102 of the glass layer 100, the opposite side may have no influence on the detection result.

[0067] Reference Fig.5I , a second insulating layer 112 , a second wiring layer 122 , and a first via layer 131 may be further formed, and a solder resist layer 150 may be formed on the second insulating layer 112 .

[0068] The manufacturing method of the printed circuit board according to the example is not necessarily limited to the above method. Since the printed circuit board according to the example may further include other components, the manufacturing method may be partially added or changed.

[0069] FIG. 6A to FIG. 6I is a schematic cross-sectional view illustrating an example of a method of manufacturing a printed circuit board. Figure 6A-6D and Figure 6G-Figure 6I The operations shown in Figure 5A-5D and Figure 5G-Figure 5I To avoid redundancy, the Figure 6A-6D and Figure 6G-Figure 6I Description, and can refer to Figure 5A-5D and Figure 5G-Figure 5I Description.

[0070] Reference FIG. 6E to FIG. 6F, the first-first wiring layer 121-1 and the first-second wiring layer 121-2 may be formed on the glass layer 100, respectively, and then the second region 102 of the glass layer 100 may be formed. The method of forming the first-first wiring layer 121-1 and the first-second wiring layer 121-2 and the method of forming the second region 102 may be the same as the method of manufacturing a printed circuit board according to an example. Therefore, repeated description will be omitted.

[0071] In a method of manufacturing a printed circuit board according to another example, after the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are respectively formed, the second region 102 may be formed in the glass layer 100. Therefore, the second region 102 may be formed in a region where the first-first wiring layer 121-1 and the first-second wiring layer 121-2 are not formed.

[0072] In a method for manufacturing a printed circuit board according to another example, the description other than the description of the operation of forming the first-first wiring layer 121-1, the first-second wiring layer 121-2, and the second region 102 may be the same as the description of the method for manufacturing the printed circuit board according to the example, and thus repeated descriptions related thereto will be omitted.

[0073] As used herein, the term "covering" may include completely covering and at least partially covering, and may include directly covering and indirectly covering. In addition, the term "filling" may include not only completely filling, but also substantially filling, for example, may include the presence of some gaps, holes, etc.

[0074] As used herein, "substantially" may be a concept including measurement errors and process errors and / or positional deviations occurring in the manufacturing process, etc. For example, "substantially vertical" may include not only "completely vertical" but also "approximately vertical". Furthermore, "substantially coplanar" may include not only "completely coplanar" but also "approximately coplanar".

[0075] As used herein, the same insulating material may mean not only the completely same insulating material, but also the same type of insulating material. Therefore, the components of the insulating material may be substantially the same, but the specific component ratio thereof may vary slightly.

[0076] As used herein, a cross-sectional view may indicate a view of a cross-sectional shape of an object when the object is cut vertically, or may indicate a view of a cross-sectional shape of an object when the object is viewed from a side perspective. In addition, a plan view may indicate a view of a shape of an object when the object is cut horizontally, or may indicate a view of a planar shape of an object when the object is viewed from a top or bottom perspective.

[0077] As used herein, for convenience, "upper" in upper side, upper part, upper surface, etc. is used to refer to the direction toward the surface on which electronic components can be mounted based on the cross section of the drawings, and "lower" in lower side, lower part, lower surface, etc. is used to refer to the direction opposite to the direction. However, the above directions are defined for convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions, and the concepts of "upper" and "lower" may be changed at any time.

[0078] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" via an adhesive layer or the like. The term "electrical connection" may include both a case where components are "physically connected" and a case where components are "not physically connected." In addition, the terms "first," "second," and the like may be used to distinguish a component from another component, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the example embodiments.

[0079] As used herein, the term "exemplary embodiment" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same exemplary embodiment. In addition, particular characteristics or features may be combined in any suitable manner in one or more exemplary embodiments. For example, unless described to the contrary or inconsistent with the content in other exemplary embodiments, content described in a particular exemplary embodiment may be used in other exemplary embodiments even if the content is not described in other exemplary embodiments.

[0080] The terms used herein are only used to describe specific example embodiments, and the present disclosure is not limited thereby.As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0081] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A glass layer having a first region and a second region, the first region having a first transmittance, the second region having a second transmittance different from the first transmittance; as well as The first wiring layer is arranged on the glass layer.

2. The printed circuit board according to claim 1, wherein: The second region is located on each of an upper side and a lower side of the glass layer, and At least a portion of the first region is located in a central portion between the upper side and the lower side of the glass layer.

3. The printed circuit board according to claim 2, wherein: The second transmittance is lower than the first transmittance.

4. The printed circuit board according to claim 2, wherein: The thickness of the first region is greater than the thickness of the second region.

5. The printed circuit board according to claim 1, wherein The first wiring layer includes a first-first wiring layer disposed on an upper surface of the glass layer and a first-second wiring layer disposed on a lower surface of the glass layer, and At least a portion of the first-first wiring layer is disposed to be misaligned with at least a portion of the first-second wiring layer.

6. The printed circuit board according to claim 1, wherein The second region is provided in at least a portion of the glass layer where the first wiring layer is not provided.

7. The printed circuit board according to claim 1, wherein: The second region is provided in at least a portion of the glass layer where the first wiring layer is provided.

8. The printed circuit board according to claim 1, wherein: The glass layer includes colored glass.

9. The printed circuit board according to any one of claims 1 to 8, further comprising: A through via penetrates the glass layer to connect the first wiring layer, The first wiring layer includes a first metal layer and a second metal layer disposed on the first metal layer, and The first metal layer of the first wiring layer covers each of the upper and lower surfaces of the through via.

10. The printed circuit board according to claim 9, further comprising: a first insulating layer, disposed on the glass layer and covering the first wiring layer; One or more second insulating layers, disposed on the first insulating layer; as well as One or more second wiring layers are disposed on the one or more second insulating layers and / or within the one or more second insulating layers.

11. The printed circuit board according to claim 10, further comprising: A solder resist layer is provided on the one or more second insulating layers and has an opening exposing at least a portion of the one or more second wiring layers.

12. A printed circuit board, comprising: A glass layer having a first region located at a central portion of the glass layer relative to a stacking direction of the printed circuit board and a second region located at at least one of an upper side and a lower side of the glass layer; as well as A first wiring layer is disposed on the glass layer, The transmittance of the second region is lower than the transmittance of the first region.

13. The printed circuit board according to claim 12, further comprising: a first insulating layer, disposed on the glass layer and covering the first wiring layer; At least a portion of the second region is in contact with the first insulating layer.

14. The printed circuit board according to claim 12, wherein: A portion of the first region is in contact with the first wiring layer.

15. The printed circuit board according to claim 12, wherein: The first region is spaced apart from the first wiring layer.

16. The printed circuit board according to any one of claims 12 to 15, wherein: The thickness of the first region is greater than the thickness of the second region.

17. The printed circuit board according to claim 12, wherein: The second region is located on at least a portion of each of the upper side and the lower side of the glass layer and extends toward the central portion of the glass layer.

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