Multi-station parallel test method and system based on digital signal tester

Abstract

The invention provides a multi-station parallel test method and system based on a digital signal tester, and the method comprises the steps: combing the corresponding relation among a to-be-tested piece pin, a station serial number, a test module serial number and a channel serial number according to the test demands of a to-be-tested piece, and building a to-be-tested piece pin-station-test module mapping relation; performing primary parameter configuration on the pin of the to-be-tested piece according to the mapping relation; testing is executed, and part or all of the testing stations are selected according to the mapping relation for synchronous parallel testing; and the to-be-tested piece pin transmits a response signal to the corresponding test channel based on the corresponding station according to the mapping relation for test result acquisition and analysis. According to the invention, the concept of taking the pin of the tested piece as the center is enhanced by constructing the mapping relation of the pin of the piece to be tested, the station and the test module, so that the test efficiency and the resource utilization rate are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data testing, and in particular to a multi-station parallel testing method and system based on a digital signal tester. Background Art

[0002] Digital signal tester is the core equipment in digital, mixed analog and microwave integrated circuit test system, providing test environment for digital and mixed signal integrated circuit (IC) design, verification and production. Digital signal tester mainly generates digital test vector signals, or digital stimulus signals, composed of 0 (low level), 1 (high level), X (not driven), L (expected low level), H (expected high level), etc. On the one hand, it can provide multi-channel dynamic digital test vector signals for the tested integrated circuit; on the other hand, it can collect the response signal of the tested integrated circuit to determine whether the integrated circuit has faults.

[0003] In the chip mass production test phase, in order to meet the mass production test requirements, the test performance of the integrated circuit test system is extremely high. The traditional PXI bus digital signal tester test process has the following disadvantages:

[0004] 1) Long development cycle of multi-station test program: Each test station needs to develop a corresponding test program. The test program needs to configure the connection relationship between the pin of the device under test and the channel of the digital signal tester, channel timing, channel level and other information, and needs to build complex test vectors. The development workload is large, the code is redundant, and it is difficult for developers to modify and maintain it;

[0005] 2) Waste of test instrument resources: In traditional testing methods, one test station requires one or more test instruments, and the channels of the test instruments cannot be fully utilized, resulting in waste of resources;

[0006] 3) Poor synchronization effect and low test efficiency: The test system implements multi-station synchronous parallel testing. Compared with the parallel synchronous testing implemented inside the test instrument, the synchronization effect is poor and the test efficiency is low. Summary of the invention

[0007] In order to solve the above problems, the present invention proposes a multi-station parallel testing method and system based on a digital signal tester, and proposes a DUT pin-station-test module mapping model. The mapping model is centered on the DUT and the DUT pin, weakening the concept of the test module as an independent configuration and debugging core. After establishing the mapping relationship between the DUT pin and the test module, for all subsequent parameter settings and test executions, the user only needs to care about the DUT pin to complete the multi-station parallel test. Multi-station parameter configuration is performed based on the tester host computer software, and there is no need to develop complex multi-station test programs through the test system.

[0008] In order to achieve the above object, the present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a multi-station parallel testing method based on a digital signal tester, comprising:

[0010] According to the test requirements of the DUT, sort out the correspondence between the DUT pins, station numbers, test module numbers, and channel numbers, and establish a mapping relationship between the DUT pins, station numbers, and test modules;

[0011] According to the mapping relationship, the pins of the device under test are configured with parameters once, and the configured parameters are synchronously distributed to the corresponding test stations and test channels based on the mapping relationship;

[0012] Execute the test, select some or all of the test stations for synchronous and parallel testing according to the mapping model, synchronously send test vectors and detect received collected data; judge and analyze the test results according to the test stations, and transmit the response signal to the corresponding test channel based on the corresponding station according to the mapping relationship for test result collection and analysis.

[0013] Preferably, the mapping relationship between the pin of the device under test, the station number, the test module number and the channel number is established according to the test requirements of the device under test, specifically including:

[0014] The pins of the device under test, the test station and the test module are taken as nodes, and the connection between each pin of the device under test and the test station and the test module is performed according to the specific test requirements in different test demand scenarios to obtain the connection rules;

[0015] According to the connection rules, the mapping relationship is determined for different test requirement scenarios.

[0016] Preferably, the mapping relationship includes one workstation mapping to one module, one workstation mapping to multiple modules, multiple workstations mapping to one module, and multiple workstations mapping to multiple modules;

[0017] The mapping relationship of mapping one station to one module is applied to the test requirement that only a single test station is needed and the number of DUT pins is consistent with the number of test module channels: each test station uses one test module, and the DUT pins are connected to the test module channels in sequence;

[0018] The mapping relationship of mapping one station to multiple modules is applied to the test requirements of only one test station and a large number of DUT pins requiring collaborative testing by multiple test modules: each test station uses multiple test modules, the DUT pins are connected to the channels of each test module in turn, and multiple test modules work synchronously;

[0019] The mapping relationship of mapping multiple stations to one module is applied to the test requirement that the number of pins of the DUT is small and only a single test module is used to complete the multi-station test: multiple test stations share one test module, and multiple DUTs are connected to different channels of the test module in turn;

[0020] The mapping relationship between the multiple stations and the multiple modules is applied to test requirements with complex test logic and connection relationships: each test station corresponds to channels of multiple test modules, the test of each test station requires the cooperation of multiple test modules, and each test module contains the tests of multiple stations.

[0021] Preferably, performing parameter configuration on the pins of the device under test once according to the mapping relationship, and synchronously distributing the configured parameters to the corresponding test stations and test channels based on the mapping relationship, specifically includes:

[0022] The pin of the device under test is used as the main line to perform a timing, level, and test vector parameter configuration. Based on the mapping relationship, the test station and corresponding test channel associated with the pin are identified, and the parameter configuration is completed synchronously.

[0023] Preferably, the test vector signal includes a low level signal, a high level signal, a non-driven signal, an expected low level signal and an expected high level signal.

[0024] Preferably, the test results are stored separately according to the test stations, and the test results of a specific test station can be selected and viewed according to needs.

[0025] Preferably, the method further includes: saving the mapping relationship between the pin of the device under test, the workstation and the test module established in this test to a local file for calling in the next test.

[0026] In a second aspect, the present invention provides a multi-station parallel testing system based on a digital signal tester, comprising:

[0027] A mapping relationship building module is used to sort out the correspondence between the pins of the DUT, the station number, the test module number, and the channel number according to the test requirements of the DUT, and establish a mapping relationship between the pins of the DUT, the station number, and the test module number;

[0028] A parameter configuration module is used to perform parameter configuration on the pins of the device under test according to the mapping relationship, and synchronously distribute the configured parameters to the corresponding test stations and test channels based on the mapping relationship;

[0029] The test and analysis module is used to execute the test, select some or all of the test stations for synchronous and parallel testing according to the mapping relationship, synchronously send test vectors and detect received collected data; judge and analyze the test results according to the test stations, and transmit the response signal to the corresponding test channel based on the corresponding station according to the mapping relationship for result collection and analysis.

[0030] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a multi-station parallel testing method based on a digital signal tester described in the first aspect.

[0031] In a fourth aspect, the present invention provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in a multi-station parallel testing method based on a digital signal tester described in the first aspect are implemented.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention constructs a mapping model of the pin of the device to be tested-station-test module and determines a variety of mapping relationships according to the specific test requirements in different test demand scenarios. Developers select relationships according to pin requirements and configure parameters once with them as the core, which can be distributed to stations and channels synchronously, eliminating the tediousness of each station independently developing programs, configuring a large amount of information, and building complex vectors, reducing workload and redundancy, and shortening the development cycle. At the same time, flexible mapping relationships can flexibly configure instrument channels according to actual conditions, multiple stations sharing or single station multiple modules, etc., and select stations for testing on demand, dynamically allocate resources, and improve resource utilization. In addition, with the help of the multi-station synchronous parallel testing mode, the overall test time is effectively shortened, so that the test process is optimized and accelerated in both the development and execution links.

[0034] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their description are used to explain the present invention but do not constitute a limitation of the present invention.

[0036] Figure 1 A main flow chart of a multi-station parallel testing method based on a digital signal tester provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the connection relationship between the pin stations and the channels provided in an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of a DUT pin-station-tester channel mapping model provided in an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a channel sharing of a digital excitation signal and a response receiving signal provided by an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of test station selection and test vector sending provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0042] Embodiment 1

[0043] like Figure 1 As shown, this embodiment discloses a multi-station parallel testing method based on a digital signal tester, comprising the following steps:

[0044] S1: According to the test requirements of the DUT, sort out the correspondence between the DUT pins, station numbers, test module numbers, and channel numbers, and establish a mapping relationship between the DUT pins, station numbers, and test modules;

[0045] S2: According to the mapping relationship, perform parameter configuration on the pins of the device under test, and synchronously distribute the configured parameters to the corresponding test stations and test channels based on the mapping relationship;

[0046] S3: Execute the test, select some or all of the test stations for synchronous and parallel testing according to the mapping model, synchronously send test vectors and detect received acquisition data; judge and analyze the test results according to the test stations, and transmit the response signal to the corresponding test channel based on the corresponding station according to the mapping relationship for result collection and analysis.

[0047] Next, combine Figure 1 , a multi-station parallel testing method based on a digital signal tester disclosed in this embodiment is described in detail.

[0048] In S1, according to the test requirements of the DUT, the correspondence between the DUT pins, station numbers, test module numbers, and channel numbers is sorted out to establish a mapping relationship between the DUT pins, stations, and test modules. Different stations can select different channels, and each test station selects a corresponding test channel for connection. At the same time, channel multiplexing is supported based on the data transmission and reception characteristics of the channel. If the channel only sends test vectors and does not receive and collect data, the test vector signal of the channel can be divided into multiple identical signals through hardware connection, that is, the same channel can be used in multiple test stations and transmitted to the DUT pins based on a multi-station sharing method, further saving test resources.

[0049] Among them, the mapping relationship between the pin of the device under test, the workstation and the test module is constructed. The specific process is as follows:

[0050] According to the test requirements of the DUT, the DUT has different test items, different pins that need to be connected, and different parameter configurations and test vectors. The DUT pins, test stations, test modules, and test module channels are extracted as key entities, and the DUT pins, test stations, and test modules are taken as nodes to analyze the connection relationship between each DUT pin and the test station and test module under different test requirement scenarios.

[0051] Furthermore, after the test is finished, the mapping relationship between the pin of the device under test, the workstation and the test module established in the test is saved to a local file, and the corresponding mapping relationship is called to perform the test according to the test requirements of the new device under test.

[0052] The schematic diagram of the connection relationship between the pin station and the channel is as follows Figure 2 shown.

[0053] The mapping relationship includes flexible and diverse mapping relationships such as one workstation mapping to one module, one workstation mapping to multiple modules, multiple workstations mapping to one module, and multiple workstations mapping to multiple modules.

[0054] (1) In the one-station-one-module mode, each test station needs to use a test module, and the pins of the device under test are connected to the channels of the test module in sequence. This mapping relationship is mainly used in scenarios where there is only one test station and the number of pins of the device under test is basically the same as the number of channels of the test module.

[0055] (2) In the mode of mapping multiple modules to one workstation, due to the large number of pins of the DUT, each test station needs to use multiple test modules. The pins of the DUT are connected to the channels of each test module in turn, and multiple test modules work synchronously. This mapping relationship is mainly used in scenarios where there is only one test station, the number of DUT pins is large, and multiple test modules are required for testing.

[0056] (3) In the mode where multiple stations map to one module, the number of pins of the device under test is relatively small, and multiple test stations share one test module. Multiple devices under test are connected to different channels of the test module in turn. This mapping relationship is mainly used in scenarios where the number of pins of the device under test is very small and one test module can be used to complete multiple station tests.

[0057] (4) Multiple stations map to multiple modules. In the mode, each test station corresponds to the channels of multiple test modules. The test of each test station requires multiple test modules. At the same time, each test module contains the tests of multiple stations. This mapping relationship is mainly used in scenarios where the test logic and connection relationship of the DUT are relatively complex. The "DUT pin-station-test module" mapping model is shown in the figure. Figure 3 shown.

[0058] The present embodiment sets up multiple mapping relationships to provide a unified and standardized framework for testing. Multiple mapping relationships can be standardized and adapted according to different test scenarios, such as the number of workstations, the number of pins of the device under test, and the complexity of the test logic. In different projects, testers can follow the established mapping relationship rules, clarify the connection methods of each element, reduce differences in human judgment and arbitrary operations, and ensure the consistency of the test process. For example, when there is a single workstation and the pins and channels match, one workstation is used to map one module to make the test settings standardized and orderly; under complex logic, multiple workstations are mapped to multiple modules according to the rules to ensure the standardization of the coordination between each workstation and module. This avoids the test confusion caused by the lack of unified standards, improves the repeatability and comparability of the test, is conducive to the effective comparison and analysis of data between different tests, and also provides clear guidance for the collaboration of the test team, improving the overall test quality and efficiency.

[0059] In S2, a mapping relationship is selected according to the test requirements of the pins of the device under test. Before the test is performed, parameter configuration is first performed.

[0060] The pin of the device under test is used as the main line to configure the timing, level, test vector and other parameters. The pin of the device under test only needs to configure the timing, level, test vector and other parameters once. According to the mapping relationship, the configured parameters will be synchronously distributed to the test station and test channel corresponding to the pin of the device under test in the upper computer software to achieve synchronous configuration.

[0061] The timing parameter configuration of the device under test includes information such as cycle, drive format, drive start, drive data, drive return, drive end and comparison edge.

[0062] The level parameter configuration includes information such as driving high level, driving low level, expected high level, expected low level and termination mode.

[0063] The test vector parameters include setting the pin states of 1, 0, H, L, X, etc. for each test vector, as well as vector opcodes such as repeat, halt, and jump.

[0064] In terms of parameter setting, this embodiment only needs to configure the timing, level, test vector and other parameters for the pin of the device under test once, and then rely on the mapping relationship to automatically synchronize the parameters to the corresponding test station and test channel. There is no need to perform tedious parameter settings for each station and each test module channel separately, thereby improving configuration efficiency.

[0065] In S3, the test is executed, and some or all of the test stations are selected for synchronous and parallel testing according to the mapping relationship. The pins of the device under test transmit response signals based on the corresponding stations to the corresponding test channels for test result collection and analysis according to the mapping relationship.

[0066] After the parameters are configured, the channels of the test module can support sharing by multiple test stations according to their specific functions. The digital signal tester mainly provides digital excitation signals and response receiving signals. When the channel of the test module provides a digital excitation signal, the digital excitation signal of the channel can be divided into multiple identical signals through hardware connection and provided to multiple test stations for sharing. When the channel of the test module provides a response receiving signal, since the test results received by each test station are different, each test station needs to use a different channel for response reception. Sharing channels by multiple test stations of the test module can save test resources and reduce test costs. The schematic diagram of sharing digital excitation signal and response receiving signal channels is shown in the figure. Figure 4 shown.

[0067] According to the mapping relationship, some or all test stations can be selected for synchronous parallel testing, synchronously sending test vectors and detecting received data. Some or all test stations can be selected for parallel testing according to test requirements. After selecting the test station, only the selected test station will be tested. The schematic diagram of test station selection and test vector sending is shown in the figure. Figure 5 shown.

[0068] In the test execution stage of this embodiment, it is also based on the mapping relationship. The pin of the device under test can transmit the response signal to the corresponding test channel according to the preset rules for subsequent test result collection and analysis. During the whole process, the user only needs to grasp the key of the pin of the device under test, which can smoothly promote the orderly progress of multi-station parallel testing and improve the convenience of operation and test efficiency.

[0069] As a further implementation, the test results are judged and analyzed according to the test stations. The test results of each test station are stored separately. After selecting one or several test stations, you can check whether the test results of the corresponding test station are correct. The test results of each test station do not affect each other.

[0070] In this embodiment, during the entire test process, the corresponding mapping relationship is first selected around the test requirements of the pins of the device under test. Regardless of the specific mapping situation, such as one station mapping one module, one station mapping multiple modules, etc., it is based on the pins of the device under test, considering its number, the corresponding test requirement scenario and other factors to determine how to map and connect with the station and the test module; and when the pins of the device under test are subsequently configured with parameters, the pins of the device under test are also used as the main line, and based on the determined mapping relationship, the corresponding test stations and corresponding test channels are associated to complete the parameter configuration work synchronously. Therefore, the core of the entire process revolves around the device under test and the pins of the device under test, so as to drive the operation of other related links, reflecting the characteristics of being centered on the pins of the device under test. It avoids the cumbersome process of configuring each station and each channel one by one, greatly shortens the configuration time, and reduces the investment in manpower costs.

[0071] The user selects the appropriate mapping relationship according to the pins of the DUT, and then based on this mapping relationship, the configured parameters can be easily and synchronously distributed to the corresponding test stations and test channels, and then the test is executed, and the analysis results are collected, etc. The user does not need to focus too much on configuring the connection relationship between the pins of the DUT and the channels of the digital signal tester, channel timing, channel level and other information, and building complex test vectors. Instead, with the help of the well-organized relationship in the mapping model, a series of test-related operations can be completed through the key entry point of the pins of the DUT, so the concept of the test module is relatively weakened. The time spent on focusing on the test module in the early preparation stage is reduced, and the overall efficiency of multi-station parallel testing is effectively improved.

[0072] Embodiment 2

[0073] This embodiment provides a multi-station parallel testing system based on a digital signal tester, comprising:

[0074] A mapping relationship building module is used to sort out the correspondence between the pins of the DUT, the station number, the test module number, and the channel number according to the test requirements of the DUT, and establish a mapping relationship between the pins of the DUT, the station number, and the test module number;

[0075] A parameter configuration module is used to perform parameter configuration on the pins of the device under test according to the mapping relationship, and synchronously distribute the configured parameters to the corresponding test stations and test channels based on the mapping relationship;

[0076] The test and analysis module is used to execute the test, select some or all of the test stations for synchronous and parallel testing according to the mapping relationship, synchronously send test vectors and detect received collected data; judge and analyze the test results according to the test stations, and transmit the response signal to the corresponding test channel based on the corresponding station according to the mapping relationship for result collection and analysis.

[0077] Embodiment 3

[0078] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the multi-station parallel testing method based on a digital signal tester as described in the first embodiment above are implemented.

[0079] Embodiment 4

[0080] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in a multi-station parallel testing method based on a digital signal tester as described in the first embodiment above are implemented.

[0081] The steps or modules involved in the above embodiments 2 to 4 correspond to those in embodiment 1. For the specific implementation, please refer to the relevant description of embodiment 1. The term "computer-readable storage medium" should be understood as a single medium or multiple media including one or more instruction sets; it should also be understood to include any medium that can store, encode or carry an instruction set for execution by a processor and enable the processor to execute any method in the present invention.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-station parallel testing method based on a digital signal tester, characterized in that: include: According to the test requirements of the DUT, sort out the correspondence between the DUT pins, station numbers, test module numbers, and channel numbers, and establish a mapping relationship between the DUT pins, station numbers, and test modules; According to the mapping relationship, the pins of the device under test are configured with parameters once, and the configured parameters are synchronously distributed to the corresponding test stations and test channels based on the mapping relationship; Execute the test, select part or all of the test stations for synchronous and parallel testing according to the mapping model, and synchronously send test vectors and detect received collected data; The test results are judged and analyzed according to the test stations, and the response signals are transmitted to the corresponding test channels based on the corresponding stations according to the mapping relationship for test result collection and analysis.

2. A multi-station parallel testing method based on a digital signal tester as claimed in claim 1, characterized in that: According to the test requirements of the DUT, the corresponding relationship between the DUT pin, the station number, the test module number, and the channel number is sorted out, and a mapping relationship between the DUT pin, the station number, and the test module number is established, which specifically includes: The pins of the device under test, the test station and the test module are taken as nodes, and the connection between each pin of the device under test and the test station and the test module is performed according to the specific test requirements in different test demand scenarios to obtain the connection rules; According to the connection rules, the mapping relationship is determined for different test requirement scenarios.

3. A multi-station parallel testing method based on a digital signal tester as claimed in claim 1, characterized in that: The mapping relationship includes one workstation mapping to one module, one workstation mapping to multiple modules, multiple workstations mapping to one module, and multiple workstations mapping to multiple modules; The mapping relationship of mapping one station to one module is applied to the test requirement that only a single test station is needed and the number of DUT pins is consistent with the number of test module channels: each test station uses one test module, and the DUT pins are connected to the test module channels in sequence; The mapping relationship of mapping one station to multiple modules is applied to the test requirements of only one test station and a large number of DUT pins requiring collaborative testing by multiple test modules: each test station uses multiple test modules, the DUT pins are connected to the channels of each test module in turn, and multiple test modules work synchronously; The mapping relationship of mapping multiple stations to one module is applied to the test requirement that the number of pins of the DUT is small and only a single test module is used to complete the multi-station test: multiple test stations share one test module, and multiple DUTs are connected to different channels of the test module in turn; The mapping relationship between the multiple stations and the multiple modules is applied to test requirements with complex test logic and connection relationships: each test station corresponds to channels of multiple test modules, the test of each test station requires the cooperation of multiple test modules, and each test module contains the tests of multiple stations.

4. A multi-station parallel testing method based on a digital signal tester as claimed in claim 1, characterized in that: The method of performing parameter configuration on the pin of the device under test according to the mapping relationship and synchronously distributing the configured parameters to the corresponding test stations and test channels based on the mapping relationship specifically includes: The pin of the device under test is used as the main line to perform a timing, level, and test vector parameter configuration. Based on the mapping relationship, the test station and corresponding test channel associated with the pin are identified, and the parameter configuration is completed synchronously.

5. A multi-station parallel testing method based on a digital signal tester as claimed in claim 1, characterized in that: The test vector signals include a low level signal, a high level signal, a non-driving signal, an expected low level signal and an expected high level signal.

6. A multi-station parallel testing method based on a digital signal tester as claimed in claim 1, characterized in that: The test results are stored separately according to the test stations, and the test results of a specific test station can be selected and viewed according to needs.

7. A multi-station parallel testing method based on a digital signal tester as claimed in claim 1, characterized in that: Also includes: The mapping relationship between the DUT pin, station and test module established in this test is saved to a local file for reference in the next test.

8. A multi-station parallel testing system based on a digital signal tester, characterized in that: include: A mapping relationship building module is used to sort out the correspondence between the pins of the DUT, the station number, the test module number, and the channel number according to the test requirements of the DUT, and establish a mapping relationship between the pins of the DUT, the station number, and the test module number; A parameter configuration module is used to perform parameter configuration on the pins of the device under test according to the mapping relationship, and synchronously distribute the configured parameters to the corresponding test stations and test channels based on the mapping relationship; A test and analysis module, used to execute the test, select part or all of the test stations for synchronous and parallel testing according to the mapping relationship, synchronously send the test vectors and detect the received collected data; The test results are judged and analyzed according to the test stations, and the response signals are transmitted to the corresponding test channels based on the corresponding stations according to the mapping relationship for result collection and analysis.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in a multi-station parallel testing method based on a digital signal tester as described in any one of claims 1 to 7 are implemented.

10. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the multi-station parallel testing method based on a digital signal tester as described in any one of claims 1 to 7 are implemented.

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