Power failure protection circuit, micro-control system and chip

Abstract

The invention discloses a power-down protection circuit, a micro-control system and a chip, and relates to the technical field of data storage and the like, the power-down protection circuit is arranged in a micro-control system MCU, and the power-down protection circuit comprises a low-voltage detection module which is configured to generate a power-down signal when detecting a low-voltage signal of the micro-control system MCU; the power failure management module is connected with the low-voltage detection module and the peripheral access control module, the peripheral access control module is connected with the data storage module, and the power failure management module is configured to respond to the power failure signal, generate a first control signal and send the first control signal to the peripheral access control module; the peripheral access control module generates a second control signal based on the first control signal and sends the second control signal to the data storage module; and the data storage module comprises a first memory and a second memory, and is configured to store the data in the first memory to the second memory in response to the second control signal. The power-down protection circuit is built in the micro-control system MCU, is realized through hardware, does not need software and a CPU to participate, and is faster in response.

Description

Technical Field

[0001] The present invention relates to the technical fields of data storage, and in particular to a power-off protection circuit, a microcontroller system and a chip. Background Art

[0002] In automotive electronic systems, there are many occasions where it is necessary to save some important data information to non-volatile memory (NVM) in time after the system loses power, so that the system can complete power-on initialization faster or continue to operate normally as expected when it is powered on again next time. For example, the digital instrument system needs to record the setting information or real-time status information of the instrument panel, odometer, and graphics status; the body control unit (BCM) needs to store the setting information and operating position information of the sunroof, windows, and electric seats after power failure; the advanced driver assistance system (ADAS) needs to record and store sensor data related to driving safety in real time, etc. These setting information, real-time function operation data and security record data are indispensable, especially when the system loses power, they need to be stored in NVM in a timely and reliable manner. Therefore, when designing system solutions for various ECUs (Electronic Control Units), the current solution is to integrate multiple hardware circuits and software factors to achieve power failure detection, data storage and recovery functions. This is mainly achieved through complex hardware circuits inside and outside the MCU (Microcontroller Unit, also known as a single-chip microcomputer), and complex software processes and algorithms need to be designed inside the chip. The system is complex and the application cost is high. There is a risk of untimely power failure detection and data storage, and data damage. Summary of the invention

[0003] To this end, the purpose of the embodiments of the present invention is to propose a power-off protection circuit, a microcontroller system and a chip. The power-off protection circuit is built into the microcontroller system MCU and is implemented through hardware, without the need for software and CPU participation, and has a faster response.

[0004] An embodiment of the present invention provides a power-off protection circuit, which is built into a microcontroller system MCU, and includes: a low-voltage detection module, which is configured to generate a power-off signal and send the power-off signal to a power-off management module when a low-voltage signal of the microcontroller system MCU is detected; a power-off management module, which is connected to the low-voltage detection module and a peripheral access control module, and the peripheral access control module is connected to a data storage module, and the power-off management module is configured to respond to the power-off signal, generate a first control signal and send the first control signal to the peripheral access control module, so that the peripheral access control module generates a second control signal based on the first control signal, and sends the second control signal to the data storage module; a data storage module, which includes a first memory and a second memory, and the data storage module is configured to respond to the second control signal and store data in the first memory to the second memory.

[0005] Exemplarily, the low voltage detection module includes a voltage comparator, a first input terminal of the voltage comparator is connected to the power supply voltage of the microcontroller system MCU, a second input terminal of the voltage comparator is connected to a voltage reference source, and the voltage comparator is configured to generate a power-off signal to the power-off management module when the power supply voltage is less than the voltage reference source voltage.

[0006] Exemplarily, the power-off management module is also connected to the low-power oscillator module and the system clock module, and the power-off management module is also used to: respond to the power-off signal, generate a start signal and send the start signal to the low-power oscillator module, so that the low-power oscillator module generates a working clock and sends the working clock to the power-off management module, the peripheral access control module, and the data storage module; and / or, respond to the power-off signal, generate a shutdown signal and send the shutdown signal to the system clock module, so that the system clock module shuts down the system clock.

[0007] Exemplarily, the peripheral device access control module is further used to: control the first external device to be turned off based on the first control signal, and / or control the second external device to enter a power-off mode.

[0008] Exemplarily, the data storage module also includes a dedicated multi-channel DMA control unit, a memory address offset management unit, and a cyclic redundancy correction unit. The dedicated multi-channel DMA control unit is connected to the peripheral access control module. The dedicated multi-channel DMA control unit is also connected to the memory address offset management unit, the cyclic redundancy correction unit, the first memory, and the second memory. The first memory includes multiple first storage areas, and the second memory includes multiple second storage areas. The dedicated multi-channel DMA control unit is configured to respond to the second control signal to store the data in the multiple first storage areas in parallel in the corresponding multiple second storage areas.

[0009] Exemplarily, the memory address offset management unit is connected to the first memory and the second memory, and the memory address offset management unit is configured to determine a synchronization offset address of a data transmission address of the first memory and the second memory.

[0010] Exemplarily, the cyclic redundancy correction unit is connected to the first memory, and the cyclic redundancy correction unit is configured to determine a cyclic redundancy correction code of data in the first memory.

[0011] Exemplarily, the dedicated multi-channel DMA control unit is specifically used to: read the data to be stored in the first storage area and obtain the cyclic redundancy correction code of the data to be stored; and store the data to be stored and the cyclic redundancy correction code in at least one of multiple second storage areas based on the synchronization offset address of the data to be stored.

[0012] Another embodiment of the present invention provides a micro control system, wherein the micro control system includes the power-off protection circuit as described above.

[0013] Another embodiment of the present invention provides a chip, wherein the chip includes the microcontrol system as described above.

[0014] In the above implementation, the power-off protection circuit is built into the microcontrol system MCU, including: a low voltage detection module, configured to generate a power-off signal when a low voltage signal of the microcontrol system MCU is detected; a power-off management module, the power-off management module is connected to the low voltage detection module and the peripheral access control module, the peripheral access control module is connected to the data storage module, the power-off management module is configured to respond to the power-off signal, generate a first control signal and send it to the peripheral access control module, so that the peripheral access control module generates a second control signal based on the first control signal and sends it to the data storage module; the data storage module includes a first memory and a second memory, and the data storage module is configured to respond to the second control signal and store the data in the first memory to the second memory. The power-off protection circuit of the present invention is built into the microcontrol system MCU, is implemented by hardware, does not require the participation of software and CPU, and responds faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a power-off protection circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of a power-off protection circuit provided in an embodiment of the present invention; Figure 3 A schematic diagram of a data storage module provided in an embodiment of the present invention; Figure 4 A schematic diagram of a microcontroller system provided by an embodiment of the present invention; Figure 5 A schematic diagram of a chip provided in accordance with an embodiment of the present invention.

[0016] Reference numerals: 101- low voltage detection module, 102- power-off management module, 103- peripheral access control module, 104- data storage module, 105- low power oscillator module, 106- system clock module, 401- dedicated multi-channel DMA control unit, 402- memory address offset management unit, 403- cyclic redundancy correction unit, 1- first memory, 2- second memory, 100- power-off protection circuit, 400- micro control system, 500- chip. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0018] In automotive electronic systems, there are many occasions where it is necessary to save some important data information to non-volatile memory (NVM) in time after the system loses power, so that the system can complete power-on initialization faster or continue to operate normally as expected when it is powered on again next time. For example, the digital instrument system needs to record the setting information or real-time status information of the instrument panel, odometer, and graphics status; the body control unit (BCM) needs to store the setting information and operating position information of the sunroof, windows, and electric seats after power failure; the advanced driver assistance system (ADAS) needs to record and store sensor data related to driving safety in real time, etc. These setting information, real-time function operation data and security record data are indispensable, especially when the system loses power, they need to be stored in NVM in a timely and reliable manner. Therefore, when designing system solutions for various ECUs (Electronic Control Units), the current solution is to integrate multiple hardware circuits and software factors to achieve power failure detection, data storage and recovery functions. This is mainly achieved through complex hardware circuits inside and outside the MCU (Microcontroller Unit, also known as a single-chip microcomputer), and complex software processes and algorithms need to be designed inside the chip. The system is complex and the application cost is high. There is a risk of untimely power failure detection and data storage, and data damage.

[0019] Based on this, the present invention proposes a power-off detection and automatic data storage module built into a chip, especially an MCU. When it is detected that the system voltage drops to a specific range, the power-off management unit is activated. Without the need for a CPU, a system clock, or software code, a small portion of data in the SRAM is automatically and quickly stored in the Dflash inside the MCU. This effectively solves the problems of complex software, untimely response, and the risk of data corruption in the current solution.

[0020] Figure 1 A schematic diagram of a power-off protection circuit according to an embodiment of the present invention.

[0021] As an example, Figure 1 As shown, the power-off protection circuit includes: A low voltage detection module 101, the low voltage detection module 101 is configured to generate a power-off signal and send the power-off signal to a power-off management module 102 when a low voltage signal of a microcontroller system MCU is detected; a power-off management module 102, the power-off management module 102 is connected to the low voltage detection module 101 and the peripheral access control module 103, the peripheral access control module 103 is connected to the data storage module 104, the power-off management module 102 is configured to respond to the power-off signal, generate a first control signal and send the first control signal to the peripheral access control module 103, so that the peripheral access control module 103 generates a second control signal based on the first control signal, and sends the second control signal to the data storage module 104; a data storage module 104, the data storage module 104 includes a first memory and a second memory, the data storage module 104 is configured to respond to the second control signal and store the data in the first memory to the second memory. It should be noted that the power-off protection circuit of the present invention is built into the microcontroller system MCU.

[0022] For example, in an automotive electronic system, each ECU has its normal working voltage to ensure the normal operation of its hardware and software; however, during operation, abnormal power failure of certain components may occur frequently and unavoidably due to human operation or component failure. In order to avoid losing some important parameter setting information in the system, real-time operating status information of certain functions, and parameter records related to safety, the hardware and software of the ECU must be able to operate normally for a short period of time before the power is completely lost, and these data must be stored in the non-volatile memory (NVM) in a timely manner.

[0023] Exemplarily, the low voltage detection module 101 is directly connected to the inside of the microcontrol system MCU, and generates a power-off signal when a low voltage signal of the microcontrol system MCU is detected. The low voltage signal of the microcontrol system MCU can be a human operation, or a low voltage signal caused by abnormal power failure of some components due to a part failure. The low voltage detection module 101 is connected to the power-off management module 102, and the low voltage detection module 101 sends the generated power-off signal to the power-off management module 102, and the power-off management module 102 responds to the power-off signal and controls the microcontrol system MCU to enter the power-off operation mode. The power-off management module 102 is also connected to the peripheral access control module 103, and the power-off management module 102 responds to the power-off signal, generates a first control signal, and sends the first control signal to the peripheral access control module 103, so that the peripheral access control module 103 generates a second control signal, and the peripheral access control module 103 is also connected to the data storage module 104, and the peripheral access control module 103 sends the second control signal to the data storage module 104 so that the data storage module 104 stores necessary data.

[0024] Exemplarily, the data storage module 104 includes a first memory and a second memory. It can be understood that the first memory is a memory for storing data when the system is running, and the second memory is a memory for storing some necessary data when the system is powered off.

[0025] The power-off protection circuit of the present invention is built into the system MCU in the form of hardware. When the system is powered off, the internal processing of the chip is implemented without the participation of software code, and the robustness and adaptability are better.

[0026] As an example, the power supply mode of the microcontroller system MCU can be an external power supply mode. For example, by using a backup battery, a redundant battery backup is added to the ECU system. When the system is powered off, the backup battery can continue to provide stable power to the CPU and the necessary external logic circuits and memory. The software code in the system has enough time to complete power-off detection and data storage. The advantages are sufficient power, high reliability, and sufficient time for software processing, so the software algorithm will be relatively simple. The disadvantages are increased redundancy costs and the risk of the backup battery's service life. Another example is the use of an external large capacitor energy storage method. In the MCU power supply circuit, usually in the front and end stages of the power supply circuit, an energy storage capacitor of appropriate capacity is added. When the system is powered off, the first thing to disconnect is the unnecessary or power-consuming peripheral circuits. The remaining power in the capacitor is used to power the CPU and the necessary peripheral circuits for a short period of time. In the current reference design, a capacitor of about 100uF can allow the MCU to work at a minimum system of 20mA and maintain a time of about 30ms-50ms. The software inside the MCU needs to complete a certain amount of data storage within this time range. The advantages are low cost, and the disadvantages are compact power and processing time, and high software performance requirements. The present invention can select the power supply mode of the microcontroller system MCU according to the specific application scenario.

[0027] As an example, the first memory may be an SRAM memory (Static Random-Access Memory). To ensure the security of necessary parameters, the second memory may be a non-volatile memory NVM. According to the chip process principle, the following three types of non-volatile memory NVM are commonly used: 1. NorFlash: Features: It must be erased before it can be written. The erasing speed is slow, generally 1ms-20ms per sector; while the reading and writing speed is fast, generally a few us to tens of us per sector; the number of erasures is generally 100,000 times; it can be integrated into the MCU or a separate chip outside the MCU, and the MCU accesses it through the SPI bus. The code memory Pflash and data memory DFlash integrated in the MCU are both NorFlash.

[0028] 2. EEPROM or Ferroelectric RAM (FRAM): Both of these memories are non-volatile, and their read and write performance is better than NorFlash, and there is no need to erase before reading and writing; after writing a page, EEPROM needs to wait for 5~10ms, while FRAM can be read and written as conveniently and quickly as SRAM; both of these NVMs can be integrated into the MCU or can be separate chips outside the MCU, which are accessed by the MCU through the SPI bus, but compared with NorFlash, the cost is higher when integrated into the MCU, and the capacity is also smaller.

[0029] The second memory can be any of the above three types. Considering the chip built-in mode, integration process maturity, and cost factors, preferably, DFlash in NorFlash can be selected as the second memory. The following takes DFlash as the second memory as an example.

[0030] As an example, the low voltage detection module includes a voltage comparator, a first input terminal of the voltage comparator is connected to the power supply voltage of the microcontroller system MCU, a second input terminal of the voltage comparator is connected to the voltage reference source, and the voltage comparator is configured to generate a power-off signal to the power-off management module when the power supply voltage is less than the voltage reference source voltage.

[0031] Exemplarily, the low voltage detection in the prior art continuously collects the external power supply voltage through the internal ADC (Analog-to-Digital Converter) module and acquisition channel of the MCU in cooperation with the software code, while the low voltage detection module 101 of the present invention has a built-in analog voltage comparator, the first input end of the voltage comparator is connected to the power supply voltage of the microcontroller system MCU, and the second input end of the voltage comparator is connected to the voltage reference source. Before the power of the MCU is powered off, the voltage comparator detects the power supply voltage in real time. When the power supply voltage drops below the corresponding voltage reference source power supply, the voltage comparator flips and outputs a power-off signal to the power-off management unit.

[0032] Exemplarily, the voltage reference source can be configured in advance. When the system operates normally, the low voltage detection module 101 keeps running, and the reference source voltage of its internal voltage comparator is configured with a threshold according to application requirements. The low voltage detection module 101 detects the power supply voltage in real time online. When the power supply voltage is lower than the voltage reference source voltage, the voltage comparator flips, triggering the power-off management unit, and the entire system immediately enters the power-off operation mode.

[0033] The power-off detection module of the present invention is implemented by hardware built into the MCU, does not require the participation of software code, and continuously detects the power supply voltage. Compared with the method of using software to control ADC module acquisition and applying for CPU interrupt processing, it saves MCU operating resources, has a fast response speed, and can make full use of the time window of battery decline.

[0034] As an example, Figure 2 As shown, the power-off management module 102 is also connected to the low-power oscillator module 105 and the system clock module 106, and the power-off management module 102 is also used for: In response to the power-off signal, a start signal is generated and sent to the low-power oscillator module 105, so that the low-power oscillator module 105 generates a working clock and sends the working clock to the power-off management module 102, the peripheral access control module 103, and the data storage module 104; And / or, in response to the power-off signal, a shutdown signal is generated and sent to the system clock module 106, so that the system clock module 106 shuts down the system clock.

[0035] Exemplarily, after receiving the power-off signal from the low-voltage detection module 101, the power-off management unit quickly puts the MCU into the power-off mode. It can first generate a start signal and send the start signal to the low-power oscillator module 105 to start the low-power oscillator module 105 so that the low-power oscillator module 105 maintains the working clock of the necessary modules in the power-off mode. For example, the low-power oscillator module 105 sends the working clock to the power-off management module 102, the peripheral access control module 103, and the data storage module 104.

[0036] Exemplarily, the power-off management module 102 may then generate a shutdown signal and send the shutdown signal to the system clock module 106, so that the system clock module 106 turns off the system clock, and the CPU is in HALT mode (HALT mode is a low power consumption mode, which consumes less power than the standby mode). The power-off management module 102 of the present invention coordinates other submodules to jointly complete the task of automatic data storage in a low-power minimum system manner.

[0037] Since the time window for power-off detection and data storage is very small and the remaining power is very little, the design of the present invention is based on on-chip hardware implementation. Compared with solutions that require software participation, the power-off detection can be completed faster. After entering the power-off mode, the system clock and CPU are not required to execute complex software algorithms, which saves most of the software processing time, achieves lower power consumption during the processing, and ensures the use of remaining power.

[0038] As an example, the peripheral device access control module 103 is further configured to: control the first external device to be turned off based on the first control signal, and / or control the second external device to enter a power-off mode.

[0039] For example, the first external device can be understood as an external device that needs to be turned off in time, or is unnecessary, or consumes a lot of energy in the power-off mode, and the second external device can be understood as an external device used to ensure basic functions. The external device access control module 103 controls the external devices that need to be turned off in time, or are unnecessary, or consume a lot of energy to be turned off according to the first control signal from the power-off management module 102, and / or controls the external devices used to ensure basic functions to enter the power-off mode.

[0040] The peripheral access control module 103 of the present invention shuts down other external devices except for the peripherals used for basic functions, and can process the remaining tasks with the lowest power consumption, thus ensuring the use of the remaining power.

[0041] As an example, Figure 3 As shown, the data storage module 104 also includes a dedicated multi-channel DMA control unit 401, a memory address offset management unit 402, and a cyclic redundancy correction unit 403. The dedicated multi-channel DMA control unit 401 is connected to the peripheral access control module 103. The dedicated multi-channel DMA control unit 401 is also connected to the memory address offset management unit 402, the cyclic redundancy correction unit 403, the first memory 1, and the second memory 2. The first memory 1 includes multiple first storage areas, and the second memory 2 includes multiple second storage areas. The dedicated multi-channel DMA control unit 401 is configured to respond to the second control signal to store the data in the multiple first storage areas in parallel in the corresponding multiple second storage areas.

[0042] Exemplarily, the peripheral access control module 103 shuts down unnecessary high-energy-consuming peripheral modules in the MCU in a timely manner, controls other peripherals to enter the power-down mode, and manages the working modes of the dedicated multi-channel DMA control unit 401, the memory address offset management unit 402, the cyclic redundancy correction unit 403, the first memory 1, and the second memory 2 together with the power-down management module 102. The peripheral access control module 103 can notify the first memory 1, the memory address offset management unit 402, and the second memory 2 to make synchronous offset settings for the addresses that need to be read and written on both sides of the first memory 1 and the second memory 2, and initialize the data source address, target address, and channel parameters transmitted by the dedicated multi-channel DMA control unit 401.

[0043] Exemplarily, the peripheral access control module 103 generates a second control signal based on the first control signal to the dedicated multi-channel DMA control unit 401, and the dedicated multi-channel DMA control unit 401 responds to the second control signal to store the data in the multiple first storage areas in parallel to the corresponding multiple second storage areas. The first memory 1 can be SRAM, and the second memory 2 can be DFlash. For example, the data in a specific area of ​​the SRAM is automatically moved to the area corresponding to the DFlash.

[0044] The dedicated multi-channel DMA control unit 401 of the present invention can transmit multiple blocks of regional data in parallel in a multi-channel manner, which is more efficient and saves time and power compared to the CPU software reading and writing method.

[0045] The dedicated multi-channel DMA control unit and the memory address offset management unit of the present invention jointly complete the address management of the first memory 1 and the second memory 2, data reading, transmission, storage and verification. Compared with the existing solution, the software completes the complex software process and storage algorithm under the execution of the CPU, which has the advantages of fast time, simple process and high reliability.

[0046] As an example, the memory address offset management unit 402 is connected to the first memory 1 and the second memory 2 , and the memory address offset management unit 402 is configured to determine a synchronization offset address of a data transmission address of the first memory 1 and the second memory 2 .

[0047] Exemplarily, the memory address offset management unit 402 is responsible for determining the synchronization offset management of the data transmission address between the first memory 1 and the second memory 2 .

[0048] For example, considering that there are some applications where power is frequently turned on and off, such as the engine ECU, which needs to be frequently powered off to save data, and the erase and write life of DFlash (second memory 2) is generally within 100,000 times. In order to improve the life and long-term data security, the same sector of DFlash cannot be repeatedly erased and written. After the memory address offset management unit 402 completes a power-off storage of data, it needs to record the offset address of the data storage this time, and then increase the offset address of the second memory 2. In this way, when the power is off and stored next time, the next area is stored, and the life of the second memory is increased in a sequential recycling manner. The memory address offset management unit can automatically increase the address offset of the second memory to avoid frequent erasing of the same sector or area, and increase the life of the second memory and the durability of data storage.

[0049] The memory address offset management unit of the present invention manages the second memory 2 to store in a manner of sequentially utilizing blocks, thereby avoiding frequent erasing of the same area and increasing the life of the second memory 2.

[0050] As an example, the cyclic redundancy correction unit 403 is connected to the first memory 1 , and the cyclic redundancy correction unit 403 is configured to determine a cyclic redundancy correction code of data in the first memory 1 .

[0051] Exemplarily, the cyclic redundancy correction unit 403 may be a hardware device that performs a real-time online CRC (Cyclic Redundancy Check) check on the data to be stored after power failure, so as to protect the integrity and reliability of the data.

[0052] The present invention performs CRC check on the transmitted and stored data in a hardware CRC check mode to ensure the integrity and reliability of the data. Compared with the software check or software-controlled check mode, the performance is better.

[0053] As an example, the dedicated multi-channel DMA control unit 401 is specifically used for: Reading the data to be stored in the first storage area, and obtaining a cyclic redundancy correction code of the data to be stored; The data to be stored and the cyclic redundancy correction code are stored in at least one of the plurality of second storage areas based on the synchronization offset address of the data to be stored.

[0054] Exemplarily, the dedicated multi-channel DMA control unit 401 reads a segment of data to be stored from the first memory 1, which can be called the data to be stored, and uses the built-in cyclic redundancy correction unit 403 to calculate the corresponding CRC code of the data to be stored in real time, and transmits it together with the data to be stored to the second memory 2 for storage. When the data is retrieved in subsequent applications, the integrity and reliability of the stored data are verified by the CRC code. Since the dedicated multi-channel DMA control unit 401 has multiple channels, multiple channels can transmit each segment of data at the same time, greatly improving the transmission speed.

[0055] Exemplarily, in order to ensure the security of data, the same data packet can also be stored in different areas of the second memory 2 in a double backup manner, and the data to be stored and the cyclic redundancy correction code are stored in at least one of the multiple second storage areas. For example, the data packet is stored in two second storage areas in the second memory. When a data check fails, another data can be used for verification and recovery. The second memory 2 is a built-in non-volatile memory that stores necessary data when power is off. When the power is turned on again next time, the application software of the MCU can read the data from the second memory 2. The present invention implements non-volatile storage in the form of hardware integrated DFlash, which has the characteristics of large capacity, small size, low cost, and suitable time performance compared to an off-chip independent chip.

[0056] After completing the automatic data storage, the system ends the task when the external power is completely cut off.

[0057] The present invention integrates multiple hardware functional modules into one module, does not require the participation of software and CPU, simplifies the external interface, has the characteristics of high integration, simple process and fast response, and greatly reduces the complexity brought by software algorithm and chip resource overhead compared with the software implementation method, and realizes automatic storage of power-off data in a faster and more power-saving mode.

[0058] The invention also provides a micro control system.

[0059] As an example, Figure 4 As shown, the micro control system 400 includes the power-off protection circuit 100 as described above.

[0060] The invention also provides a chip.

[0061] As an example, Figure 5 As shown, the chip 500 includes the microcontroller system 400 as described above.

[0062] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of the present invention, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0063] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0064] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0065] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0066] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0067] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0068] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0069] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A power-off protection circuit, characterized in that: The circuit is built into a microcontroller system MCU, and the circuit includes: A low voltage detection module, wherein the low voltage detection module is configured to generate a power-off signal and send the power-off signal to the power-off management module when a low voltage signal of the microcontroller system MCU is detected; a power-off management module, the power-off management module being connected to the low-voltage detection module and the peripheral access control module, the peripheral access control module being connected to the data storage module, the power-off management module being configured to generate a first control signal in response to the power-off signal and send the first control signal to the peripheral access control module, so that the peripheral access control module generates a second control signal based on the first control signal and sends the second control signal to the data storage module; The data storage module comprises a first memory and a second memory, and the data storage module is configured to store the data in the first memory into the second memory in response to the second control signal.

2. The power-off protection circuit according to claim 1, characterized in that: The low voltage detection module includes a voltage comparator, a first input end of the voltage comparator is connected to the power supply voltage of the microcontroller system MCU, a second input end of the voltage comparator is connected to a voltage reference source, and the voltage comparator is configured to generate a power-off signal to the power-off management module when the power supply voltage is less than the voltage reference source voltage.

3. The power-off protection circuit according to claim 1, characterized in that: The power-off management module is also connected to the low-power oscillator module and the system clock module, and the power-off management module is also used for: In response to the power-off signal, generating a start signal and sending the start signal to the low-power oscillator module, so that the low-power oscillator module generates a working clock and sends the working clock to the power-off management module, the peripheral access control module, and the data storage module; And / or, in response to the power-off signal, generating a shutdown signal and sending the shutdown signal to the system clock module, so that the system clock module shuts down the system clock.

4. The power-off protection circuit according to claim 1, characterized in that: The peripheral access control module is also used for: Based on the first control signal, the first external device is controlled to be turned off, and / or the second external device is controlled to enter a power-off mode.

5. The power-off protection circuit according to claim 1, characterized in that: The data storage module also includes a dedicated multi-channel DMA control unit, a memory address offset management unit, and a cyclic redundancy correction unit. The dedicated multi-channel DMA control unit is connected to the peripheral access control module. The dedicated multi-channel DMA control unit is also connected to the memory address offset management unit, the cyclic redundancy correction unit, the first memory, and the second memory. The first memory includes multiple first storage areas, and the second memory includes multiple second storage areas. The dedicated multi-channel DMA control unit is configured to respond to the second control signal to store the data in the multiple first storage areas in parallel into the corresponding multiple second storage areas.

6. The power-off protection circuit according to claim 5, characterized in that: The memory address offset management unit is connected to the first memory and the second memory, and is configured to determine a synchronization offset address of a data transmission address of the first memory and the second memory.

7. The power-off protection circuit according to claim 5, characterized in that: The cyclic redundancy correction unit is connected to the first memory, and is configured to determine a cyclic redundancy correction code of data in the first memory.

8. The power-off protection circuit according to any one of claims 5 to 7, characterized in that: The dedicated multi-channel DMA control unit is specifically used for: Reading the data to be stored in the first storage area, and obtaining a cyclic redundancy correction code of the data to be stored; The data to be stored and the cyclic redundancy correction code are stored in at least one of a plurality of second storage areas based on a synchronization offset address of the data to be stored.

9. A microcontroller system, characterized in that: The microcontrol system includes a power-off protection circuit as described in any one of claims 1-8.

10. A chip, characterized in that: The chip includes the microcontroller system as claimed in claim 9.

Images