Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel includes: a substrate; a plurality of pixel circuit groups on the substrate; each pixel circuit group comprises two pixel circuits, each pixel circuit comprises a first functional element and a second functional element, in the same pixel circuit group, the first functional elements in the two pixel circuits are arranged along a first direction, the second functional elements in the two pixel circuits are arranged along a second direction, and the first direction intersects with the second direction; the multiple first gate lines are arranged in the first direction and extend in the second direction, and the second functional elements in the two pixel circuits in the same pixel circuit group are electrically connected to the same first gate line. According to the technical scheme, the use performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display panels needs to be improved. Summary of the invention

[0004] The present invention provides a display panel and a display device to improve the performance of the display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, the display panel comprising:

[0006] substrate;

[0007] A plurality of pixel circuit groups are disposed on a substrate; each pixel circuit group includes two pixel circuits, each pixel circuit includes a first functional element and a second functional element, and in the same pixel circuit group, the first functional elements in the two pixel circuits are arranged along a first direction, and the second functional elements in the two pixel circuits are arranged along a second direction, and the first direction intersects the second direction;

[0008] A plurality of first gate lines are arranged along a first direction and extend along a second direction, and the second functional elements in two pixel circuits in the same pixel circuit group are electrically connected to the same first gate line.

[0009] Optionally, in two pixel circuit groups arranged and adjacent to each other along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit, the first functional elements in the first pixel circuit and the second pixel circuit are arranged along the first direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the first functional elements in the first pixel circuit and the third pixel circuit are arranged along the second direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the second direction, the second functional element in the second pixel circuit, the second functional element in the first pixel circuit, the second functional element in the third pixel circuit, and the second functional element in the fourth pixel circuit are arranged in sequence along the second direction; or, the second functional element in the first pixel circuit, the second functional element in the second pixel circuit, the second functional element in the fourth pixel circuit, and the second functional element in the third pixel circuit are arranged in sequence along the second direction.

[0010] Optionally, in two pixel circuit groups arranged and adjacent to each other along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit, the first functional elements in the first pixel circuit and the second pixel circuit are arranged along the first direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the first functional elements in the first pixel circuit and the third pixel circuit are arranged along the second direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the second direction, the second functional element in the first pixel circuit, the second functional element in the second pixel circuit, the second functional element in the third pixel circuit, and the second functional element in the fourth pixel circuit are arranged sequentially along the second direction.

[0011] Optionally, the first functional element includes a driving transistor, and the second functional element includes an initialization transistor;

[0012] Optionally, the functions of the second functional elements in different pixel circuits are the same.

[0013] Optionally, the second functional element comprises a first initialization transistor,

[0014] The first initialization transistor is electrically connected to the gate of the driving transistor, or,

[0015] The pixel circuit includes a compensation transistor connected between a first electrode and a gate of the driving transistor, and a first initialization transistor is electrically connected to the first electrode of the driving transistor;

[0016] Optionally, the display panel further includes a plurality of first initialization sub-signal lines arranged along the first direction and extending along the second direction, and the first initialization transistors in two pixel circuits in the same pixel circuit group are electrically connected to the same first initialization sub-signal line;

[0017] The first initialization sub-signal line comprises a first sub-segment and a second sub-segment alternately arranged along its own extension direction, and the first sub-segment and the second sub-segment are arranged in different layers;

[0018] Optionally, the first initialization transistor includes an N-type transistor or a P-type transistor;

[0019] Optionally, the compensation transistor includes an N-type transistor or a P-type transistor.

[0020] Optionally, the display panel further includes a plurality of light emitting elements, and the second functional element includes a second initialization transistor, and the second initialization transistor is electrically connected to the first electrodes of the light emitting elements.

[0021] Optionally, the second functional element includes a third initialization transistor, and the third initialization transistor is electrically connected to the first electrode or the second electrode of the driving transistor.

[0022] Optionally, the display panel further includes a plurality of initialization signal lines arranged along the first direction and extending along the second direction.

[0023] The second functional elements in the two pixel circuits in the same pixel circuit group are electrically connected to the same initialization signal line.

[0024] Optionally, the pixel circuit further includes a third functional element,

[0025] Of the two pixel circuit groups that are arranged adjacent to each other along the first direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a fifth pixel circuit and a sixth pixel circuit, and a first functional element in the first pixel circuit, a first functional element in the second pixel circuit, a first functional element in the fifth pixel circuit, and a first functional element in the sixth pixel circuit are arranged in sequence along the first direction,

[0026] The display panel further includes: a plurality of second gate lines arranged along the first direction and extending along the second direction;

[0027] In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are arranged along the first direction and electrically connected to different second gate lines.

[0028] Optionally, the first functional element comprises a driving transistor,

[0029] One of the second functional element and the third functional element includes a first initialization transistor, the first initialization transistor is electrically connected to the gate of the driving transistor, or the pixel circuit includes a compensation transistor, the compensation transistor is connected between the first electrode and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first electrode of the driving transistor;

[0030] The other of the second functional element and the third functional element includes a second initialization transistor,

[0031] The display panel further includes a plurality of light emitting elements, and the second initialization transistor is electrically connected to the first electrodes of the light emitting elements;

[0032] Optionally, the pixel circuit further includes a third initialization transistor, and a first electrode of the third initialization transistor is electrically connected to the first electrode or the second electrode of the driving transistor;

[0033] The display panel further includes a plurality of second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate line;

[0034] Optionally, the second initialization transistor and the third initialization transistor have the same channel type;

[0035] Optionally, the second initialization transistor includes a P-type transistor; and the third initialization transistor includes a P-type transistor.

[0036] Optionally, the display panel further includes a plurality of first initialization sub-signal lines arranged along the first direction and extending along the second direction.

[0037] The second functional elements in the two pixel circuits in the same pixel circuit group are electrically connected to the same first initialization sub-signal line;

[0038] The display panel further includes a plurality of second initialization sub-signal lines arranged along the first direction and extending along the second direction.

[0039] In two pixel circuit groups arranged in the first direction and adjacent to each other, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the same second initialization sub-signal line;

[0040] Optionally, the display panel further includes a plurality of third initialization sub-signal lines arranged along the second direction and extending along the first direction; the third initialization sub-signal lines are electrically connected to the first initialization sub-signal lines;

[0041] The first initialization sub-signal line comprises a first sub-segment and a second sub-segment alternately arranged along its own extension direction, and the first sub-segment and the second sub-segment are arranged in different layers;

[0042] The display panel further includes a plurality of fourth initialization sub-signal lines arranged along the second direction and extending along the first direction; the fourth initialization sub-signal lines are electrically connected to the second initialization sub-signal lines; an orthographic projection of the second sub-segment on the substrate overlaps with an orthographic projection of the fourth initialization sub-signal line on the substrate, and the second sub-segment and the fourth initialization sub-signal line are arranged in different layers;

[0043] Optionally, the first sub-segment, the third initialization sub-signal line, and the fourth initialization sub-signal line are arranged on the same layer, and the second sub-segment and the second initialization sub-signal line are arranged on the same layer;

[0044] Optionally, the first sub-segment and the second sub-segment are connected via a first via hole, and the first sub-segment is connected to the second functional element via a second via hole;

[0045] Optionally, the second via holes corresponding to the second functional elements in two pixel circuits in the same pixel circuit group are located on two opposite sides of the first sub-segment along the first direction.

[0046] Optionally, the display panel further includes a first gate driving circuit, the first gate driving circuit includes a plurality of cascaded first shift registers, the second functional element in the first pixel circuit and the second functional element in the second pixel circuit are electrically connected to an output end of the same first shift register, the second functional element in the fifth pixel circuit and the second functional element in the sixth pixel circuit are electrically connected to an output end of the same first shift register, and the second functional element in the second pixel circuit and the second functional element in the fifth pixel circuit are electrically connected to output ends of different first shift registers;

[0047] Optionally, the display panel also includes a second gate driving circuit, the second gate driving circuit includes a plurality of cascaded second shift registers, the third functional element in the first pixel circuit and the third functional element in the second pixel circuit are electrically connected to the output end of the same second shift register, the third functional element in the fifth pixel circuit and the third functional element in the sixth pixel circuit are electrically connected to the output end of the same second shift register, and the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the output ends of different second shift registers.

[0048] Optionally, the third functional element comprises an initialization transistor,

[0049] In two pixel circuit groups that are arranged in the first direction and are adjacent to each other, an active portion of the third functional element in the second pixel circuit and an active portion of the third functional element in the fifth pixel circuit are connected.

[0050] Optionally, the pixel circuit includes a driving transistor and a third initialization transistor, and a first electrode of the third initialization transistor is electrically connected to the first electrode or the second electrode of the driving transistor;

[0051] The second electrodes of the third initialization transistors in the two pixel circuits in the same pixel circuit group are electrically connected;

[0052] and / or, active portions of third initialization transistors in two pixel circuits in the same pixel circuit group are connected;

[0053] and / or, in two pixel circuit groups arranged in the second direction and adjacent to each other, the second electrodes of the third initialization transistors in the first pixel circuit and the second pixel circuit are connected;

[0054] and / or, in two pixel circuit groups arranged in the second direction and adjacent to each other, active parts of third initialization transistors in the first pixel circuit and the second pixel circuit are connected;

[0055] and / or, in two pixel circuit groups arranged along the second direction and adjacent to each other, the second electrodes of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected;

[0056] and / or, in two pixel circuit groups arranged in the second direction and adjacent to each other, active parts of third initialization transistors in the first pixel circuit and the third pixel circuit are connected;

[0057] And / or, in two pixel circuit groups arranged along the second direction and adjacent to each other, second electrodes of third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit are connected;

[0058] And / or, in two pixel circuit groups arranged along the second direction and adjacent to each other, active portions of third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

[0059] Optionally, the pixel circuit includes an element group, the element group includes a first functional element,

[0060] The component groups in two adjacent pixel circuits arranged along the first direction are arranged in mirror symmetry;

[0061] Optionally, the component groups in two adjacent pixel circuits arranged along the second direction are arranged in mirror symmetry;

[0062] Optionally, two adjacent pixel circuits arranged along the second direction are arranged in a mirror-symmetrical manner;

[0063] Optionally, the first functional element includes a driving transistor, and the element group further includes a data writing transistor, a compensation transistor, a first light emission control transistor, and a second light emission control transistor;

[0064] Optionally, the display panel further includes a plurality of third gate lines arranged along the first direction and extending along the second direction; the gate of the compensation transistor is electrically connected to the third gate line,

[0065] The third gate line to which the compensation transistors in two pixel circuits in the same pixel circuit group are electrically connected is symmetrical with respect to the first gate line;

[0066] Optionally, the display panel further includes a plurality of fourth gate lines arranged along the first direction and extending along the second direction; the gate of the data writing transistor is electrically connected to the fourth gate line,

[0067] A fourth gate line to which the data writing transistors in two pixel circuits in the same pixel circuit group are electrically connected is symmetrical with respect to the first gate line;

[0068] Optionally, the display panel further includes a data line, a first data connection line and a second data connection line, the first data connection line is connected between the second data connection line and the data line, and the data line is connected to the data writing transistor;

[0069] The pixel circuit further includes a third initialization transistor; the display panel further includes a plurality of fifth initialization sub-signal lines; a gate of the third initialization transistor is connected to the second gate line, and a second electrode of the third initialization transistor is electrically connected to the fifth initialization sub-signal line;

[0070] The second gate line, the fifth initialization sub-signal line and the first data connection line extend in the same direction;

[0071] Along the thickness direction of the display panel, the fifth initialization sub-signal line is located between the second gate line and the first data connection line;

[0072] Optionally, the display panel further includes a connecting wire, active parts of data writing transistors in two pixel circuits in the same pixel circuit group are connected to the connecting wire through a third via hole, and the connecting wire is connected to a corresponding data line through the same fourth via hole;

[0073] Optionally, at least partially adjacent two first data link lines are located on two opposite sides of the second initialization sub-signal line along the first direction, and at least partially adjacent two first data link lines are symmetrical about the second initialization sub-signal line.

[0074] Optionally, the pixel circuit includes a driving transistor and a third initialization transistor, and a first electrode of the third initialization transistor is electrically connected to the first electrode or the second electrode of the driving transistor;

[0075] The display panel further includes a plurality of fifth initialization sub-signal lines arranged along the first direction and extending along the second direction; the second electrode of the third initialization transistor is electrically connected to the fifth initialization sub-signal line,

[0076] The display panel further includes a plurality of second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate line, and the orthographic projection of the second gate line on the substrate overlaps with the orthographic projection of the fifth initialization sub-signal line on the substrate;

[0077] Optionally, the display panel further includes a plurality of sixth initialization sub-signal lines arranged along the second direction and extending along the first direction; the sixth initialization sub-signal line is electrically connected to the fifth initialization sub-signal line;

[0078] Optionally, the third initialization transistor includes at least two transistors connected in series.

[0079] Optionally, the pixel circuit includes a driving transistor and a first light emitting control transistor,

[0080] The display panel further includes a first power line, and the first light emitting control transistor is connected between the second electrode of the driving transistor and the first power line.

[0081] The active portion of the first light emission control transistor in the first pixel circuit and the active portion of the first light emission control transistor in the third pixel circuit are connected;

[0082] The active portion of the first light emission control transistor in the second pixel circuit and the active portion of the first light emission control transistor in the fourth pixel circuit are connected;

[0083] Optionally, the display panel further includes a light emitting control line electrically connected to the gate of the first light emitting control transistor;

[0084] The light emission control lines to which the first light emission control transistors in two pixel circuits in the same pixel circuit group are electrically connected are symmetrical with respect to the first gate line.

[0085] According to another aspect of the present invention, there is provided a display panel, the display panel comprising:

[0086] substrate;

[0087] A plurality of pixel circuit groups are located on the substrate; each pixel circuit group includes two pixel circuits, each pixel circuit includes a driving transistor and a third initialization transistor, and a first electrode of the third initialization transistor is electrically connected to a first electrode or a second electrode of the driving transistor;

[0088] Of the two pixel circuit groups arranged and adjacent to each other along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit, driving transistors in the first pixel circuit and the second pixel circuit are arranged along the first direction, driving transistors in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, driving transistors in the first pixel circuit and the third pixel circuit are arranged along the second direction, and driving transistors in the third pixel circuit and the fourth pixel circuit are arranged along the second direction; the first direction intersects the second direction;

[0089] In two pixel circuit groups arranged in the second direction and adjacent to each other, the second electrodes of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected;

[0090] And / or, in two pixel circuit groups arranged along the second direction and adjacent to each other, active portions of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected.

[0091] Optionally, in two pixel circuit groups arranged along the second direction and adjacent to each other, second electrodes of third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit are connected;

[0092] And / or, in two pixel circuit groups arranged along the second direction and adjacent to each other, active portions of third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

[0093] According to another aspect of the present invention, a display device is provided. The display device includes the display panel described in any embodiment of the present invention.

[0094] The technical solution of the embodiment of the present invention can reduce the number of first gate lines in the display panel by arranging the second functional elements in two pixel circuits in the same pixel circuit group along the second direction and electrically connecting them to the same first gate line, thereby improving the transmittance of the display panel and further improving the display effect of the display panel.

[0095] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0097] Figure 1 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention;

[0098] Figure 2 is a schematic diagram of an arrangement of a second functional element provided by an embodiment of the present invention;

[0099] Figure 3 is a schematic diagram of another arrangement of second functional elements provided by an embodiment of the present invention;

[0100] Figure 4A is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0101] Figure 4B is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0102] Figure 5 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0103] Figure 6 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0104] Figure 7 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0105] Figure 8 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0106] Fig. 9 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0107] Fig.10 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0108] Fig.11 is a partial top view of a display panel provided by an embodiment of the present invention;

[0109] Fig.12 is another partial top view of the display panel provided by the embodiment of the present invention;

[0110] Fig.13 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0111] Fig.14 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0112] Fig.15 yes Fig.14 Cross-sectional view along the direction a1-a2;

[0113] Fig.16 yes Fig.12 A schematic diagram of a partial top view structure;

[0114] Fig.17 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention;

[0115] Fig.18 yes Fig.13 Cross-sectional view along the b1-b2 direction;

[0116] Fig.19 is a schematic diagram of the layout structure of the first conductive layer and the first active layer of the display panel provided by an embodiment of the present invention;

[0117] Fig. 20 is a schematic diagram of the layout structure of the second conductive layer of the display panel provided by an embodiment of the present invention;

[0118] Fig.21 It is a schematic diagram of the layout structure of the second conductive layer, the second active layer and the third conductive layer of the display panel provided by an embodiment of the present invention;

[0119] Fig. 22 is a schematic diagram of a layout structure of a fourth conductive layer of a display panel provided by an embodiment of the present invention;

[0120] Fig.23 is a schematic diagram of a layout structure of a fifth conductive layer of a display panel provided by an embodiment of the present invention;

[0121] Fig.24 is a schematic diagram of the layout structure of the sixth conductive layer of the display panel provided by an embodiment of the present invention;

[0122] Fig.25 yes Fig.13 Another cross-sectional view along the b1-b2 direction;

[0123] Fig.26 yes Fig.14 Cross-sectional view along the direction e1-e2;

[0124] Fig. 27 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0125] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0126] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0127] The display panel includes a photosensitive device, which is generally set under the screen. The photosensitive device may include a fingerprint recognition module, a camera, an infrared sensor, and an ambient light detection module. When the pixel density of the display panel is high, the transmittance of the display panel will also be reduced, affecting the photosensitivity of the photosensitive device.

[0128] In view of the above technical problem, an embodiment of the present invention provides a display panel. Figure 1 is a schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention, with reference to Figure 1 , the display panel includes:

[0129] Substrate 100;

[0130] A plurality of pixel circuit groups 200 are disposed on a substrate 100; each pixel circuit group 200 includes two pixel circuits 210, each pixel circuit 210 includes a first functional element 211 and a second functional element 212, and in the same pixel circuit group 200, the first functional elements 211 in the two pixel circuits 210 are arranged along a first direction Y, and the second functional elements 212 in the two pixel circuits 210 are arranged along a second direction X, and the first direction Y intersects with the second direction X, for example, perpendicularly;

[0131] A plurality of first gate lines S1 are arranged along a first direction Y and extend along a second direction X. The second functional elements 212 in two pixel circuits 210 in the same pixel circuit group 200 are electrically connected to the same first gate line S1. For example, the orthographic projections of the second functional elements 212 in two pixel circuits 210 in the same pixel circuit group 200 on the substrate overlap with the orthographic projections of the same first gate line S1 on the substrate.

[0132] Among them, the substrate 100 has the functions of supporting, protecting and buffering. The substrate 100 can be a flexible substrate or a hard substrate, which is not limited in this embodiment. The first direction Y can be a column direction, and the second direction X can be a row direction. In some other embodiments, the first direction Y can also be a row direction, and the second direction X can be a column direction. The pixel circuit 210 can be a 2T1C pixel circuit and its deformation, and the pixel circuit 210 can also be a 7T1C pixel circuit and its deformation, which is not limited here. The display panel can also include a light-emitting element, and the pixel circuit 210 can be connected to the corresponding light-emitting element to provide a driving current for the light-emitting element, so that the light-emitting element responds to the driving current to emit light, so that the display panel displays a picture. Multiple pixel circuit groups 200 can be arranged in an array, for example, multiple pixel circuit groups 200 are arranged along the first direction Y, and multiple pixel circuit groups 200 are arranged along the second direction X.

[0133] Specifically, the first functional element 211 and the second functional element 212 may be transistors in the pixel circuit 210. The second functional element 212 is connected to the first gate line S1, and the first gate line S1 may provide a gate driving signal for the second functional element 212, thereby controlling the second functional element 212 to be turned on or off, that is, controlling the turn-on timing of the second functional element 212, and further controlling the timing of the pixel circuit 210. By arranging the second functional elements 212 in two pixel circuits 210 in the same pixel circuit group 200 along the second direction X and electrically connected to the same first gate line S1, the number of first gate lines S1 in the display panel may be reduced, thereby improving the light transmittance of the display panel, so that the photosensitive device in the display panel may better detect ambient light or perform fingerprint recognition or video recording, etc.

[0134] In the same pixel circuit group 200, the first functional elements 211 in the two pixel circuits 210 are arranged along the first direction Y. In the same pixel circuit group 200, the second functional elements 212 in the two pixel circuits 210 are arranged along the second direction X, which facilitates the connection between the second functional elements 212 and the first gate line S1, reduces the connection wiring, and can further improve the transmittance of the display panel, thereby improving the use effect of the display panel.

[0135] The technical solution of this embodiment can reduce the number of first gate lines in the display panel by arranging the second functional elements in two pixel circuits in the same pixel circuit group along the second direction and electrically connecting them to the same first gate line, thereby improving the transmittance of the display panel and further improving the display effect of the display panel.

[0136] On the basis of the above technical solutions, the arrangement of the second functional elements 212 in different pixel circuits is further described below, but it is not intended to limit the present application.

[0137] Optionally, refer to Figure 1 , in two pixel circuit groups 200 arranged and adjacent to each other along the second direction X, one pixel circuit group 200 includes a first pixel circuit 210A and a second pixel circuit 210B, and the other pixel circuit group 200 includes a third pixel circuit 210C and a fourth pixel circuit 210D, the first functional elements 211 in the first pixel circuit 210A and the second pixel circuit 210B are arranged along the first direction Y, the first functional elements 211 in the third pixel circuit 210C and the fourth pixel circuit 210D are arranged along the first direction Y, the first functional elements 211 in the first pixel circuit 210A and the third pixel circuit 210C are arranged along the second direction X, and the first functional elements 211 in the third pixel circuit 210C and the fourth pixel circuit 210D are arranged along the second direction X. For example, the first functional elements 211 in the two pixel circuits 210 arranged and adjacent to each other along the first direction Y are arranged along the first direction Y and are symmetrically arranged. For example, the first functional elements 211 in the two pixel circuits 210 arranged and adjacent to each other along the second direction X are arranged along the second direction X and are symmetrically arranged. This saves space and simplifies wiring.

[0138] In one embodiment, Figure 1As shown, the second functional element 212 in the second pixel circuit 210B, the second functional element 212 in the first pixel circuit 210A, the second functional element 212 in the third pixel circuit 210C, and the second functional element 212 in the fourth pixel circuit 210D are arranged in sequence along the second direction X. For example, the second functional elements 212 in two adjacent pixel circuits 210 arranged along the second direction X are symmetrically arranged. For example, the second functional elements 212 in the 2n-1 and 2n-row pixel circuits 210 are arranged along the second direction X and connected to the same first gate line S1, reducing the connection wiring, which can further improve the transmittance of the display panel. For example, the orthographic projection of the second functional element 212 in the 2n-1 and 2n-row pixel circuits 210 on the substrate overlaps with the orthographic projection of the same first gate line S1 on the substrate. For example, n is an integer greater than or equal to 1, such as n=1, 2, 3... For example, the row direction is parallel to the second direction, and the column direction is parallel to the first direction. For example, the second functional element 212 in the pixel circuit 210 of the 2nth row and the 2kth column, the second functional element 212 in the pixel circuit 210 of the 2nth-1th row and the 2kth column, the second functional element 212 in the pixel circuit 210 of the 2nth-1th row and the 2kth column, and the second functional element 212 in the pixel circuit 210 of the 2nth-1th row and the 2kth column are arranged along the second direction X and connected to the same first gate line S1. For example, k is an integer greater than or equal to 1, such as k=1, 2, 3... In another embodiment, Figure 2 is a schematic diagram of an arrangement of a second functional element provided by an embodiment of the present invention. Optionally, refer to Figure 2 , the second functional element 212 in the first pixel circuit 210A, the second functional element 212 in the second pixel circuit 210B, the second functional element 212 in the fourth pixel circuit 210D, and the second functional element 212 in the third pixel circuit 210C are sequentially arranged along the second direction X. For example, the second functional elements 212 in two adjacent pixel circuits 210 arranged along the second direction X are symmetrically arranged. In addition, the second functional element 212 of the first pixel circuit 210A can be closer to other devices in the first pixel circuit 210A, and the second functional element 212 of the second pixel circuit 210B can be closer to other devices in the second pixel circuit 210B, thereby facilitating the wiring design. For example, the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2k-1th column, the second functional element 212 in the pixel circuit 210 in the 2nth row and the 2k-1th column, the second functional element 212 in the pixel circuit 210 in the 2nth row and the 2kth column, and the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2kth column are arranged along the second direction X and are connected to the same first gate line S1.

[0139] In yet another embodiment, Figure 3is another arrangement diagram of the second functional element provided by an embodiment of the present invention. Figure 3 , the second functional element 212 in the first pixel circuit 210A, the second functional element 212 in the second pixel circuit 210B, the second functional element 212 in the third pixel circuit 210C, and the second functional element 212 in the fourth pixel circuit 210D are arranged in sequence along the second direction X. In this way, the second functional elements 212 of the plurality of pixel circuits 210 arranged and adjacent to each other along the second direction X are arranged along the second direction X, which facilitates the connection of the plurality of second functional elements 212 with the first gate line S1, reduces the connection wiring, and can further improve the transmittance of the display panel. For example, the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2k-1th column, the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2kth column, and the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2kth column, are arranged along the second direction X and connected to the same first gate line S1. For example, the second functional element 212 in the pixel circuit 210 in the 2nth row and the 2k-1th column, the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2k-1th column, the second functional element 212 in the pixel circuit 210 in the 2nth row and the 2kth column, and the second functional element 212 in the pixel circuit 210 in the 2n-1th row and the 2kth column are arranged along the second direction X and are connected to the same first gate line S1.

[0140] On the basis of the above technical solutions, the devices that may be included in the pixel circuit 210 are described below, but this is not intended to limit the present application.

[0141] Optionally, the first functional element 211 includes a driving transistor T1, and the second functional element 212 includes an initialization transistor. For example, the functions of the second functional elements 212 in different pixel circuits 210 are the same. The driving transistor T1 can generate a driving current so that the light-emitting element emits light in response to the driving current. The initialization transistor can be initialized, for example, the gate of the driving transistor T1 or the first electrode of the light-emitting element can be initialized, and other electrodes of the driving transistor T1 can also be initialized, for example, the first electrode or the second electrode of the driving transistor T1 can be initialized, and residual charges can be cleared so that the light-emitting element can emit light better.

[0142] On the basis of the above technical solution, the transistors that may be included in the second functional element 212 are described below, but this is not intended to limit the present application.

[0143] In some embodiments, the second functional element 212 includes a first initialization transistor T2 .

[0144] In one embodiment, Figure 4A is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 4A , the first initialization transistor T2 is electrically connected to the gate of the driving transistor T1. In this way, the first initialization transistor T2 can initialize the gate of the driving transistor T1, so as to prevent the residual charge of the gate of the driving transistor T1 from affecting the driving current generated by the driving transistor T1, so that the light-emitting element can better respond to the driving current to emit light.

[0145] In another embodiment, Figure 4B is a schematic diagram of a structure of another pixel circuit provided by an embodiment of the present invention. Figure 4B The pixel circuit 210 includes a compensation transistor T3 connected between the first electrode and the gate of the driving transistor T1 , and the first initialization transistor T2 is electrically connected to the first electrode of the driving transistor T1 .

[0146] Among them, the compensation transistor T3 can transmit the voltage related to the threshold voltage and data voltage of the driving transistor T1 to the gate of the driving transistor T1, so that the driving current generated by the driving transistor T1 is independent of the threshold voltage of the driving transistor T1, so that the change of the threshold voltage of the driving transistor T1 will not affect the driving current generated by the driving transistor T1, thereby ensuring the stability of the driving current, thereby improving the stability of the light emission of the light-emitting element.

[0147] Specifically, the compensation transistor T3 is connected between the first electrode of the driving transistor T1 and the gate of the driving transistor T1. When the compensation transistor T3 and the first initialization transistor T2 are turned on, the first initialization transistor T2 can transmit the first initialization voltage to the gate of the driving transistor T1 through the compensation transistor T3, thereby initializing the gate of the driving transistor T1.

[0148] Figure 5 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. Figure 5 The display panel further includes a plurality of first initialization sub-signal lines Vref1 arranged along the first direction Y and extending along the second direction X.

[0149] The first initialization transistors T2 in the two pixel circuits 210 in the same pixel circuit group 200 are electrically connected to the same first initialization sub-signal line Vref1 ;

[0150] The first initialization sub-signal line Vref1 includes first sub-segments V11 and second sub-segments V12 alternately arranged along its extension direction, and the first sub-segments V11 and the second sub-segments V12 are arranged in different layers.

[0151] Specifically, the first initialization sub-signal line Vref1 can provide the first initialization voltage for the first initialization transistor T2, so that the first initialization transistor T2 can transmit the first initialization voltage on the first initialization sub-signal line Vref1 to the gate of the driving transistor T1 when it is turned on, and initialize the gate of the driving transistor T1. By setting the first initialization sub-signal line Vref1 to include a first sub-segment V11 and a second sub-segment V12 of different layers, the first initialization sub-signal line Vref1 can be jumpered when encountering other signal lines to avoid overlapping with other signal lines, thereby avoiding short circuit or crosstalk of the signal, and ensuring the reliability and accuracy of signal transmission.

[0152] Optionally, the first initialization transistor T2 includes an N-type transistor or a P-type transistor.

[0153] Specifically, when the first initialization transistor T2 is an N-type transistor, the gate leakage current of the driving transistor T1 can be reduced, thereby ensuring the stability of the driving current of the driving transistor T1. When the first initialization transistor T2 is a P-type transistor, the cost can be reduced and the size of the pixel circuit 210 can be reduced. Figure 4A , Figure 4B and Figure 5 FIG. 5 shows a case where the first initialization transistor T2 is an N-type transistor, but this is not limited thereto.

[0154] Optionally, the compensation transistor T3 includes an N-type transistor or a P-type transistor.

[0155] Specifically, when the compensation transistor T3 is an N-type transistor, the leakage current of the gate of the driving transistor T1 can be reduced, thereby ensuring the stability of the driving current of the driving transistor T1. When the compensation transistor T3 is a P-type transistor, the cost can be reduced and the volume of the pixel circuit 210 can be reduced. Figure 4A , Figure 4B and Figure 5 2 shows a case where the compensation transistor T3 is an N-type transistor, but this is not limiting.

[0156] In some embodiments, Figure 6 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. Figure 6, the display panel also includes a plurality of light-emitting elements D1, and the second functional element 212 includes a second initialization transistor T4, and the second initialization transistor T4 is electrically connected to the first electrode of the light-emitting element D1. The second initialization transistor T4 can initialize the first electrode of the light-emitting element D1. Among them, the first electrode of the light-emitting element D1 can be an anode, and the second electrode of the light-emitting element D1 can be a cathode; or, the first electrode of the light-emitting element D1 can be a cathode, and the second electrode of the light-emitting element D1 can be an anode. The second functional element 212 includes the second initialization transistor T4, and the element groups of the same pixel circuit group 200 can be symmetrically arranged about the first gate line S1 corresponding to the second initialization transistor T4, which is convenient for routing design.

[0157] like Figure 6 As shown, the pixel circuit may further include a data writing transistor T6, a first light emission control transistor T7 and a second light emission control transistor T8, and the first light emission control transistor T7 and the second light emission control transistor T8 are connected to the light emission control line EM. Figure 6 The connection relationship of transistors in the pixel circuit is not limited. Figure 6 As shown, the pixel circuit may further include a third functional element 213. When the second functional element 212 includes a second initialization transistor T4, the third functional element 213 may include a first initialization transistor T2. The third functional element 213 is connected to the second gate line S2. The compensation transistor T3 is connected to the third gate line S3, and the data writing transistor T6 is connected to the fourth gate line S4. The third gate line S3 and the fourth gate line S4 may be the same gate line.

[0158] In some embodiments, Figure 7 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. Figure 7 , the second functional element 212 includes a third initialization transistor T5, and the third initialization transistor T5 is electrically connected to the first electrode or the second electrode of the driving transistor T1. The third initialization transistor T5 can initialize the first electrode or the second electrode of the driving transistor T1. Among them, the first electrode of the driving transistor T1 is the source electrode, and the second electrode of the driving transistor T1 is the drain electrode; or, the first electrode of the driving transistor T1 is the drain electrode, and the second electrode of the driving transistor T1 is the source electrode. The second functional element 212 includes the third initialization transistor T5, and the element groups of the same pixel circuit group 200 can be symmetrically arranged about the first gate line S1 corresponding to the third initialization transistor T5, which is convenient for routing design.

[0159] like Figure 7 As shown, the pixel circuit 210 may further include a data writing transistor T6, a first light emission control transistor T7 and a second light emission control transistor T8, and the first light emission control transistor T7 and the second light emission control transistor T8 are connected to the light emission control line EM. Figure 7 The connection relationship of transistors in the pixel circuit is not limited. Figure 7 As shown, the pixel circuit 210 may further include a third functional element 213. When the second functional element 212 includes a third initialization transistor T5, the third functional element 213 may include a first initialization transistor T2. The third functional element 213 is connected to the second gate line S2. The compensation transistor T3 is connected to the third gate line S3, and the data writing transistor T6 is connected to the fourth gate line S4.

[0160] In some other embodiments, Figure 7 As shown, the second functional element 212 may also include a second initialization transistor T4.

[0161] like Figure 4A As shown, the third initialization transistor T5 is connected to the second electrode of the driving transistor T1. Figure 4B As shown, the third initialization transistor T5 is connected to the first electrode of the driving transistor T1.

[0162] On the basis of the above technical solutions, optionally, the display panel further includes a plurality of initialization signal lines, which are arranged along the first direction Y and extend along the second direction X, and the second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 are electrically connected to the same initialization signal line. For example, the orthographic projections of the second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 on the substrate overlap with the orthographic projections of the same initialization signal line electrically connected thereto on the substrate. For example, the orthographic projections of the gate lines connected to the second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 on the substrate overlap with the orthographic projections of the same initialization signal line electrically connected thereto on the substrate.

[0163] Specifically, the initialization signal line may be connected to the first initialization transistor T2, the second initialization transistor T4, or the third initialization transistor T5. Figure 5 As shown, the initialization signal line is the first initialization sub-signal line Vref1, which can provide the first initialization voltage for the first initialization transistor T2. By setting the second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 to be electrically connected to the same initialization signal line, the number of initialization signal lines can be reduced, which is beneficial to improving the transmittance of the display panel, and further improving the use effect of the display panel. For example Figure 3 As shown, the first pixel circuit 210A and the second pixel circuit 210B share the same first initialization sub-signal line Vref1 , so that the number of first initialization sub-signal lines Vref1 is small.

[0164] On the basis of the above technical solutions, the structure that the pixel circuit 210 may further include is described below, but it is not intended to limit the present application.

[0165] Figure 8 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. Figure 8 The pixel circuit 210 also includes a third functional element 213. In two adjacent pixel circuit groups 200 arranged along the first direction Y, one pixel circuit group 200 includes a first pixel circuit 210A and a second pixel circuit 210B, and the other pixel circuit group 200 includes a fifth pixel circuit 210E and a sixth pixel circuit 210F. The first functional element 211 in the first pixel circuit 210A, the first functional element 211 in the second pixel circuit 210B, the first functional element 211 in the fifth pixel circuit 210E, and the first functional element 211 in the sixth pixel circuit 210F are arranged in sequence along the first direction Y.

[0166] The display panel further includes: a plurality of second gate lines S2 arranged along the first direction Y and extending along the second direction X.

[0167] In two adjacent pixel circuit groups 200 arranged along the first direction Y, the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E are arranged along the first direction Y and electrically connected to different second gate lines S2 .

[0168] Specifically, the third functional element 213 may be a transistor in the pixel circuit 210. The second gate line S2 may provide a gate driving signal for the third functional element 213, thereby controlling the third functional element 213 to be turned on or off, and further controlling the turn-on timing of the third functional element 213, so as to facilitate control of the pixel circuit 210. By arranging the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E along the first direction Y and electrically connecting them to different second gate lines S2, the wiring design may be facilitated.

[0169] On the basis of the above technical solution, optionally, refer to Figure 8 , the first functional element 211 includes a driving transistor T1,

[0170] One of the second functional element 212 and the third functional element 213 includes a first initialization transistor T2, which is electrically connected to the gate of the driving transistor T1, or the pixel circuit 210 includes a compensation transistor T3, which is connected between the first electrode and the gate of the driving transistor T1, and the first initialization transistor T2 is electrically connected to the first electrode of the driving transistor T1;

[0171] The other of the second functional element 212 and the third functional element 213 includes a second initialization transistor T4,

[0172] The display panel further includes a plurality of light emitting elements D1 , and the second initialization transistor T4 is electrically connected to the first electrodes of the light emitting elements D1 .

[0173] Specifically, one of the second functional element 212 and the third functional element 213 includes a first initialization transistor T2, and the other includes a second initialization transistor T4, that is, the two pixel circuits 210 in the same pixel circuit group 200 can be symmetrical about the gate line corresponding to the first initialization transistor T2, or can be symmetrical about the gate line corresponding to the second initialization transistor T4. Then, the gate line corresponding to the first initialization transistor T2 of the two pixel circuits 210 in the same pixel circuit group 200 is shared, or the gate line corresponding to the second initialization transistor T4 is shared.

[0174] Optionally, refer to Figure 8 , the pixel circuit 210 further includes a third initialization transistor T5, a first electrode of the third initialization transistor T5 is electrically connected to the first electrode or the second electrode of the driving transistor T1;

[0175] The display panel further includes a plurality of second gate lines S2 arranged along the first direction Y and extending along the second direction X; the gate of the third initialization transistor T5 is electrically connected to the second gate line S2.

[0176] Specifically, the third initialization transistor T5 can initialize the first electrode or the second electrode of the driving transistor T1, thereby eliminating the residual charge of the first electrode or the second electrode of the driving transistor T1, so that the driving transistor T1 can better generate the driving current. And the bias state of the driving transistor T1 can be adjusted to improve the characteristics of the driving transistor T1, so that the driving transistor T1 can stably generate the driving current.

[0177] Optionally, the second initialization transistor T4 and the third initialization transistor T5 have the same channel type. Thus, when the second functional element 212 includes the first initialization transistor T2 and the third functional element 213 includes the second initialization transistor T4, that is, when the two pixel circuits 210 in the same pixel circuit group 200 can be symmetrical about the gate line corresponding to the first initialization transistor T2, the second initialization transistor T4 and the third initialization transistor T5 can share the gate line, thereby further reducing the number of gate lines, further improving the transmittance of the display panel, and improving the performance of the display panel.

[0178] Optionally, the second initialization transistor T4 includes a P-type transistor; the third initialization transistor T5 includes a P-type transistor. In this way, the cost can be reduced, and the occupied space of the second initialization transistor T4 and the third initialization transistor T5 can be reduced, thereby improving the transmittance of the display panel. In addition, the second initialization transistor T4 and the third initialization transistor T5 can share a gate line, thereby further reducing the number of gate lines.

[0179] On the basis of the above technical solution, optionally, refer to Figure 8 The display panel further includes a plurality of first initialization sub-signal lines Vref1 arranged along the first direction Y and extending along the second direction X.

[0180] The second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 are electrically connected to the same first initialization sub-signal line Vref1;

[0181] The display panel further includes a plurality of second initialization sub-signal lines Vref2 arranged along the first direction Y and extending along the second direction X.

[0182] In two adjacent pixel circuit groups 200 arranged along the first direction Y, the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E are electrically connected to the same second initialization sub-signal line Vref2 .

[0183] Specifically, the second initialization sub-signal line Vref2 can provide a second initialization voltage for the third functional element 213, so that when the third functional element 213 is turned on, the second initialization voltage can be transmitted to the first pole of the light-emitting element to initialize the first pole of the light-emitting element. By setting the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E to be electrically connected to the same second initialization sub-signal line Vref2, the number of second initialization sub-signal lines Vref2 can be reduced, that is, the number of signal lines in the display panel is further reduced, thereby further improving the transmittance of the display panel. For example, the voltages on the first initialization sub-signal line Vref1 and the second initialization sub-signal line Vref2 are different. For example, the first initialization sub-signal line Vref1 and the second initialization sub-signal line Vref2 are alternately arranged along the first direction Y.

[0184] Optionally, refer to Figure 8 , the display panel further includes a plurality of third initialization sub-signal lines Vref3 arranged along the second direction X and extending along the first direction Y; the third initialization sub-signal line Vref3 is electrically connected to the first initialization sub-signal line Vref1;

[0185] The first initialization sub-signal line Vref1 includes first sub-segments V11 and second sub-segments V12 alternately arranged along its own extension direction, and the first sub-segments V11 and the second sub-segments V12 are arranged in different layers;

[0186] The display panel also includes a plurality of fourth initialization sub-signal lines Vref4, which are arranged along the second direction X and extend along the first direction Y; the fourth initialization sub-signal line Vref4 is electrically connected to the second initialization sub-signal line Vref2; an orthographic projection of the second sub-segment V12 on the substrate 100 overlaps with an orthographic projection of the fourth initialization sub-signal line Vref4 on the substrate 100, and the second sub-segment V12 and the fourth initialization sub-signal line Vref4 are arranged in different layers.

[0187] Specifically, by setting the third initialization sub-signal line Vref3, the third initialization sub-signal line Vref3 can form a mesh structure with the first initialization sub-signal line Vref1, which can reduce the voltage drop on the first initialization sub-signal line Vref1 and avoid large fluctuations in the first initialization voltage on the first initialization sub-signal line Vref1. Similarly, by setting the fourth initialization sub-signal line Vref4, the fourth initialization sub-signal line Vref4 can form a mesh structure with the second initialization sub-signal line Vref2 and avoid large fluctuations in the second initialization voltage on the second initialization sub-signal line Vref2. By setting the first initialization sub-signal line Vref1 to include the first sub-segment V11 and the second sub-segment V12, the second sub-segment V12 and the fourth initialization sub-signal line Vref4 are arranged in different layers, which can avoid the fourth initialization sub-signal line Vref4 from overlapping with the first initialization sub-signal line Vref1 and avoid signal confusion or short circuit.

[0188] It should be noted that the third initialization sub-signal line Vref3 may be located on the left or right side of the fourth initialization sub-signal line Vref4, which is not limited in this embodiment.

[0189] Optionally, refer to Figure 8 The first sub-segment V11, the third initialization sub-signal line Vref3, and the fourth initialization sub-signal line Vref4 are arranged on the same layer, and the second sub-segment V12 and the second initialization sub-signal line Vref2 are arranged on the same layer. In this way, the number of film layers can be reduced, the thickness of the display panel can be reduced, and the thin and light design of the display panel can be facilitated.

[0190] Optionally, refer to Figure 8The first sub-segment V11 and the second sub-segment V12 are connected through the first via hole V01, and the first sub-segment V11 is connected to the second functional element 212 through the second via hole V02. In this way, the first sub-segment V11 and the second sub-segment V12 are connected to form the first initialization sub-signal line Vref1, so that the first sub-segment V11 is connected to the second functional element 212, and the first initialization voltage is provided to the second functional element 212.

[0191] Optionally, the second via holes V02 corresponding to the second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 are located on two opposite sides of the first subsection V11 along the first direction Y. Figure 6 As shown, the second via hole V02 corresponding to the second functional element 212 in the first pixel circuit 210A is located below the second sub-segment V12, and the second via hole V02 corresponding to the second functional element 212 in the second pixel circuit 210B is located above the second sub-segment V12. The two second via holes V02 are located on opposite sides of the first sub-segment V11 along the first direction Y, so that the first initialization sub-signal line Vref1 provides the first initialization voltage for the corresponding second functional element 212.

[0192] On the basis of the above technical solutions, the structure that the display panel may also include is described below, but it is not intended to limit the present application.

[0193] Fig. 9 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig. 9 The display panel also includes a first gate driving circuit 310, the first gate driving circuit 310 includes a plurality of cascaded first shift registers 311, the second functional element 212 in the first pixel circuit 210A and the second functional element 212 in the second pixel circuit 210B are electrically connected to the output terminal Out of the same first shift register 311, the second functional element 212 in the fifth pixel circuit 210E and the second functional element 212 in the sixth pixel circuit 210F are electrically connected to the output terminal Out of the same first shift register 311, and the second functional element 212 in the second pixel circuit 210B and the second functional element 212 in the fifth pixel circuit 210E are electrically connected to the output terminal Out of different first shift registers 311.

[0194] Exemplarily, for example, the first gate drive circuit 310 includes a plurality of first shift registers 311, the input end of the first first shift register 311 is connected to the input voltage SIN, and the input end of the m+1 first shift register 311 is connected to the output end of the m first shift register 311 to achieve a cascade connection. Each first shift register 311 is connected to the first clock signal CLK1 and the second clock signal CLK2, and the first clock signal CLK1 has the same frequency as the second clock signal CLK2, for example, the second clock signal CLK2 is delayed than the first clock signal CLK1, that is, the phases are different, for example, the phases are opposite. The first clock end SCK1 of the m first shift register 311 is connected to the first clock signal CLK1, and the second clock end SCK2 of the m first shift register 311 is connected to the second clock signal CLK2. The first clock end SCK1 of the m+1 first shift register 311 is connected to the second clock signal CLK2, and the second clock end SCK2 of the m+1 first shift register 311 is connected to the first clock signal CLK1. In this way, it is convenient to realize the shift output of the gate driving signal. Wherein, m is an integer greater than or equal to 1.

[0195] Specifically, by setting the second functional element 212 in the first pixel circuit 210A and the second functional element 212 in the second pixel circuit 210B to be electrically connected to the output terminal Out of the same first shift register 311, and the second functional element 212 in the fifth pixel circuit 210E and the second functional element 212 in the sixth pixel circuit 210F to be electrically connected to the output terminal Out of the same first shift register 311, the number of first gate lines S1 and first shift registers 311 can be reduced, thereby further improving the transmittance of the display panel. For example, the output terminal of each first shift register 311 is connected to at least two rows of pixel circuits or 2i rows of pixel circuits. For example, i is an integer greater than or equal to 1.

[0196] Fig.10 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Fig.10 The display panel also includes a second gate driving circuit 320, the second gate driving circuit 320 includes a plurality of cascaded second shift registers 321, the third functional element 213 in the first pixel circuit 210A and the third functional element 213 in the second pixel circuit 210B are electrically connected to the output terminal OUT of the same second shift register 321, the third functional element 213 in the fifth pixel circuit 210E and the third functional element 213 in the sixth pixel circuit 210F are electrically connected to the output terminal of the same second shift register 321, and the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E are electrically connected to the output terminal OUT of different second shift registers 321.

[0197] Specifically, for example, the second gate drive circuit 320 includes a plurality of second shift registers 321, the input end of the first second shift register 321 is connected to the input voltage SIN', and the input end of the j+1 second shift register 321 is connected to the output end of the j-th second shift register 321 to achieve a cascade connection. Each second shift register 321 is connected to the third clock signal CLK3 and the fourth clock signal CLK4, and the third clock signal CLK3 and the fourth clock signal CLK4 have the same frequency, for example, the fourth clock signal CLK4 is delayed than the third clock signal CLK3. The first clock end SCK3 of the j-th second shift register 321 is connected to the third clock signal CLK3, and the second clock end SCK4 of the j-th second shift register 321 is connected to the fourth clock signal CLK4. The first clock end SCK3 of the j+1 second shift register 321 is connected to the fourth clock signal CLK4, and the second clock end SCK4 of the j+1 second shift register 321 is connected to the third clock signal CLK3. In this way, it is convenient to realize the shift output of the gate drive signal. For example, j is an integer greater than or equal to 1.

[0198] By setting the third functional element 213 in the first pixel circuit 210A and the third functional element 213 in the second pixel circuit 210B to be electrically connected to the output terminal OUT of the same second shift register 321, and the third functional element 213 in the fifth pixel circuit 210E and the third functional element 213 in the sixth pixel circuit 210F to be electrically connected to the output terminal OUT of the same second shift register 321, the number of second gate lines S2 and second shift registers 321 can be reduced, thereby further improving the transmittance of the display panel. For example, the output terminal of each second shift register 321 is connected to at least two rows of pixel circuits or 2i rows of pixel circuits. For example, i is an integer greater than or equal to 1. For example, the number of pixel circuit rows connected to the output terminal of each second shift register 321 is equal to the number of pixel circuit rows connected to the output terminal of each first shift register 311. For example, the 2i row pixel circuit connected to the output terminal of the w-th stage second shift register 321 and the 2i row pixel circuit connected to the output terminal of the w-th stage first shift register 311 are the same 2i row pixel circuits.

[0199] On the basis of the above technical solutions, optionally, refer to Figure 8The third functional element 213 includes an initialization transistor. In two pixel circuit groups 200 arranged in the first direction Y and adjacent to each other, the active portion T41 of the third functional element 213 in the second pixel circuit 210B and the active portion T41 of the third functional element 213 in the fifth pixel circuit 210E are connected. In this way, the drain or source of the third functional element 213 in the second pixel circuit 210B and the fifth pixel circuit 210E can be shared, so that the third functional element 213 in the second pixel circuit 210B and the fifth pixel circuit 210E are connected to the same initialization signal line, that is, two adjacent third functional elements 213 are connected to the same initialization signal line, and the number of vias used to connect the third functional element 213 to the initialization signal line is reduced, which is conducive to reducing the occupied space of the third functional element 213 and reducing the number of signal lines, thereby better improving the transmittance of the display panel, and / or improving the pixel resolution. For example, at least two third functional elements 213 are connected to the same initialization signal line through the same via.

[0200] On the basis of the above technical solutions, optionally, the pixel circuit 210 includes a driving transistor T1 and a third initialization transistor T5, and a first electrode of the third initialization transistor T5 is electrically connected to a first electrode or a second electrode of the driving transistor T1;

[0201] The second electrodes of the third initialization transistors T5 in the two pixel circuits 210 in the same pixel circuit group 200 are electrically connected; and / or, the active parts of the third initialization transistors T5 in the two pixel circuits 210 in the same pixel circuit group 200 are connected. In this way, the second electrodes of the third initialization transistors T5 in the two pixel circuits 210 in the same pixel circuit group 200 can be shared, which can reduce the occupied space of the third initialization transistors T5, reduce the number of vias used to connect the third initialization transistors T5 to the initialization signal line, and further improve the transmittance of the display panel. For example, at least two third initialization transistors T5 are connected to the same initialization signal line through the same via.

[0202] Optionally, in two pixel circuit groups 200 arranged and adjacent to each other along the second direction X, the second electrodes of the third initialization transistors T5 in the first pixel circuit 210A and the second pixel circuit 210B are connected; and / or, in two pixel circuit groups 200 arranged and adjacent to each other along the second direction X, the active parts of the third initialization transistors T5 in the first pixel circuit 210A and the second pixel circuit 210B are connected. In this way, the second electrodes of the third initialization transistors T5 in the two pixel circuits 210 in each pixel circuit group 200 are shared, which is convenient for layout design and can better improve the transmittance of the display panel.

[0203] Fig.11is a partial top view of a display panel provided by an embodiment of the present invention. Fig.11 , in two pixel circuit groups 200 arranged and adjacent along the second direction X, the second pole T51 of the third initialization transistor T5 in the first pixel circuit 210A and the third pixel circuit 210C is connected; and / or, in two pixel circuit groups 200 arranged and adjacent along the second direction X, the active portion T52 of the third initialization transistor T5 in the first pixel circuit 210A and the third pixel circuit 210C is connected. In this way, the second pole T51 of the third initialization transistor T5 in the first pixel circuit 210A and the third pixel circuit 210C is shared, thereby reducing the occupied space of the third initialization transistor T5, which is conducive to improving the transmittance of the display panel. For example, at least three third initialization transistors T5 are connected to the same initialization signal line through the same via.

[0204] Fig.12 is another partial top view of a display panel provided by an embodiment of the present invention. Fig.12 , in two pixel circuit groups 200 arranged and adjacent along the second direction X, the second poles of the third initialization transistors T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C, and the fourth pixel circuit 210D are connected; and / or, in two pixel circuit groups 200 arranged and adjacent along the second direction X, the active parts of the third initialization transistors T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C, and the fourth pixel circuit 210D are connected. In this way, the second poles of the third initialization transistors T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C, and the fourth pixel circuit 210D can be shared, which can reduce the occupied space of the third initialization transistor T5 and facilitate the wiring design. For example, at least four third initialization transistors T5 are connected to the same initialization signal line through the same via.

[0205] On the basis of the above technical solutions, Fig.13 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. Fig.13 The pixel circuit 210 includes an element group, which includes a first functional element 211. The element groups in two adjacent pixel circuits 210 arranged along the first direction Y are arranged in a mirror-symmetrical manner. That is, the element group is symmetrical about the first gate line S1, which can reduce the number of wirings and facilitate the improvement of the transmittance of the display panel. The element group is a part of the structure in the pixel circuit 210.

[0206] Optionally, refer to Fig.13, the component groups in two adjacent pixel circuits 210 arranged along the second direction X are arranged in mirror symmetry. In this way, some electrodes or wirings in the component groups can be shared, which is convenient for improving the transmittance of the display panel and facilitating wiring design.

[0207] Optionally, refer to Fig.13 , two pixel circuits 210 arranged and adjacent to each other along the second direction X are arranged in mirror symmetry. That is, the entire structure of the two pixel circuits 210 arranged and adjacent to each other along the second direction X can be mirror symmetric, so that some electrodes or wirings of the two pixel circuits 210 arranged and adjacent to each other along the second direction X can be shared, which is convenient for improving the transmittance of the display panel and facilitating wiring design.

[0208] Optionally, refer to Fig.13 , the first functional element 211 includes a driving transistor T1, and the element group further includes a data writing transistor T6, a compensation transistor T3, a first light emission control transistor T7 and a second light emission control transistor T8. Fig.13 As shown, the driving transistor T1 in the first pixel circuit 210A is mirror-symmetric with the driving transistor T1 in the second pixel circuit 210B, the data writing transistor T6 in the first pixel circuit 210A is mirror-symmetric with the data writing transistor T6 in the second pixel circuit 210B, the compensation transistor T3 in the first pixel circuit 210A is mirror-symmetric with the compensation transistor T3 in the second pixel circuit 210B, the first light emission control transistor T7 in the first pixel circuit 210A is mirror-symmetric with the first light emission control transistor T7 in the second pixel circuit 210B, and the second light emission control transistor T8 in the first pixel circuit 210A is mirror-symmetric with the second light emission control transistor T8 in the second pixel circuit 210B. In this way, some electrodes and / or signal lines can be shared, thereby reducing the occupied space of the pixel circuit 210 and improving the transmittance of the display panel.

[0209] Optionally, refer to Fig.13 The display panel further includes a plurality of third gate lines S3 arranged along the first direction Y and extending along the second direction X; the gate of the compensation transistor T3 is electrically connected to the third gate line S3.

[0210] The third gate line S3 electrically connected to the compensation transistors T3 in the two pixel circuits 210 in the same pixel circuit group 200 is symmetrical about the first gate line S1. In this way, it is convenient to connect the compensation transistor T3 to the third gate line S3, and in the two pixel circuits 210 in the same pixel circuit group 200, the corresponding two third gate lines S3 are located on opposite sides of the first gate line S1 along the first direction, and the distances between the corresponding two third gate lines S3 and the first gate line S1 are equal, which can ensure that the gate driving signals received by the compensation transistors T3 in the two pixel circuits 210 in the same pixel circuit group 200 are consistent, which is conducive to improving the accuracy of the timing control of the pixel circuit 210 and facilitating the improvement of the display uniformity of the display panel. For example, the third gate line S3 includes a third sub-segment and a fourth sub-segment alternately arranged along its own extension direction, and the third sub-segment of the third gate line S3 electrically connected to the compensation transistors T3 in the two pixel circuits 210 in the same pixel circuit group 200 is equal to the distance d1 of the first gate line S1, and the fourth sub-segment is equal to the distance d2 of the first gate line S1, and d1 is equal to or not equal to d2, for example, d1 is less than d2.

[0211] Optionally, refer to Fig.13 The display panel further includes a plurality of fourth gate lines S4 arranged along the first direction Y and extending along the second direction X; the gate of the data writing transistor T6 is electrically connected to the fourth gate line S4,

[0212] The fourth gate line S4 electrically connected to the data writing transistor T6 in the two pixel circuits 210 in the same pixel circuit group 200 is symmetrical about the first gate line S1. In this way, it is convenient for the data writing transistor T6 to be connected to the fourth gate line S4, and in the two pixel circuits 210 in the same pixel circuit group 200, the corresponding two fourth gate lines S4 are located on opposite sides of the first gate line S1 along the first direction, and the distances between the corresponding two fourth gate lines S4 and the first gate line S1 are equal, which can ensure that the gate driving signals received by the data writing transistors T6 in the two pixel circuits 210 in the same pixel circuit group 200 are consistent, which is conducive to improving the accuracy of the timing control of the pixel circuit 210 and facilitating the improvement of the display uniformity of the display panel. For example, the fourth gate line S4 includes a fifth subsegment and a sixth subsegment alternately arranged along its own extension direction, and the fifth subsegment of the fourth gate line S4 electrically connected to the compensation transistors T3 in the two pixel circuits 210 in the same pixel circuit group 200 is equal to the distance d3 of the first gate line S1, and the sixth subsegment is equal to the distance d4 of the first gate line S1, and d3 is equal to or not equal to d4, for example, d3 is less than d4.

[0213] Fig.14 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention, Fig.15 yes Fig.14A cross-sectional view along the direction a1-a2, optionally, referring to Fig.14 and Fig.15 The display panel further includes a data line Data, a first data connection line F1 and a second data connection line F2, the first data connection line F1 is connected between the second data connection line F2 and the data line Data, and the data line Data is connected to the data writing transistor T4;

[0214] The pixel circuit 210 further includes a third initialization transistor T5; the display panel further includes a plurality of fifth initialization sub-signal lines Vref5; the gate of the third initialization transistor T5 is connected to the second gate line S2, and the second electrode of the third initialization transistor T5 is electrically connected to the fifth initialization sub-signal line Vref5;

[0215] The second gate line S2, the fifth initialization sub-signal line Vref5 and the first data connection line F1 extend in the same direction;

[0216] The fifth initialization sub-signal line Vref5 is located between the second gate line S2 and the first data connection line F1 along the thickness direction Z of the display panel. For example, the overlapping area of ​​the orthographic projection of the second gate line S2 on the substrate and the orthographic projection of the first data connection line F1 on the substrate 100 overlaps with the orthographic projection of the fifth initialization sub-signal line Vref5 on the substrate 100. For example, at least partially adjacent two first data connection lines F1 are located on opposite sides of the second initialization sub-signal line Vref2 along the first direction Y, for example, at least partially adjacent two first data connection lines F1 are symmetrical about the second initialization sub-signal line Vref2, so as to reduce or shield the signal interference between adjacent first data connection lines F1 through the second initialization sub-signal line Vref2.

[0217] Specifically, by setting the first data connection line F1 and the second data connection line F2 in the display area of ​​the display panel, the driving voltage output by the corresponding driving chip can be transmitted to the data line Data through the first data connection line F1 and the second data connection line F2, so that there is no need to set too many fan-shaped wirings in the non-display area or the frame area, and the size of the frame of the display panel can be reduced, which is convenient for realizing a narrow frame. By setting the fifth initialization sub-signal line Vref5 between the second gate line S2 and the first data connection line F1 along the thickness direction of the display panel, the voltage on the fifth initialization sub-signal line Vref5 is a DC voltage or a power supply voltage, and will not fluctuate, so that a shielding effect can be achieved, avoiding the gate driving signal on the second gate line S2 and the data voltage on the first data connection line F1 from interfering with each other, making the signals on the second gate line S2 and the first data connection line F1 more stable, thereby improving the stability and accuracy of the driving current generated by the pixel circuit 210, which is conducive to improving the display effect of the display panel.

[0218] Alternatively, if Fig.14 As shown, the display panel further includes a connecting line L1. In the same pixel circuit group 200, the active parts of the data writing transistors T6 in two pixel circuits (for example, the data writing transistors T6 in the first pixel circuit 210A and the data writing transistors T6 in the second pixel circuit 210B arranged along the first direction Y and adjacent to each other) are connected to the connecting line L1 through the third via hole V3, and the connecting line L1 is connected to the corresponding data line Data through the same fourth via hole V4. In this way, the number of via holes can be reduced, the transmittance of the display panel is improved, and the performance of the display panel is further improved. The second sub-segment V12 and the connecting line L1 can be arranged in the same layer.

[0219] Among them, Fig.15 As shown, the display panel further includes a first active layer 101, and the first active layer 101 may include an active portion of the driving transistor T1. The display panel further includes a first conductive layer M1.

[0220] On the basis of the above technical solutions, optionally, refer to Figure 4A , Figure 4B and Fig.13 , the pixel circuit 210 includes a driving transistor T1 and a third initialization transistor T5, and a first electrode of the third initialization transistor T5 is electrically connected to a first electrode or a second electrode of the driving transistor T1;

[0221] The display panel further includes a plurality of fifth initialization sub-signal lines Vref5 arranged along the first direction Y and extending along the second direction X; the second electrode of the third initialization transistor T5 is electrically connected to the fifth initialization sub-signal line Vref5,

[0222] The display panel also includes a plurality of second gate lines S2, which are arranged along the first direction Y and extend along the second direction X; the gate of the third initialization transistor T5 is electrically connected to the second gate line S2, and the orthographic projection of the second gate line S2 on the substrate 100 overlaps with the orthographic projection of the fifth initialization sub-signal line Vref5 on the substrate. In this way, it is convenient for the third initialization transistor T5 to be connected to the second gate line S2 and the fifth initialization sub-signal line Vref5 respectively, and the fifth initialization sub-signal line Vref5 can shield the interference of the signal line on the side of the fifth initialization sub-signal line Vref5 away from the substrate 100 to the second gate line S2, so that the fluctuation of the gate drive signal on the second gate line S2 is small, thereby improving the stability of the operation of the pixel circuit 210. For example, the voltage magnitudes of the fifth initialization sub-signal line Vref5 and the first initialization sub-signal line Vref1 are different. For example, the fifth initialization sub-signal line Vref5 and the first initialization sub-signal line Vref1 are alternately arranged along the first direction Y. For example, the voltage magnitudes of the fifth initialization sub-signal line Vref5 and the second initialization sub-signal line Vref2 are different. For example, the fifth initialization sub-signal line Vref5 and the second initialization sub-signal line Vref2 are alternately arranged along the first direction Y. The fifth initialization sub-signal line Vref5 and the second sub-segment V12 may be disposed in the same layer.

[0223] Optionally, refer to Figure 8 The display panel further includes a plurality of sixth initialization sub-signal lines Vref6 arranged along the second direction X and extending along the first direction Y; the sixth initialization sub-signal line Vref6 is electrically connected to the fifth initialization sub-signal line Vref5. In this way, the sixth initialization sub-signal line Vref6 and the fifth initialization sub-signal line Vref5 form a mesh structure, which is convenient for reducing the voltage drop on the fifth initialization sub-signal line Vref5, thereby improving the accuracy of signal transmission on the fifth initialization sub-signal line Vref5.

[0224] Fig.16 yes Fig.12 Schematic diagram of the partial top view structure, refer to Fig.16 , the third initialization transistor T5 includes at least two transistors connected in series. Fig.16As shown, the portion where the second gate line S2 overlaps with the first active layer 101 is the gate of the third initialization transistor T5. The third initialization transistor T5 includes a first sub-transistor T5-1 and a second sub-transistor T5-2, so that the third initialization transistor T5 is a dual-gate transistor, which can reduce the leakage current of the driving transistor T1, thereby ensuring the stability of the driving current generated by the driving transistor T1. For example, the sixth initialization sub-signal line Vref6 and the third initialization sub-signal line Vref3 are alternately arranged along the second direction X. For example, the sixth initialization sub-signal line Vref6 and the fourth initialization sub-signal line Vref4 are alternately arranged along the second direction X. The sixth initialization sub-signal line Vref6 and the third initialization sub-signal line Vref3 can be arranged in the same layer.

[0225] On the basis of the above technical solutions, Fig.17 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. Figure 4A , Figure 4B and Fig.17 The pixel circuit 210 includes a driving transistor T1 and a first light emitting control transistor T7.

[0226] The display panel further includes a first power line VDD, and a first light emitting control transistor T7 is connected between the second electrode of the driving transistor T1 and the first power line VDD.

[0227] like Figure 5 As shown, the active portion T71 of the first light emission control transistor T7 in the first pixel circuit 210A and the active portion of the first light emission control transistor T7 in the third pixel circuit 210C are connected;

[0228] The active portion of the first light emission control transistor T7 in the second pixel circuit 210B and the active portion of the first light emission control transistor T7 in the fourth pixel circuit 210D are connected.

[0229] Specifically, when the first light-emitting control transistor T7 is turned on, the first light-emitting control transistor T7 can transmit the first power supply voltage on the first power supply line VDD to the second electrode of the driving transistor T1, so that the driving transistor T1 can generate a driving current. By setting the active part T71 of the first light-emitting control transistor T7 in the first pixel circuit 210A and the active part T71 of the first light-emitting control transistor T7 in the third pixel circuit 210C to be connected, and the active part of the first light-emitting control transistor T7 in the second pixel circuit 210B and the active part of the first light-emitting control transistor T7 in the fourth pixel circuit 210D to be connected, it is convenient to design the wiring, reduce the number of vias, and facilitate the first power supply line VDD to be connected to the two first light-emitting control transistors T7 through one via, so as to realize the via sharing, which is conducive to further improving the transmittance of the display panel.

[0230] Optionally, refer to Figure 4A , Figure 4B and Fig.17 , the display panel further includes a light emitting control line EM electrically connected to the gate of the first light emitting control transistor T7;

[0231] The light emitting control lines EM electrically connected to the first light emitting control transistors T7 in the two pixel circuits 210 in the same pixel circuit group 200 are symmetrical about the first gate line S1. In this way, it is convenient to connect the first light emitting control transistor T7 to the light emitting control line EM, and in the two pixel circuits 210 in the same pixel circuit group 200, the corresponding two light emitting control lines EM are located on opposite sides of the first gate line S1 along the first direction, and the distances between the corresponding two light emitting control lines EM and the first gate line S1 are equal, which can ensure that the gate driving signals received by the first light emitting control transistors T7 in the two pixel circuits 210 in the same pixel circuit group 200 are consistent, which is conducive to improving the accuracy of the timing control of the pixel circuit 210 and facilitating the improvement of the display uniformity of the display panel.

[0232] The structure of the display panel is further described below in conjunction with a schematic diagram of the layout structure of each film layer of the display panel and a cross-sectional view of the display panel, but this does not limit the present application.

[0233] Optionally, the display panel includes one or more of a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4 and a fifth conductive layer M5 which are stacked on the substrate 100, and the display panel also includes one or more of a first active layer 101 and a second active layer 102. The pixel circuit 210 also includes a storage capacitor C1, a first end of the storage capacitor C1 is connected to a first power line VDD, and a second end of the storage capacitor C1 is connected to a gate of the driving transistor T1. For example, any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4 and the fifth conductive layer M5 may include a metal layer or a light-transmitting conductive layer (such as indium tin oxide ITO). An insulating layer may be provided between adjacent conductive layers. An insulating layer may be provided between adjacent conductive layers and the active layer. The active portion may be located in the active layer.

[0234] Fig.18 yes Fig.13 Cross-sectional view along the b1-b2 direction, Fig.19 is a schematic diagram of the layout structure of the first conductive layer and the first active layer of the display panel provided in an embodiment of the present invention. Optionally, refer to Fig.18 and Fig.19 , the light emitting control line EM, the second gate line S2 and the fourth gate line S4 are located in the first conductive layer M1, and the first plate C01 of the storage capacitor C1 is located in the first conductive layer M1, and the first plate C01 is multiplexed as the gate of the driving transistor T1. Fig.18 As shown, the gate T11 of the driving transistor T1 is located in the first conductive layer M1. The active portion of the driving transistor T1 is located in the first active layer 101. The first electrode T12 and the second electrode T13 of the driving transistor T1 are located in the fourth conductive layer M4. For example, the first active layer 101 may include polysilicon semiconductor material.

[0235] Fig. 20 is a schematic diagram of the layout structure of the second conductive layer of the display panel provided in an embodiment of the present invention. Optionally, refer to Fig. 20 , the first gate line S1, the third gate line S3 and the second electrode C02 of the storage capacitor C1 are located in the second conductive layer M2. Two third gate lines S3 arranged and adjacent to each other along the first direction Y are mirror-symmetrical about the first gate line S1, so that two pixel circuits 210 arranged and adjacent to each other along the first direction Y can share one first gate line S1, reducing the number of first gate lines S1, thereby improving the transmittance of the display panel. Fig.18 As shown, the first gate line S1 and the third gate line S3 are located in the first conductive layer M1. The portion where the first gate line S1 overlaps with the second active layer 102 forms the first gate T21 of the first initialization transistor T2, and the portion where the third gate line S3 overlaps with the second active layer 102 forms the first gate T31 of the compensation transistor T3. For example, the second active layer 102 may include a metal oxide semiconductor material, such as indium gallium zinc oxide IGZO.

[0236] Fig.21 is a schematic diagram of the layout structure of the second conductive layer, the second active layer and the third conductive layer of the display panel provided in an embodiment of the present invention. Optionally, refer to Fig.18 and Fig.21 , the portion where the first gate line S1 overlaps with the second active layer 102 is the first gate T21 of the first initialization transistor T2, and the portion where the gate line S12 in the third conductive layer M3 overlaps with the second active layer 102 and the first gate line S1 is the second gate T22 of the first initialization transistor T2. The portion where the third gate line S3 overlaps with the second active layer 102 is the first gate T31 of the compensation transistor T3, and the portion where the gate line S32 in the third conductive layer M3 overlaps with the second active layer 102 and the third gate line S3 is the second gate T32 of the compensation transistor T3. In this way, the compensation transistor T3 and the first initialization transistor T2 are N-type transistors, which can reduce the leakage current of the driving transistor T1. And the first initialization transistors T2 in two pixel circuits arranged along the first direction Y and adjacent to each other are arranged along the second direction X, which is convenient for connection with the first gate line S1 and the compensation transistor T3. Fig.18 As shown, the first electrode T23 and the second electrode T24 of the first initialization transistor T2 are located in the fourth conductive layer M4, and the first electrode T33 and the second electrode T34 of the compensation transistor T3 are located in the fourth conductive layer M4.

[0237] Fig. 22 is a schematic diagram of a layout structure of a fourth conductive layer of a display panel provided by an embodiment of the present invention. Optionally, refer to Fig. 22 , the first sub-segment V11 of the first initialization sub-signal line Vref1, the third initialization sub-signal line Vref3, the fourth initialization sub-signal line Vref4 and the sixth initialization sub-signal line Vref6 are located in the fourth conductive layer M4. By setting the first initialization sub-signal line Vref1 to include the first sub-segment V11, the first sub-segment V11 and the fourth initialization sub-signal line Vref4 do not overlap, so that interference or short circuit between the signal on the first initialization sub-signal line Vref1 and the signal on the fourth initialization sub-signal line Vref4 can be avoided, thereby ensuring the reliability of signal transmission.

[0238] Fig.23 is a schematic diagram of a layout structure of a fifth conductive layer of a display panel provided by an embodiment of the present invention. Optionally, refer to Fig.23 , the first data link line F1 and the second sub-segment V12 of the first initialization sub-signal line Vref1 are located in the fifth conductive layer M5.

[0239] Fig.24 is a schematic diagram of the layout structure of the sixth conductive layer of the display panel provided in an embodiment of the present invention. Optionally, refer to Fig.24 , the first power line VDD, the second data link line F2 and the data line Data are located in the sixth conductive layer M6.

[0240] In some embodiments, Fig.25 yes Fig.13 Another cross-sectional view along the b1-b2 direction, optionally, refer to Fig.23 The display panel may further include a shielding layer M0, which is located on the side of the first active layer 101 close to the substrate 100, that is, the shielding layer M0 is located between the substrate 100 and the pixel circuit 210, and the orthographic projection of the shielding layer M0 on the substrate 100 overlaps at least part of the active part of the driving transistor T1. In this way, the shielding portion M0 can play the role of electrostatic shielding for the driving transistor T1, avoid the influence of static electricity on the characteristics of the driving transistor T1, avoid the change of the threshold voltage of the driving transistor T1, thereby ensuring the stability of the driving current of the driving transistor T1. In addition, it can prevent static electricity from damaging the gate of the driving transistor T1, thereby protecting the driving transistor T1. The shielding layer M0 may be a light shielding layer.

[0241] In some embodiments, the shielding layer M0 may further include a portion overlapping with an active portion of other transistors (eg, a data writing transistor, etc.) to achieve the effect of protecting other transistors (eg, a data writing transistor, etc.).

[0242] Fig.26 yes Fig.14 A cross-sectional view along the direction e1-e2, optionally, referring to Fig.26 , the second data link line F2 and the data line Data are located in the sixth conductive layer M6.

[0243] On the basis of the above technical solutions, optionally, refer to Figure 4A and Figure 4B , the second electrode of the light emitting element D1 is connected to the second power line VSS.

[0244] It should be noted that the data writing transistor T6 can be an N-type transistor or a P-type transistor, the first light emission control transistor T7 can be an N-type transistor or a P-type transistor, and the second light emission control transistor T8 can be an N-type transistor or a P-type transistor. Figure 4A , Figure 4B 2 shows the case where the data writing transistor T6, the first light emission control transistor T7 and the second light emission control transistor T8 are all P-type transistors, but this is not limited to this.

[0245] Each signal line or routing (eg, gate line, initialization signal line, power line, data line, data connection line, etc.) may extend in a straight line, a folded line, a curve, an irregular shape (eg, a tree-like shape), or a combination of the two or more thereof along its own extension direction.

[0246] An embodiment of the present invention further provides a display panel, the display panel comprising: a substrate 100;

[0247] A plurality of pixel circuit groups 200 are disposed on a substrate 100; each pixel circuit group 200 includes two pixel circuits 210, each pixel circuit 210 includes a driving transistor T1 and a third initialization transistor T5, and a first electrode of the third initialization transistor T5 is electrically connected to a first electrode or a second electrode of the driving transistor T1;

[0248] like Figure 5 and Fig.11 As shown, in two pixel circuit groups 200 arranged and adjacent to each other along the second direction X, one pixel circuit group 200 includes a first pixel circuit 210A and a second pixel circuit 210B, and the other pixel circuit group includes a third pixel circuit 210C and a fourth pixel circuit 210D, the driving transistors T1 in the first pixel circuit 210A and the second pixel circuit 210B are arranged along the first direction Y, the driving transistors T1 in the third pixel circuit 210C and the fourth pixel circuit 210D are arranged along the first direction Y, the driving transistors T1 in the first pixel circuit 210A and the third pixel circuit 210C are arranged along the second direction X, and the driving transistors T1 in the third pixel circuit 210C and the fourth pixel circuit 210D are arranged along the second direction Y;

[0249] In two pixel circuit groups 200 arranged along the second direction X and adjacent to each other, the second electrodes of the third initialization transistors T5 in the first pixel circuit 210A and the third pixel circuit 210C are connected;

[0250] And / or, in two pixel circuit groups 200 arranged along the second direction X and adjacent to each other, active portions of the third initialization transistors T5 in the first pixel circuit 210A and the third pixel circuit 210C are connected.

[0251] On the basis of the above technical solution, optionally, as Fig.12 As shown, in two pixel circuit groups 200 arranged along the second direction X and adjacent to each other, the second electrodes of the third initialization transistors T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C and the fourth pixel circuit 210D are connected;

[0252] And / or, in two adjacent pixel circuit groups 200 arranged along the second direction X, active portions of the third initialization transistors T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C, and the fourth pixel circuit 210D are connected.

[0253] This embodiment can be combined with some or all of the features of the above embodiments, which will not be described in detail here.

[0254] This embodiment also provides a display device, Fig. 27 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig. 27 As shown, the display device includes the display panel provided by any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital camera, etc. The display device includes the display panel provided by any embodiment of the present invention, and thus has the same beneficial effects as the display panel provided by any embodiment of the present invention, which will not be described in detail here.

[0255] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of pixel circuit groups are located on the substrate; each of the pixel circuit groups includes two pixel circuits, each of the pixel circuits includes a first functional element and a second functional element, and in the same pixel circuit group, the first functional elements in the two pixel circuits are arranged along a first direction, and the second functional elements in the two pixel circuits are arranged along a second direction, and the first direction intersects with the second direction; A plurality of first gate lines are arranged along the first direction and extend along the second direction, and the second functional elements in the two pixel circuits in the same pixel circuit group are electrically connected to the same first gate line.

2. The display panel according to claim 1, characterized in that: Of the two pixel circuit groups arranged and adjacent along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit, the first functional elements in the first pixel circuit and the second pixel circuit are arranged along the first direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the first functional elements in the first pixel circuit and the third pixel circuit are arranged along the second direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the second direction, the second functional element in the second pixel circuit, the second functional element in the first pixel circuit, the second functional element in the third pixel circuit, and the second functional element in the fourth pixel circuit are arranged in sequence along the second direction; or, the second functional element in the first pixel circuit, the second functional element in the second pixel circuit, the second functional element in the fourth pixel circuit, and the second functional element in the third pixel circuit are arranged in sequence along the second direction.

3. The display panel according to claim 1, characterized in that: Of the two pixel circuit groups arranged adjacent to each other along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit, the first functional elements in the first pixel circuit and the second pixel circuit are arranged along the first direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the first functional elements in the first pixel circuit and the third pixel circuit are arranged along the second direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the second direction, the second functional elements in the first pixel circuit, the second functional elements in the second pixel circuit, the second functional elements in the third pixel circuit, and the second functional elements in the fourth pixel circuit are arranged in sequence along the second direction.

4. The display panel according to claim 1, characterized in that: The first functional element comprises a driving transistor, and the second functional element comprises an initializing transistor; Preferably, the functions of the second functional elements in different pixel circuits are the same.

5. The display panel according to claim 4, characterized in that: The second functional element comprises a first initialization transistor, The first initialization transistor is electrically connected to the gate of the driving transistor, or, The pixel circuit includes a compensation transistor, the compensation transistor is connected between the first electrode and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first electrode of the driving transistor; Preferably, the display panel further includes a plurality of first initialization sub-signal lines arranged along the first direction and extending along the second direction. The first initialization transistors in the two pixel circuits in the same pixel circuit group are electrically connected to the same first initialization sub-signal line; The first initialization sub-signal line comprises a first sub-segment and a second sub-segment alternately arranged along its own extension direction, and the first sub-segment and the second sub-segment are arranged in different layers; Preferably, the first initialization transistor comprises an N-type transistor or a P-type transistor; Preferably, the compensation transistor includes an N-type transistor or a P-type transistor.

6. The display panel according to claim 4, characterized in that: The display panel further includes a plurality of light emitting elements, and the second functional element includes a second initialization transistor, which is electrically connected to the first electrodes of the light emitting elements.

7. The display panel according to claim 4, characterized in that: The second functional element includes a third initialization transistor, and the third initialization transistor is electrically connected to the first electrode or the second electrode of the driving transistor.

8. The display panel according to claim 4, characterized in that: The display panel further includes a plurality of initialization signal lines arranged along the first direction and extending along the second direction. The second functional elements in the two pixel circuits in the same pixel circuit group are electrically connected to the same initialization signal line.

9. The display panel according to claim 1, characterized in that: The pixel circuit further includes a third functional element, Of the two pixel circuit groups that are arranged adjacent to each other along the first direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a fifth pixel circuit and a sixth pixel circuit, and the first functional element in the first pixel circuit, the first functional element in the second pixel circuit, the first functional element in the fifth pixel circuit, and the first functional element in the sixth pixel circuit are arranged in sequence along the first direction, The display panel further includes: a plurality of second gate lines arranged along the first direction and extending along the second direction; In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are arranged along the first direction and electrically connected to different second gate lines.

10. The display panel according to claim 9, characterized in that: The first functional element includes a driving transistor, One of the second functional element and the third functional element includes a first initialization transistor, the first initialization transistor is electrically connected to the gate of the driving transistor, or the pixel circuit includes a compensation transistor, the compensation transistor is connected between the first electrode and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first electrode of the driving transistor; The other of the second functional element and the third functional element includes a second initialization transistor, The display panel further comprises a plurality of light emitting elements, and the second initialization transistor is electrically connected to the first electrodes of the light emitting elements; Preferably, the pixel circuit further comprises a third initialization transistor, and a first electrode of the third initialization transistor is electrically connected to the first electrode or the second electrode of the driving transistor; The display panel further includes a plurality of second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate line; Preferably, the second initialization transistor and the third initialization transistor have the same channel type; Preferably, the second initialization transistor includes a P-type transistor; and the third initialization transistor includes a P-type transistor.

11. The display panel according to claim 9, characterized in that: The display panel further includes a plurality of first initialization sub-signal lines arranged along the first direction and extending along the second direction. The second functional elements in the two pixel circuits in the same pixel circuit group are electrically connected to the same first initialization sub-signal line; The display panel further includes a plurality of second initialization sub-signal lines arranged along the first direction and extending along the second direction. In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the same second initialization sub-signal line; Preferably, the display panel further comprises a plurality of third initialization sub-signal lines arranged along the second direction and extending along the first direction; the third initialization sub-signal lines are electrically connected to the first initialization sub-signal lines; The first initialization sub-signal line comprises a first sub-segment and a second sub-segment alternately arranged along its own extension direction, and the first sub-segment and the second sub-segment are arranged in different layers; The display panel further includes a plurality of fourth initialization sub-signal lines arranged along the second direction and extending along the first direction; the fourth initialization sub-signal line is electrically connected to the second initialization sub-signal line; an orthographic projection of the second sub-segment on the substrate overlaps with an orthographic projection of the fourth initialization sub-signal line on the substrate, and the second sub-segment and the fourth initialization sub-signal line are arranged in different layers; Preferably, the first sub-segment, the third initialization sub-signal line, and the fourth initialization sub-signal line are arranged on the same layer, and the second sub-segment and the second initialization sub-signal line are arranged on the same layer; Preferably, the first sub-segment and the second sub-segment are connected via a first via hole, and the first sub-segment is connected to the second functional element via a second via hole; Preferably, the second via holes corresponding to the second functional elements in the two pixel circuits in the same pixel circuit group are located on two opposite sides of the first subsegment along the first direction.

12. The display panel according to claim 9, characterized in that: The display panel further includes a first gate driving circuit, the first gate driving circuit includes a plurality of cascaded first shift registers, the second functional element in the first pixel circuit and the second functional element in the second pixel circuit are electrically connected to an output end of the same first shift register, the second functional element in the fifth pixel circuit and the second functional element in the sixth pixel circuit are electrically connected to an output end of the same first shift register, and the second functional element in the second pixel circuit and the second functional element in the fifth pixel circuit are electrically connected to output ends of different first shift registers; Preferably, the display panel also includes a second gate driving circuit, the second gate driving circuit includes a plurality of cascaded second shift registers, the third functional element in the first pixel circuit and the third functional element in the second pixel circuit are electrically connected to the output end of the same second shift register, the third functional element in the fifth pixel circuit and the third functional element in the sixth pixel circuit are electrically connected to the output end of the same second shift register, and the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the output ends of different second shift registers.

13. The display panel according to claim 9, characterized in that: The third functional element includes an initialization transistor, In two adjacent pixel circuit groups arranged along the first direction, an active portion of the third functional element in the second pixel circuit and an active portion of the third functional element in the fifth pixel circuit are connected.

14. The display panel according to claim 2 or 3, characterized in that: The pixel circuit comprises a driving transistor and a third initialization transistor, wherein a first electrode of the third initialization transistor is electrically connected to a first electrode or a second electrode of the driving transistor; The second electrodes of the third initialization transistors in the two pixel circuits in the same pixel circuit group are electrically connected; and / or, active parts of the third initialization transistors in the two pixel circuits in the same pixel circuit group are connected; and / or, in two adjacent pixel circuit groups arranged along the second direction, the second electrodes of the third initialization transistors in the first pixel circuit and the second pixel circuit are connected; and / or, in two adjacent pixel circuit groups arranged along the second direction, active parts of the third initialization transistors in the first pixel circuit and the second pixel circuit are connected; and / or, in two adjacent pixel circuit groups arranged along the second direction, second electrodes of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected; and / or, in two adjacent pixel circuit groups arranged along the second direction, active parts of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the second electrodes of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit and the fourth pixel circuit are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, active portions of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

15. The display panel according to claim 1, characterized in that: The pixel circuit includes an element group, and the element group includes the first functional element. The component groups in two adjacent pixel circuits arranged along the first direction are arranged in mirror symmetry; Preferably, the component groups in two adjacent pixel circuits arranged along the second direction are arranged in mirror symmetry; Preferably, two adjacent pixel circuits arranged along the second direction are arranged in mirror symmetry; Preferably, the first functional element includes a driving transistor, and the element group further includes a data writing transistor, a compensation transistor, a first light emission control transistor and a second light emission control transistor; Preferably, the display panel further comprises a plurality of third gate lines arranged along the first direction and extending along the second direction; the gate of the compensation transistor is electrically connected to the third gate line, The third gate line to which the compensation transistors in the two pixel circuits in the same pixel circuit group are electrically connected is symmetrical with respect to the first gate line; Preferably, the display panel further comprises a plurality of fourth gate lines arranged along the first direction and extending along the second direction; the gate of the data writing transistor is electrically connected to the fourth gate line, The fourth gate line to which the data writing transistors in the two pixel circuits in the same pixel circuit group are electrically connected is symmetrical with respect to the first gate line; Preferably, the display panel further comprises a data line, a first data connection line and a second data connection line, the first data connection line is connected between the second data connection line and the data line, and the data line is connected to the data writing transistor; The pixel circuit further includes a third initialization transistor; the display panel further includes a plurality of fifth initialization sub-signal lines; a gate of the third initialization transistor is connected to the second gate line, and a second electrode of the third initialization transistor is electrically connected to the fifth initialization sub-signal line; The second gate line, the fifth initialization sub-signal line and the first data connection line extend in the same direction; Along the thickness direction of the display panel, the fifth initialization sub-signal line is located between the second gate line and the first data connection line; Preferably, the display panel further comprises a connecting wire, the active parts of the data writing transistors in the two pixel circuits in the same pixel circuit group are connected to the connecting wire through a third via hole, and the connecting wire is connected to the corresponding data line through the same fourth via hole; Preferably, at least partially adjacent two first data link lines are located on two opposite sides of the second initialization sub-signal line along the first direction, and at least partially adjacent two first data link lines are symmetrical about the second initialization sub-signal line.

16. The display panel according to claim 1, characterized in that: The pixel circuit comprises a driving transistor and a third initialization transistor, wherein a first electrode of the third initialization transistor is electrically connected to a first electrode or a second electrode of the driving transistor; The display panel further includes a plurality of fifth initialization sub-signal lines arranged along the first direction and extending along the second direction; the second electrode of the third initialization transistor is electrically connected to the fifth initialization sub-signal line, The display panel further includes a plurality of second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate line, and the orthographic projection of the second gate line on the substrate overlaps with the orthographic projection of the fifth initialization sub-signal line on the substrate; Preferably, the display panel further comprises a plurality of sixth initialization sub-signal lines arranged along the second direction and extending along the first direction; the sixth initialization sub-signal lines are electrically connected to the fifth initialization sub-signal lines; Preferably, the third initialization transistor includes at least two transistors connected in series.

17. The display panel according to claim 2 or 3, characterized in that: The pixel circuit includes a driving transistor and a first light emission control transistor, The display panel further includes a first power line, and the first light emission control transistor is connected between the second electrode of the driving transistor and the first power line. The active portion of the first light emission control transistor in the first pixel circuit and the active portion of the first light emission control transistor in the third pixel circuit are connected; The active portion of the first light emission control transistor in the second pixel circuit and the active portion of the first light emission control transistor in the fourth pixel circuit are connected; Preferably, the display panel further comprises a light emitting control line electrically connected to the gate of the first light emitting control transistor; The light emission control lines to which the first light emission control transistors in the two pixel circuits in the same pixel circuit group are electrically connected are symmetrical with respect to the first gate line.

18. A display panel, characterized in that: include: substrate; A plurality of pixel circuit groups are located on the substrate; each of the pixel circuit groups includes two pixel circuits, each of the pixel circuits includes a driving transistor and a third initialization transistor, and a first electrode of the third initialization transistor is electrically connected to a first electrode or a second electrode of the driving transistor; Of the two pixel circuit groups arranged and adjacent to each other along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit, the driving transistors in the first pixel circuit and the second pixel circuit are arranged along the first direction, the driving transistors in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the driving transistors in the first pixel circuit and the third pixel circuit are arranged along the second direction, and the driving transistors in the third pixel circuit and the fourth pixel circuit are arranged along the second direction; the first direction and the second direction intersect; In two adjacent pixel circuit groups arranged along the second direction, the second electrodes of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, active portions of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected.

19. The display panel according to claim 18, characterized in that: In two adjacent pixel circuit groups arranged along the second direction, second electrodes of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, active portions of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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