Stacking structure and method of multiple associated chips, packaging structure and packaging method

Abstract

The invention discloses a stacking structure and method of a plurality of associated chips, a packaging structure and the like, and the stacking structure comprises a substrate, a plurality of chips stacked on the substrate, mucilage glue used for a bottom chip and the substrate as well as between the upper and lower chips, and electric leads used for connecting the bottom chip and the substrate as well as between the bottom chip and the associated chips, the circuit extension connecting plate is arranged between the upper chip and the lower chip, the circuit extension connecting plate is divided into an external connecting part and an internal connecting part, an extension connecting circuit from the internal connecting part to the external connecting part is at least arranged on the upper surface of the circuit extension connecting plate, the plurality of chips are vertically stacked to form a chip stacking body, the internal connecting part of the circuit extension connecting plate is stacked between two adjacent chips, and the external connecting part of the circuit extension connecting plate is connected with the external connecting part. The external connection part of the circuit extension plate is located outside the chip stacking body, an extension circuit at the internal connection end of the circuit extension plate is connected with an external connection terminal of a chip circuit on the surface of the lower chip, and electric leads between the bottom chip and the substrate and between the upper associated chips are connected through the extension circuits on the external connection part of the circuit extension plate. Compared with a traditional stacking mode, the size of a chip stacking body is reduced by 20-50%.

Description

Technical Field

[0001] The invention relates to a stacking structure and method of multiple related chips, a packaging structure and a packaging method, and belongs to the technical field of chips. Background Art

[0002] In order to reduce the assembly volume, multiple related chips need to be stacked up and down. The traditional stacking method is as follows Fig.10 As shown, multiple chips 1 are stacked one by one from bottom to top in a step-like manner, that is, when a chip 1 is mounted on a next chip 1, a circuit welding surface 102 of the next chip 1 is left, and the circuit welding surface 102 is used to connect the circuit with the previous chip 1 and the next chip 1 or the substrate. This stacking method has two major defects: First, each time a chip is added, a circuit soldering surface must be reserved for the next chip, which actually increases the volume of the entire chip package (the stacked chips must be encapsulated with epoxy resin); 2. During packaging, the distance between the rear of the lower chip and the package end face is too long, which is not conducive to the heat dissipation of the lower chip. Summary of the invention

[0003] The technical problem to be solved by the present invention is: how to reduce the volume of the entire stacked chip package.

[0004] In view of the above problems, the technical solution proposed by the present invention is: A stacked structure of multiple related chips, including a substrate, multiple chips stacked on the substrate, adhesive used between the bottom chip and the substrate and between the upper and lower chips, electrical conductors used to connect the bottom chip and the substrate and electrical conductors between the related chips, and a circuit extension board arranged between the upper and lower chips, the circuit extension board is divided into an external connection part and an internal connection part, at least an extension circuit from the internal connection part to the external connection part is provided on the upper surface of the circuit extension board, multiple chips are vertically stacked to form a chip stack, the internal connection part of the circuit extension board is overlapped between two adjacent chips, and its external connection part is located outside the chip stack, the extension circuit at the internal connection end of the circuit extension board is connected to the external connection terminal of the chip circuit on the surface of the lower chip, and the electrical conductors between the bottom chip and the substrate and the electrical conductors between the upper related chips are all connected through the extension circuit on the external connection part of the circuit extension board.

[0005] The extension circuit is a printed circuit.

[0006] The extension circuit extends to the end surface of the internal connection part of the circuit extension board.

[0007] The end of the internal connection portion of the circuit extension board is located at the external connection terminal of the chip circuit on the surface of the chip.

[0008] When there are more than two circuit extension boards, the length of the external connection portion of the lower circuit extension board is greater than the length of the upper circuit extension board.

[0009] The thickness of the circuit extension board is smaller than the thickness of the adhesive between the upper and lower chips.

[0010] A method for stacking a plurality of related chips as described above comprises the following steps: S1: Apply adhesive on the substrate and attach the first chip to the adhesive; S2: a. Apply adhesive to the position of the inner connection part of the first chip mounting circuit extension board, and attach the inner connection part of the first circuit extension board to the first chip; b. Connecting the extension circuit at the internal connection end of the circuit extension board to the external connection terminal of the chip circuit on the surface of the lower chip by welding; c. Apply glue to the upper surface of the first chip that is not coated with glue and the upper surface of the inner connection part of the circuit extension board, and attach the second chip to the coated glue; S3: stack the second circuit extension board and the third chip according to the method of S2, and continue stacking in this way until the stacking is completed; S4: Welding the electrical wires, the welding operation includes: connecting the extension circuit of the first circuit extension board with the circuit on the substrate by welding using the electrical wires, connecting the extension circuit on the lower circuit extension board with the extension circuit on the upper circuit extension board by welding using the electrical wires, and connecting the extension circuit on the lower circuit extension board with the external terminal of the chip circuit on the surface of the top chip by welding using the electrical wires.

[0011] A packaging structure of a stacked structure of multiple related chips as described above includes a sealing body that covers and seals the chip stack on a substrate and a heat conductor at one end of the chip stack away from the external connection part of the circuit extension board. The inner side of the heat conductor is bonded to all chips through a thermally conductive adhesive and the outer side is exposed.

[0012] The outer bottom end of the heat conductor is provided with an L-shaped notch, and the space between the L-shaped notch and the substrate is filled with a sealing glue.

[0013] A packaging method for the packaging structure as described above, wherein a plurality of chip stacks are manufactured in rows and columns on the same substrate, the chip stacks in two adjacent columns are arranged back to back and share a thermal conductive blank to be separated, a notch to be separated with an opening downward is provided in the middle of the bottom surface of the thermal conductive blank to be separated, and then epoxy resin is used as a sealing glue on the upper surface of the substrate for overall packaging, and finally a packaging body of a single chip stack is obtained by cutting along the row and column cutting lines. Beneficial Effects

[0014] 1. The volume of the chip stack is reduced. Compared with the traditional stacking method, the volume is reduced by 20-50%. The specific reduction ratio depends on the number of chips stacked; 2. From the chip stacking structure to the chip packaging structure, it is beneficial to significantly improve the overall heat dissipation efficiency of the chip; 3. The production method is simple and easy. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a three-dimensional schematic diagram of the chip stacking body described in Embodiments 1 and 2; Figure 2 It is a cross-sectional schematic diagram of the chip stacking body described in Embodiments 1 and 2; Figure 3 It is a three-dimensional schematic diagram of the circuit extension board described in Examples 1 and 2; Figure 4 It is a plan view of the circuit extension board described in Embodiments 1 and 2; Figure 5 for Figure 2 A partial schematic diagram of Figure 6 It is a three-dimensional schematic diagram of the packaging structure described in Embodiments 3 and 4; Figure 7 It is a cross-sectional schematic diagram of the packaging structure described in Embodiments 3 and 4; Figure 8 It is a cross-sectional schematic diagram of the heat conductor described in Embodiments 3 and 4; Fig. 9 It is a cross-sectional schematic diagram of two adjacent chip stacks stacked back to back and sharing a heat-conducting blank to be separated; Fig.10 A three-dimensional schematic diagram of a chip stack stacked in a traditional manner.

[0016] In the figure: 100, chip stack; 200, sealing body; 1, chip; 101, chip circuit; 102, circuit welding surface; 2, substrate; 3, adhesive; 4, electric wire; 5, circuit extension board; 501, extension circuit; 6, welding point; 7, heat conductor; 701, L-shaped notch; 8, thermal conductive adhesive; 9, thermal conductive blank to be divided; 901, notch to be divided; 10, cutting line. DETAILED DESCRIPTION

[0017] The present invention will be further described below in conjunction with embodiments and drawings: Embodiment 1

[0018] like Figure 1As shown in FIG. 5 , a stacked structure of multiple related chips includes a substrate 2, multiple chips 1 stacked on the substrate 2, an adhesive 3 used between the bottom chip 1 and the substrate 2 and between the upper and lower chips, and an electric conductor 4 used to connect the bottom chip 1 and the substrate 2 and the electric conductor 4 between the related chips 1. The improvement is that it also includes a circuit extension board 5 arranged between the upper and lower chips, the circuit extension board 5 is divided into an external connection part and an internal connection part, and at least an extension circuit 501 from the internal connection part to the external connection part is provided on the upper surface of the circuit extension board 5. Multiple chips 1 are vertically stacked to form a chip stacking body 100, the internal connection part of the circuit extension board 5 is overlapped between two adjacent chips, and the external connection part is located outside the chip stacking body 100, the extension circuit 501 at the internal connection end of the circuit extension board 5 is connected to the external terminal of the chip circuit 101 on the surface of the lower chip 1, and the electric conductor 4 between the bottom chip 1 and the substrate 2 and the electric conductor 4 between the upper related chips 1 are all connected through the extension circuit 501 on the external connection part of the circuit extension board 5. In this way, it does not need to occupy more space like the traditional step-type stacking. If the area of ​​all chips 1 is equal, they can be neatly stacked upwards on all sides. Compared with the traditional stacking method, the chip stack 100 of three chips can reduce the volume by 20-50%. In addition, during the later packaging, the chip stack 100 can be made thinner around, and the heat conductor can also be made thinner accordingly, which greatly reduces the heat conduction distance of the lower chip 1 and significantly improves the heat dissipation effect.

[0019] Preferably, the extension circuit 501 is a printed circuit.

[0020] like Figure 4 As shown, further, the extension circuit 501 extends to the end surface of the internal connection portion of the circuit extension board 5, which is conducive to connecting the end surface with the external connection terminal of the chip circuit 101 on the surface of the chip 1 nearby.

[0021] like Figure 1 , 2 As shown, the end of the internal connection portion of the circuit extension board 5 is located at the external terminal of the chip circuit 101 on the surface of the chip 1, so as to connect the extension circuit 501 to the external terminal of the chip circuit 101 on the surface of the chip 1 nearby.

[0022] like Figure 2 , 5 As shown, when there are more than two circuit extension boards 5, the length of the external connection portion of the lower circuit extension board 5 is greater than that of the upper circuit extension board 5. This is beneficial to reduce mutual interference when welding electrical conductors. However, the length of the external connection portion of the lower circuit extension board 5 is greater than that of the upper circuit extension board 5, but it is only slightly greater, and does not form an obvious step and significantly increase the stacking volume.

[0023] The thickness of the circuit extension board 5 is less than the thickness of the adhesive 3 between the upper and lower chips. Here, the thickness of the adhesive 3 refers to the normal thickness of the adhesive 3, that is, the thickness of the adhesive 3 will not be increased after the circuit extension board 5 is clamped, so as to ensure that the total thickness of the chip stack 100 is not increased.

[0024] like Figure 1 As shown, it should be noted that a certain extension circuit 501 on a circuit extension board 5 has three connection situations: 1. It is only directly or indirectly connected to the chip circuit 101 of the upper chip 1; 2. Only indirectly connected to the chip circuit 101 of the lower chip 1 or directly connected to the circuit on the substrate 35; 3. While indirectly connecting to the chip circuit 101 of the lower chip 1 or directly connecting to the circuit on the substrate 35 , it is also directly or indirectly connected to the chip circuit 101 of the upper chip 1 . Embodiment 2

[0025] See also Figure 1 —5. The stacking method of the above-mentioned embodiment 1 in which a plurality of related chips are stacked to form a stacked body comprises the following steps: S1: Apply adhesive 3 on the substrate 2, and attach the first chip 1 to the adhesive 3; S2: a. Apply adhesive 3 to the position where the first chip 1 is mounted on the inner connection part of the circuit extension board 5, and attach the inner connection part of the first circuit extension board 5 to the first chip 1; b. Connect the extension circuit 501 at the internal connection end of the circuit extension board 5 to the external connection terminal of the chip circuit 101 on the surface of the lower chip 1 by welding to form a welding point 6; c. Apply adhesive 3 to the upper surface of the first chip 1 that is not coated with adhesive 3 and the upper surface of the inner connection portion of the circuit extension board 5, and attach the second chip 1 to the coated adhesive 3; S3: stacking the second circuit extension board 5 and the third chip 1 according to the method of S2, and continuing the stacking process in this way until the stacking is completed; S4: Welding the electrical conductor 4. The welding operation includes: connecting the extension circuit 501 of the first circuit extension board 5 with the circuit on the substrate 2 by welding using the electrical conductor 4, connecting the extension circuit 501 on the lower circuit extension board 5 with the extension circuit 501 on the upper circuit extension board 5 by welding using the electrical conductor 4, and connecting the extension circuit 501 on the lower circuit extension board 5 with the external terminal of the chip circuit 101 on the surface of the top chip 1 by welding using the electrical conductor 4.

[0026] There is no strict order restriction for the operations in the above S4. Embodiment 3

[0027] like Figure 6As shown in FIG. 9 , the packaging structure of the stacked structure of multiple related chips described in the first embodiment includes a sealing glue body 200 that encapsulates the chip stack 100 on the substrate 2 and a heat conductor 7 at one end of the chip stack 100 away from the external connection part of the circuit extension board 5. The inner side of the heat conductor 7 is bonded to all the chips 1 through the heat conductive glue 8, and the outer side is exposed. In this way, the packaging of the package body is achieved, and the normal heat dissipation of the chip 1 can be ensured.

[0028] The outer bottom end of the heat conductor 7 has an L-shaped notch 701, and the space between the L-shaped notch 701 and the substrate 2 is filled with the sealing glue 200. In this way, when the heat conductor 7 is assembled, it can also ensure that the adhesive 3 at the bottom of the chip stack 100 will not overflow when encountering high temperature. Embodiment 4

[0029] See also Figure 6 —9, the packaging method of the packaging structure described in the above-mentioned embodiment 3 is to manufacture multiple chip stacks 100 in rows and columns on the same substrate 2, and the chip stacks 100 in two adjacent columns are arranged back to back and share a heat-conducting blank 9 to be divided, and a notch 901 to be divided with an opening downward is set in the middle of the bottom surface of the heat-conducting blank 9 to be divided, and then epoxy resin is used as a sealing body 200 on the upper surface of the substrate 2 for overall packaging, and finally, the packaging body of a single chip stack 100 is obtained by cutting along the row and column cutting lines 10, and the divided heat-conducting blank 9 is cut into the heat-conducting bodies 7 belonging to the left and right chip stacks 100.

[0030] The above embodiments are only used to more clearly describe the present invention and cannot be regarded as limiting the protection scope of the present invention. Any modifications in equivalent forms should be regarded as falling within the protection scope of the present invention.

Claims

1. A stacked structure of multiple associated chips, comprising a substrate (2), multiple chips (1) stacked on the substrate (2), an adhesive (3) used between the bottom chip (1) and the substrate (2) and between the upper and lower chips, an electrical conductor (4) used to connect the bottom chip (1) and the substrate (2), and an electrical conductor (4) between the associated chips (1), characterized in that: It also includes a circuit extension board (5) arranged between the upper and lower chips, the circuit extension board (5) is divided into an external connection part and an internal connection part, and an extension circuit (501) from the internal connection part to the external connection part is provided on at least the upper surface of the circuit extension board (5). A plurality of chips (1) are stacked vertically to form a chip stack (100), the internal connection part of the circuit extension board (5) is stacked between two adjacent chips, and its external connection part is located outside the chip stack (100). The extension circuit (501) at the internal connection end of the circuit extension board (5) is connected to the external connection terminal of the chip circuit (101) on the surface of the lower chip (1), and the electrical conductor (4) between the bottom chip (1) and the substrate (2) and the electrical conductor (4) between the upper associated chips (1) are all connected through the extension circuit (501) on the external connection part of the circuit extension board (5).

2. The stacked structure of multiple related chips according to claim 1, characterized in that: The extension circuit (501) is a printed circuit.

3. The stacked structure of multiple related chips according to claim 1, characterized in that: The extension circuit (501) extends to the end surface of the internal connection portion of the circuit extension plate (5).

4. The stacked structure of multiple related chips according to any one of claims 1 to 3, characterized in that: The end of the internal connection portion of the circuit extension board (5) is located at the external connection terminal of the chip circuit (101) on the surface of the chip (1).

5. The stacked structure of multiple related chips according to any one of claims 1 to 3, characterized in that: When there are more than two circuit extension plates (5), the length of the external connection portion of the lower circuit extension plate (5) is greater than the length of the upper circuit extension plate (5).

6. The stacked structure of multiple related chips according to claim 1, characterized in that: The thickness of the circuit extension plate (5) is smaller than the thickness of the adhesive (3) between the upper and lower chips.

7. A method for stacking a plurality of related chips as claimed in claim 1, characterized in that: The steps include: S1: Apply adhesive (3) on the substrate (2), and attach the first chip (1) to the adhesive (3); S2： a. Applying adhesive (3) to the position where the first chip (1) is mounted on the inner connection portion of the circuit extension board (5), and attaching the inner connection portion of the first circuit extension board (5) to the first chip (1); b. Connecting the extension circuit (501) at the internal connection end of the circuit extension board (5) to the external connection terminal of the chip circuit (101) on the surface of the lower chip (1) by welding; c. Applying adhesive (3) to the upper surface of the first chip (1) that is not coated with adhesive (3) and to the upper surface of the inner connection portion of the circuit extension board (5), and attaching the second chip (1) to the coated adhesive (3); S3: stacking the second circuit extension board (5) and the third chip (1) according to the method of S2, and continuing the stacking process in this way until the stacking is completed; S4: welding the electrical conductor (4), the welding operation comprising: connecting the extension circuit (501) of the first circuit extension board (5) to the circuit on the substrate (2) by welding using the electrical conductor (4), connecting the extension circuit (501) of the lower circuit extension board (5) to the extension circuit (501) of the upper circuit extension board (5) by welding using the electrical conductor (4), and connecting the extension circuit (501) of the lower circuit extension board (5) to the external terminal of the chip circuit (101) on the surface of the top chip (1) by welding using the electrical conductor (4).

8. A packaging structure of a stacked structure of a plurality of related chips as claimed in claim 1, characterized in that: It comprises a sealing body (200) for encapsulating a chip stack (100) on a substrate (2) and a heat conductor (7) at one end of the chip stack (100) away from the external connection portion of a circuit extension board (5), wherein the inner side of the heat conductor (7) is bonded to all chips (1) via a heat conductive adhesive (8) and the outer side is exposed.

9. The packaging structure according to claim 8, characterized in that: The outer bottom end of the heat conductor (7) has an L-shaped notch (701), and the space between the L-shaped notch (701) and the substrate (2) is filled with a sealing glue (200).

10. A packaging method for the packaging structure according to claim 8, characterized in that: A plurality of chip stacks (100) are manufactured in rows and columns on the same substrate (2); the chip stacks (100) in two adjacent columns are arranged back to back and share a common thermal conductive blank (9) to be separated; a separation notch (901) opening downward is provided in the middle of the bottom surface of the thermal conductive blank (9) to be separated; then, epoxy resin is used as a sealing glue (200) on the upper surface of the substrate (2) for overall packaging; and finally, the chip stacks (100) are cut along row and column cutting lines (10) to obtain a package of a single chip stack (100).

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