Signal filtering system, method and device, access network equipment and medium

Abstract

The invention discloses a signal filtering system, method and device, access network equipment and a medium, and relates to the field of wireless communication. According to the specific implementation scheme, an N-order filter coefficient is stored through a second memory; storing each data point obtained by sampling the target signal through a first memory; when a data point is stored in a first memory, first data stored in at least one first address is read from a second port, second data stored in at least one second address is read from a fourth port, an N-order filter coefficient is read from a sixth port, target operation is executed on the first data and the second data based on the N-order filter coefficient, and the data point is stored in the first memory. And obtaining and outputting the filtered data corresponding to one data point. Therefore, the target signal can be filtered by only adopting one DSP, the first memory and the second memory, that is, the target signal is filtered based on a serial processing mode, and the occupancy rate of DSP and LUT resources is relatively low.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a signal filtering system, method, device, access network equipment and medium. Background Art

[0002] In order to improve the quality of the transmission signal, after receiving the uplink signal sent by the terminal device in the service cell, the access network device can filter the uplink signal, or can filter the downlink signal and send it to the terminal device.

[0003] In the related art, the access network equipment can adopt a full parallel processing method to filter the transmission signal (including uplink signal and downlink signal).

[0004] The above method can realize parallel processing of multi-carrier and multi-antenna interleaving when the baseband sampling rate is relatively high. However, for NB_IOT (Narrow Band Internet of Things) cells, the baseband sampling rate is relatively low. If a full parallel processing method is used to filter the transmission signal, a large amount of LUT (Look up Table) resources and DSP (Digital Signal Processing) resources will be required, resulting in a large resource consumption. Summary of the invention

[0005] The present application provides a method, apparatus, access network equipment and medium for signal filtering.

[0006] According to one aspect of the present application, a signal filtering system is provided, comprising: a digital signal processor DSP, a first memory and a second memory, wherein a first port of the DSP is connected to a second port of the first memory, a third port of the DSP is connected to a fourth port of the first memory, and a fifth port of the DSP is connected to a sixth port of the second memory;

[0007] The second memory is used to store N-order filter coefficients; wherein N is a positive integer greater than 1;

[0008] The storage depth of the first memory is N, and the first memory is used to store each data point obtained by sampling the target signal;

[0009] The DSP is used to read at least one first data stored in a first storage address address from the second port based on the first port whenever a data point is stored in the first memory, and read at least one second data stored in a second address from the fourth port based on the third port, and read the N-order filter coefficient from the sixth port based on the fifth port, and perform a target operation on the first data and the second data based on the N-order filter coefficient to obtain and output the filtered data corresponding to the one data point.

[0010] As a possible implementation, the N-order filter coefficients are symmetric coefficients. When N is an even number, the second memory is used to store N / 2 filter coefficients, and / or when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; the data point obtained by the i-th sampling is stored in the first memory at address[(i modN)-1], where mod is a modulo operation, and i is a positive integer; the target operation includes a pre-addition operation, a multiplication operation, and an accumulation operation.

[0011] As a possible implementation, when N is an even number, the DSP is specifically used to: when the data point obtained by the i-th sampling is stored in address[(i mod N)-1] in the first memory, read the first data stored in each first address from the second port based on the first port; wherein the first address includes: address(i mod N), address{[(i mod N)+1]mod N}, address{[(i mod N)+2]mod N}, ..., address{[(i mod N)+(N / 2-1)]mod N}; read the second data stored in each second address from the fourth port based on the third port; wherein the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N], ..., address[(i+N / 2)mod N]; based on the fifth port, read N / 2 filter coefficients from the sixth port; according to the N / 2 filter coefficients, perform a target operation on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0012] As a possible implementation, the DSP is specifically used to: perform N / 2 iterations according to the N / 2 filter coefficients, the first data stored at the first address and the second data stored at the second address; use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling; wherein the first iteration includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iteration, and performing a multiplication operation on the pre-addition result of the first iteration according to the first-order filter coefficients to obtain the output of the first iteration; the j-th iteration includes: performing a multiplication operation on the first data stored at the read address {[(imod N)+j-1] mod N} and the second data stored at the address [(i+Nj) mod N] to obtain the output of the first iteration; N] performs a pre-addition operation on the second data stored in the j-th iterative process to obtain the pre-addition result of the j-th iterative process, performs a multiplication operation on the pre-addition result of the j-th iterative process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iterative process, and performs an accumulation operation on the output of the j-1-th iterative process and the intermediate result of the j-th iterative process to obtain the output of the j-th iterative process; wherein j=2, 3,…, N / 2.

[0013] As a possible implementation manner, when N is an odd number, the DSP is specifically used to: when the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, read the first data stored in each first address from the second port based on the first port; wherein the first address includes: address(i mod N), address{[(i mod N)+1]mod N}, address{[(i mod N)+2]mod N}, …, address{[(i mod N)+(N-1) / 2]mod N}; read the second data stored in each second address from the fourth port based on the third port, wherein the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N] …, address[(i+(N+1) / 2)mod N]; based on the fifth port, read (N+1) / 2 filter coefficients from the sixth port; according to the (N+1) / 2 filter coefficients, perform a target operation on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0014] As a possible implementation manner, the DSP is specifically used to: perform (N+1) / 2 iterations according to the (N+1) / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling;

[0015] The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process;

[0016] The k-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain a pre-addition result of the k-th iteration process, performing a multiplication operation on the pre-addition result of the k-th iteration process according to the k-th order filter coefficient to obtain an intermediate result of the k-th iteration process, and performing an accumulation operation on the output of the k-1-th iteration process and the intermediate result of the k-th iteration process to obtain an output of the k-th iteration process; wherein k=2, 3, ..., (N-1) / 2;

[0017] The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(i mod N)+(N-1) / 2]mod N} according to the filter coefficient of the (N+1) / 2th order to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0018] As a possible implementation manner, the first memory is a block random access memory BRAM, and the second memory is a read-only memory ROM.

[0019] As a possible implementation, applied to an access network device, the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

[0020] According to another aspect of the present application, a signal filtering method is provided, which is applied to a DSP, and includes: whenever a data point is stored in a first memory, reading first data stored at least one first storage address address from the first memory; wherein the data point is obtained by sampling a target signal, and the storage depth of the first memory is N, where N is a positive integer greater than 1; reading second data stored at least one second address from the first memory; reading N-order filter coefficients from the second memory; and performing a target operation on the first data and the second data based on the N-order filter coefficients to obtain and output filtered data corresponding to the one data point.

[0021] As a possible implementation, the N-order filter coefficients are symmetric coefficients. When N is an even number, the second memory is used to store N / 2 filter coefficients, and / or when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; the data point obtained by the i-th sampling is stored in the first memory at address[(i modN)-1], where mod is a modulo operation, and i is a positive integer; the target operation includes a pre-addition operation, a multiplication operation, and an accumulation operation.

[0022] As a possible implementation manner, when N is an even number and the data point obtained by the i-th sampling is stored in address [(i mod N) - 1] in the first memory, the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}; the second address includes: address [(i + N - 1) mod N], address [(i + N - 2) mod N], address [(i + N - 3) mod N], ..., address [(i + N / 2) mod N];

[0023] The step of reading N-order filter coefficients from the second memory comprises: reading N / 2 filter coefficients from the second memory;

[0024] The target operation is performed on the first data and the second data based on the N-order filter coefficients to obtain and output the filtered data corresponding to the one data point, including: according to the N / 2 filter coefficients, the target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain the filtered data corresponding to the data point obtained by the i-th sampling.

[0025] As a possible implementation manner, performing a target operation on the first data stored at the first address and the second data stored at the second address according to the N / 2 filter coefficients to obtain filtered data corresponding to the data point obtained by the i-th sampling includes: performing N / 2 iterations according to the N / 2 filter coefficients, the first data stored at the first address and the second data stored at the second address; and using the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling;

[0026] The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process;

[0027] The j-th iterative process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iterative process, performing a multiplication operation on the pre-addition result of the j-th iterative process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iterative process, and performing an accumulation operation on the output of the j-1-th iterative process and the intermediate result of the j-th iterative process to obtain the output of the j-th iterative process; wherein j=2, 3,…, N / 2.

[0028] As a possible implementation manner, when N is an odd number and the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, the first address includes: address(i mod N), address{[(i mod N)+1] mod N}, address{[(i mod N)+2] mod N}, ..., address{[(i mod N)+(N-1) / 2] mod N}; the second address includes: address[(i+N-1) mod N], address[(i+N-2) mod N], address[(i+N-3) mod N] ..., address[(i+(N+1) / 2) mod N];

[0029] The step of reading N-order filter coefficients from the second memory comprises: reading (N+1) / 2 filter coefficients from the second memory;

[0030] The target operation is performed on the first data and the second data based on the N-order filter coefficient to obtain and output the filtered data corresponding to the one data point, including: according to the (N+1) / 2 filter coefficients, the target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain the filtered data corresponding to the data point obtained by the i-th sampling.

[0031] As a possible implementation manner, the performing a target operation on the first data stored at the first address and the second data stored at the second address according to the (N+1) / 2 filter coefficients to obtain filtered data corresponding to the data point obtained by the i-th sampling includes: performing (N+1) / 2 iterations according to the (N+1) / 2 filter coefficients, the first data stored at the first address and the second data stored at the second address; and using the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling;

[0032] The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process;

[0033] The k-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain a pre-addition result of the k-th iteration process, performing a multiplication operation on the pre-addition result of the k-th iteration process according to the k-th order filter coefficient to obtain an intermediate result of the k-th iteration process, and performing an accumulation operation on the output of the k-1-th iteration process and the intermediate result of the k-th iteration process to obtain an output of the k-th iteration process; wherein k=2, 3, ..., (N-1) / 2;

[0034] The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(i mod N)+(N-1) / 2]mod N} according to the filter coefficient of the (N+1) / 2th order to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0035] As a possible implementation manner, the first memory is a block random access memory BRAM, and the second memory is a read-only memory ROM.

[0036] As a possible implementation, applied to an access network device, the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

[0037] According to another aspect of the present application, a signal filtering device is provided, which is applied to a DSP, comprising:

[0038] A first reading unit is used to read first data stored at least one first storage address address from the first memory whenever a data point is stored in the first memory; wherein the data point is obtained by sampling the target signal, and the storage depth of the first memory is N, where N is a positive integer greater than 1;

[0039] A second reading unit, configured to read second data stored at least one second address from the first memory;

[0040] A third reading unit, used for reading N-order filter coefficients from the second memory;

[0041] An execution unit is used to perform a target operation on the first data and the second data based on the N-th order filter coefficient to obtain and output filtered data corresponding to the one data point.

[0042] As a possible implementation, the N-order filter coefficients are symmetric coefficients. When N is an even number, the second memory is used to store N / 2 filter coefficients, and / or when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; the data point obtained by the i-th sampling is stored in the first memory at address[(i modN)-1], where mod is a modulo operation, and i is a positive integer; the target operation includes a pre-addition operation, a multiplication operation, and an accumulation operation.

[0043] As a possible implementation manner, when N is an even number and the data point obtained by the i-th sampling is stored in address [(i mod N) - 1] in the first memory, the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}; the second address includes: address [(i + N - 1) mod N], address [(i + N - 2) mod N], address [(i + N - 3) mod N], ..., address [(i + N / 2) mod N];

[0044] The third reading unit is specifically configured to: read N / 2 filter coefficients from the second memory;

[0045] The execution unit is specifically used to: perform a target operation on the first data stored at the first address and the second data stored at the second address read according to the N / 2 filter coefficients, so as to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0046] As a possible implementation manner, the execution unit is specifically configured to: perform N / 2 iterations according to the N / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling;

[0047] The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process;

[0048] The j-th iterative process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iterative process, performing a multiplication operation on the pre-addition result of the j-th iterative process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iterative process, and performing an accumulation operation on the output of the j-1-th iterative process and the intermediate result of the j-th iterative process to obtain the output of the j-th iterative process; wherein j=2, 3,…, N / 2.

[0049] As a possible implementation manner, when N is an odd number and the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, the first address includes: address(i mod N), address{[(i mod N)+1] mod N}, address{[(i mod N)+2] mod N}, ..., address{[(i mod N)+(N-1) / 2] mod N}; the second address includes: address[(i+N-1) mod N], address[(i+N-2) mod N], address[(i+N-3) mod N] ..., address[(i+(N+1) / 2) mod N];

[0050] The third reading unit is specifically configured to: read (N+1) / 2 filter coefficients from the second memory;

[0051] The execution unit is specifically used to: perform a target operation on the first data stored at the first address and the second data stored at the second address read according to the (N+1) / 2 filter coefficients, so as to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0052] As a possible implementation manner, the execution unit is specifically configured to: execute (N+1) / 2 iterations according to the (N+1) / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling;

[0053] The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process;

[0054] The k-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain a pre-addition result of the k-th iteration process, performing a multiplication operation on the pre-addition result of the k-th iteration process according to the k-th order filter coefficient to obtain an intermediate result of the k-th iteration process, and performing an accumulation operation on the output of the k-1-th iteration process and the intermediate result of the k-th iteration process to obtain an output of the k-th iteration process; wherein k=2, 3, ..., (N-1) / 2;

[0055] The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(i mod N)+(N-1) / 2]mod N} according to the filter coefficient of the (N+1) / 2th order to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0056] As a possible implementation manner, the first memory is a block random access memory BRAM, and the second memory is a read-only memory ROM.

[0057] As a possible implementation, applied to an access network device, the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

[0058] According to another aspect of the present application, an access network device is provided, comprising: a digital signal processor DSP, a first memory and a second memory, wherein a first port of the DSP is connected to a second port of the first memory, a third port of the DSP is connected to a fourth port of the first memory, and a fifth port of the DSP is connected to a sixth port of the second memory;

[0059] The second memory is used to store N-order filter coefficients; wherein N is a positive integer greater than 1;

[0060] The storage depth of the first memory is N, and the first memory is used to store each data point obtained by sampling the target signal;

[0061] The DSP is used to execute the signal filtering method described in the above embodiment.

[0062] According to another aspect of the present application, a processor-readable storage medium is provided, wherein the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the signal filtering method described in the above embodiment.

[0063] According to another aspect of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the signal filtering method described in the above embodiment of the present application is implemented.

[0064] The signal filtering system, method, device, access network equipment and medium provided in the embodiments of the present application store N-order filter coefficients through the second memory; store each data point obtained by sampling the target signal through the first memory; read the first data stored by at least one first storage address address from the second port based on the first port, read the second data stored by at least one second address from the fourth port based on the third port, read the N-order filter coefficients from the sixth port based on the fifth port, and perform the target operation on the first data and the second data based on the N-order filter coefficients to obtain and output the filtered data corresponding to one data point. Thus, it is possible to filter the target signal using only one first memory, one second memory and one DSP, which can reduce resource occupancy. That is, in the present application, the target signal can be filtered based on the serial processing method, and the occupancy rate of DSP resources and LUT resources is low.

[0065] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present application.

[0067] Figure 1 Schematic diagram of the implementation structure of the 10th order filter coefficient;

[0068] Figure 2 A schematic diagram of the structure of a signal filtering system provided in an embodiment of the present application;

[0069] Figure 3 A schematic diagram of the structure of another signal filtering system provided in an embodiment of the present application;

[0070] Figure 4 A schematic diagram of the data format provided in the embodiment of the present application;

[0071] Figure 5The timing relationship diagram provided in the embodiment of the present application is Figure 1 ;

[0072] Figure 6 The timing relationship diagram provided in the embodiment of the present application is Figure 2 ;

[0073] Figure 7 A schematic diagram of a flow chart of a signal filtering method provided in an embodiment of the present application;

[0074] Figure 8 A schematic diagram of the structure of a signal filtering device provided in an embodiment of the present application;

[0075] Fig. 9 A schematic diagram of the structure of an access network device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0076] In the embodiments of the present application, the term "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0077] In the embodiments of the present application, the term "plurality" refers to two or more than two, and other quantifiers are similar.

[0078] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0079] The impulse response of a FIR (Finite Impulse Response) filter is composed of a finite number of sample values. The differential equation of a FIR filter system with N taps is shown in formula (1):

[0080]

[0081] That is, when the input signal x(n) passes through the N-tap filter h(n), the output is y(n).

[0082] In the related art, the FIR filter system is implemented in full parallel. When the baseband sampling rate is relatively high, this implementation method can realize parallel processing of multi-carrier multi-antenna interleaving, and the implementation structure is as follows: Figure 1 As shown. Among them, Figure 1In the example, the filter coefficient of the FIR filter is 10th order. The filter coefficient of even order can save half of the DSP operation by using the DSP pre-addition operation.

[0083] Among them, the filtering processing of the input signal includes delay processing, pre-addition processing and multiplication and accumulation processing. The specific processing process includes the following steps:

[0084] Step 1: The data stream x(n) is divided into two paths, one of which enters the delay module z -1 , generates the input of the next-level multiplication and accumulation module, and the other path enters the multiplication and accumulation module of this level;

[0085] Step 2, enter the first-level multiplication and accumulation module (such as Figure 1 The data stream (shown in the middle area 11) first completes the pre-addition operation with the data stream after the delay processing, then completes the multiplication operation with the first-level filter coefficient, and finally enters the multiplication and accumulation module of the next level. Among them, each level of the multiplication and accumulation module is implemented by calling the DSP module;

[0086] Step 3, the second-level multiplication and accumulation module, i.e., the second-level DSP, has three data streams as input, namely, the output of the first-level delay processing module, the output of the eighth-level delay processing module (the delay processing modules are numbered 1 to 9 in sequence according to the data flow direction), and the output of the previous-level DSP. The pre-addition operation and multiplication operation of this level are the same as those of the first-level DSP, except that: the operation of accumulating the output of the first-level DSP is added;

[0087] Step 4: The processing method of the third-level DSP and the fourth-level DSP is the same as that of the second-level DSP;

[0088] Step 5: The pre-addition operation, multiplication operation and accumulation operation of the fifth-level DSP are the same as those of the previous levels, except that the output of the fifth-level DSP is the output of the entire FIR filter system.

[0089] Table 1 takes the 6th-order symmetrical filter coefficients as an example and lists the FIR filtering processing flow of the first 9 sampled data points (d0, d1, d2, d3, d4, d5, d6, d7, and d8, respectively).

[0090] Table 1 Filtering results of 6th order symmetric filter coefficients

[0091] H0 H1 H2 H2 H1 H0 FIR_out 1 d0 0 0 0 0 0 d0*H0 2 d1 d0 0 0 0 0 d1*H0+d0*H1 3 d2 d1 d0 0 0 0 d2*H0+d1*H1+d2*H2 4 d3 d2 d1 d0 0 0 d3*H0+d2*H1+(d1+d0)*H2 5 d4 d3 d2 d1 d0 0 d4*H0+(d3+d0)*H1+(d2+d1)*H2 6 d5 d4 d3 d2 d1 d0 (d5+d0)*H0+(d4+d1)*H1+(d3+d2)*H2 7 d6 d5 d4 d3 d2 d1 (d6+d1)*H0+(d5+d2)*H1+(d4+d3)*H2 8 d7 d6 d5 d4 d3 d2 (d7+d2)*H0+(d6+d3)*H1+(d5+d4)*H2 9 d8 d7 d6 d5 d4 d3 (d8+d3)*H0+(d7+d4)*H1+(d6+d5)*H2

[0092] Table 2 takes the 7th-order symmetrical filter coefficients as an example and lists the FIR filtering processing flow of the first 9 sampled data points (d0, d1, d2, d3, d4, d5, d6, d7, and d8, respectively).

[0093] Table 2 Filtering results of 7th order symmetric filter coefficients

[0094]

[0095] It should be noted that full parallel processing means that all DSPs work simultaneously to filter the data stream. The number of DSPs required is half the length of the filter coefficient (for symmetrical filter coefficients), and the data input to each DSP level needs to pass through the delay module to ensure that the data output by each DSP level can be aligned and added.

[0096] However, when the baseband sampling rate is relatively low, if full parallel processing is still used, it will take up half the number of DSPs of the filter order and require a large number of LUT resources to complete the data delay operation, resulting in high resource consumption.

[0097] Therefore, in order to solve at least one of the above-mentioned problems, the embodiments of the present application provide a signal filtering system, method, device, access network equipment and medium, wherein the system, method and device are based on the same application concept. Since the principles of solving the problems by the system, method and device are similar, the implementation of the system, device and method can refer to each other, and the repeated parts will not be repeated.

[0098] The signal filtering system, method, device, access network equipment and medium provided by the present application are described below with reference to the accompanying drawings. Before describing the embodiments of the present application in detail, for ease of understanding, common technical terms are first introduced:

[0099] RAM, short for Random Access Memory, is a type of read-write memory in a computer that can access any storage unit randomly. RAM is part of the computer's main memory, which can store running programs and temporary data for the CPU (Central Processing Unit) to access at any time. It has the characteristics of fast reading speed and large capacity.

[0100] ROM (Read Only Memory) is a memory that can only be read but not written. Its data is written and locked inside the chip during production and is invisible to the user. ROM has the characteristics of stable data storage and preventing data from being modified or deleted. It is often used to store solidified programs and data.

[0101] Figure 2 A schematic diagram of the structure of a signal filtering system provided in an embodiment of the present application.

[0102] like Figure 2As shown, the signal filtering system may include: DSP100, a first memory 200 and a second memory 300, wherein the first port 101 of the DSP100 is connected to the second port 201 of the first memory 200, the third port 102 of the DSP100 is connected to the fourth port 202 of the first memory 200, and the fifth port 103 of the DSP100 is connected to the sixth port 301 of the second memory 300.

[0103] The second memory 300 is used to store N-th order filter coefficients; wherein N is a positive integer greater than 1.

[0104] For example, the second memory 300 may be used to store N-th order filter coefficients (or referred to as N-th order coefficients) of a FIR filter.

[0105] The storage depth of the first memory 200 is N, wherein the first memory 200 is used to store various data points obtained by sampling the target signal.

[0106] Among them, the target signal may include an uplink signal or a downlink signal, that is, when the signal filtering system is applied to an access network device, the target signal may include an uplink signal received by the access network device, or the target signal may include a downlink signal to be sent by the access network device.

[0107] Herein, the access network device is taken as an example as a base station. The base station may include multiple cells that provide services for the terminal device. Depending on the specific application scenario, the base station may also be called an access point, or may be a device in the access network that communicates with the wireless terminal device through one or more sectors on the air interface, or other names. The access network device may be used to interchange received air frames with Internet Protocol (IP) packets, and serve as a router between the wireless terminal device and the rest of the access network, wherein the rest of the access network may include an Internet Protocol (IP) communication network. The access network device may also coordinate the attribute management of the air interface. For example, the access network device involved in the embodiments of the present application may be an access network device (Base TransceiverStation, BTS) in the Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA), or an access network device (NodeB) in Wide-band Code Division Multiple Access (WCDMA), or an evolutionary access network device (eNB or e-NodeB) in the long term evolution (LTE) system, a 5G base station (gNB) in the 5G network architecture (next generation system), or a home evolved Node B (HeNB), a relay node, a home base station (femto), a pico base station (pico), etc., which is not limited in the embodiments of the present application. In some network structures, the access network device may include a centralized unit (CU) node and a distributed unit (DU) node, and the centralized unit and the distributed unit may also be arranged geographically separately.

[0108] The terminal device may be a device that provides voice and / or data connectivity to a user, a handheld device with a wireless connection function, or other processing devices connected to a wireless modem. In different systems, the names of the terminal devices may also be different. For example, in a 5G system, the terminal device may be called a user equipment (UE). The wireless terminal device may communicate with one or more core networks (CN) via a radio access network (RAN). The wireless terminal device may be a mobile terminal device, such as a mobile phone (or "cellular" phone) and a computer with a mobile terminal device. For example, it may be a portable, pocket-sized, handheld, computer-built-in or vehicle-mounted mobile device that exchanges language and / or data with a wireless access network. For example, personal communication service (PCS) phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDA) and other devices. The wireless terminal device may also be referred to as a system, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, an access point, a remote terminal device, an access terminal device, a user terminal device, a user agent, and a user device, but is not limited in the embodiments of the present application.

[0109] DSP100 is used for reading at least one first data stored in a first storage address address from a second port 201 based on the first port 101 whenever a data point is stored in the first memory 200, and reading at least one second data stored in a second address from a fourth port 202 based on the third port 102, and reading an N-order filter coefficient from a sixth port 301 based on the fifth port 103, and performing a target operation on the first data and the second data based on the N-order filter coefficient to obtain and output filtered data corresponding to a data point.

[0110] The target operation may include a pre-addition operation, a multiplication operation, and an accumulation operation.

[0111] In any embodiment of the present application, in order to improve the reading speed of data points and to be able to access any storage address in the first memory 200, the first memory 200 may be a BRAM (Block Random Access Memory).

[0112] In any embodiment of the present application, in order to improve the stability of stored data and prevent the data from being modified or deleted, the second memory 300 may be a ROM.

[0113] In summary, the signal filtering system provided in the embodiment of the present application stores N-order filter coefficients through the second memory 300; stores each data point obtained by sampling the target signal through the first memory 200; and reads at least one first data stored in the first address from the second port 201 based on the first port 101 through the DSP 100 whenever a data point is stored in the first memory 200, and reads at least one second data stored in the second address from the fourth port 202 based on the third port 102, and reads the N-order filter coefficients from the sixth port 301 based on the fifth port 103, and performs a target operation on the first data and the second data based on the N-order filter coefficients to obtain and output the filtered data corresponding to a data point. Thus, it is possible to implement filtering processing of the target signal using only one first memory, one second memory and one DSP, and reduce resource occupancy. That is, in the present application, the target signal can be filtered based on a serial processing method, and the occupancy rate of DSP resources and LUT resources is low.

[0114] In any embodiment of the present application, the N-order filter coefficients can be symmetric coefficients. When N is an even number, the second memory 300 is used to store N / 2 filter coefficients, and / or, when N is an odd number, the second memory 300 is used to store (N+1) / 2 filter coefficients.

[0115] In any embodiment of the present application, the data point obtained by the i-th sampling can be stored in the first memory 200 at address [(i mod N) -1], where mod is a modulo operation and i is a positive integer. When N is an even number, the DSP 100 can be used to perform the following operations:

[0116] 1. When the data point obtained by the i-th sampling is stored in the address [(i mod N) - 1] in the first memory 200, the first data stored in each first address is read from the second port 201 based on the first port 101; wherein the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}.

[0117] For example, taking N=6 as an example, in the first sampling, the first addresses read may include: address1, address2, address3; in the second sampling, the first addresses read may include: address2, address3, address4; in the third sampling, the first addresses read may include: address3, address4, address5, etc., which are not listed here one by one.

[0118] 2. Read the second data stored in each second address from the fourth port 202 based on the third port 102; wherein the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N], ..., address[(i+N / 2)mod N].

[0119] For example, taking N=6 as an example, in the first sampling, the first address read may include: address0, address5, address4; in the second sampling, the first address read may include: address1, address0, address5; in the third sampling, the first address read may include: address2, address1, address0, etc., which are not listed here one by one.

[0120] 3. Based on the fifth port 103 , read N / 2 filter coefficients from the sixth port 301 .

[0121] 4. According to the N / 2 filter coefficients, a target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0122] The target operation may include a pre-addition operation, a multiplication operation, and an accumulation operation.

[0123] In the embodiment of the present application, DSP100 can perform N / 2 iterations according to N / 2 filter coefficients, the first data stored at the read first address, and the second data stored at the read second address, and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0124] Among them, the first iterative process may include: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficients to obtain the output of the first iterative process.

[0125] The j-th iteration process may include: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iteration process; performing a multiplication operation on the pre-addition result of the j-th iteration process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iteration process; performing an accumulation operation on the output of the j-1-th iteration process and the intermediate result of the j-th iteration process to obtain the output of the j-th iteration process; wherein j=2, 3,…, N / 2.

[0126] As an example, taking N=6 as an example, the second memory 300 is used to store the first-order filter coefficient H0, the second-order filter coefficient H1, and the third-order filter coefficient H2. For the first sampling, that is, i=1, the pre-addition result of the first iteration process is: the first data stored at address1 + the second data stored at address0 = 0 + d0 = d0, and the output of the first iteration process is: d0*H0; the pre-addition result of the second iteration process is: the first data stored at address2 + the second data stored at address5 = 0 + 0 = 0, the intermediate result of the second iteration process is: 0*H1 = 0, and the output of the second iteration process is: d0*H0 + 0*H1 = d0*H0; the pre-addition result of the third iteration process is: the first data stored at address3 + the second data stored at address4 = 0 + 0 = 0, the intermediate result of the third iteration process is: 0*H2 = 0, and the output of the third iteration process is: d0*H0 + 0*H2 = d0*H0. That is, the filtered data corresponding to the data point obtained by the first sampling can be: d0*H0.

[0127] Similarly, when i=2, the filtered data corresponding to the data point obtained by the second sampling can be: d1*H0+d0*H1.

[0128] When i=3, the filtered data corresponding to the data point obtained by the third sampling may be: d2*H0+d1*H1+d2*H2.

[0129] When i=4, the filtered data corresponding to the data point obtained by the fourth sampling may be: d3*H0+d2*H1+(d1+d0)*H2.

[0130] When i=5, the filtered data corresponding to the data point obtained by the fifth sampling may be: d4*H0+(d3+d0)*H1+(d2+d1)*H2.

[0131] When i=6, the filtered data corresponding to the data point obtained by the sixth sampling may be: (d5+d0)*H0+(d4+d1)*H1+(d3+d2)*H2.

[0132] When i=7, the filtered data corresponding to the data point obtained by the 7th sampling can be: (d6+d1)*H0+(d5+d2)*H1+(d4+d3)*H2.

[0133] When i=8, the filtered data corresponding to the data point obtained by the 8th sampling may be: (d7+d2)*H0+(d6+d3)*H1+(d5+d4)*H2.

[0134] When i=9, the filtered data corresponding to the data point obtained by the 9th sampling can be: (d8+d3)*H0+(d7+d4)*H1+(d6+d5)*H2. The filtered data corresponding to each data point obtained by subsequent sampling are not listed here one by one.

[0135] As an application scenario, N=6, the first port 101 of the DSP 100 is the dsp_a terminal, the third port 102 of the DSP 100 is the dsp_d terminal, the first memory 200 is a BRAM, the second port 201 of the first memory 200 is the B terminal, the fourth port 202 of the first memory 200 is the A terminal, and the second memory 300 is a ROM. The structure of the signal filtering system can be as follows: Figure 3 As shown in FIG. DSP is used to complete the pre-addition operation, the multiplication coefficient operation and the accumulation operation.

[0136] Figure 3 In the data sampling rate, the data sampling rate is 1.92MHz (megahertz, that is, every For example, if a valid data point is sampled per second and the working clock of the signal filtering system is 491.52 MHz, the serial processing method may include the following steps:

[0137] Among them, the clock period of the working clock is The sampling period of the data point = clock period * 256, that is,

[0138] Step A, for a data stream with a sampling rate of 1.92 MHz (referred to as the target signal in this application) under a working clock of 491.52 MHz, the data format is that there is a valid data sampling point (referred to as a data point in this application) every 256 clock cycles, and the data format is as follows: Figure 4 As shown, clock refers to the working clock, x_hd represents the plug, and x(n) represents the target signal.

[0139] Step B, after sampling the target signal x(n), the sampled data points are stored in the real dual-port BRAM, where the depth of the BRAM is 6 and the width is the data bit width of the data point. The storage address of the first sampled data point stored in the BRAM is addr0, the storage address of the second sampled data point stored in the BRAM is addr1, and so on. The storage address of the sixth sampled data point stored in the BRAM is addr5, and the storage address of the seventh sampled data point stored in the BRAM is addr0, overwriting the original data point, and the storage address of the eighth sampled data point stored in the BRAM is addr1, and so on to complete the storage of all data points. The first 6 sampled data points are stored in the BRAM as Table 3.

[0140] Table 3 Storage address of data points in BRAM

[0141] addr5 d5 addr4 d4 addr3 d3 addr2 d2 addr1 d1 addr0 d0

[0142] Step C, read data from the A and B terminals of the BRAM at the same time, respectively reading the data points multiplied by the first half of the filter coefficients and the data points multiplied by the second half of the filter coefficients (the coefficients are the filter coefficients stored in the ROM), as the input of the DSP, input to the DSP_D terminal and the DSP_A terminal. The BRAM outputs the data point corresponding to the read address after two clock cycles, and the timing relationship is as follows Figure 5 shown.

[0143] in, Figure 5 When the data point d5 obtained by the 6th sampling is stored in the address5 in the BRAM, an example is given based on the data points stored in each storage address read from the dsp_a terminal and the dsp_d terminal.

[0144] Step D, Figure 3The ROM in the BRAM is used to store the third-order filter coefficients of the FIR filter (H0, H1 and H2 respectively). While reading the BRAM, the ROM read address is generated. The ROM outputs the corresponding filter coefficients after two clock cycles and is aligned with the data points output by the BRAM as the input of the DSP.

[0145] In step E, DSP completes the main operations of the FIR filter, including pre-addition, multiplication and accumulation. In the present application, the operation completed by DSP is (D+A)*B+P, where D and A are the outputs of the BRAM obtained in step C, B is the output of the ROM obtained in step D, P is the output of the DSP, and +P represents the accumulation of the output.

[0146] It should be noted that the DSP input port also has a P-end clearing operation, that is, before each multiplication and accumulation operation, the P-end needs to be cleared to clear the result of the previous multiplication and accumulation operation.

[0147] In summary, the processing delay of DSP is 4 clocks, and the timing diagram is as follows Figure 6 shown.

[0148] in, Figure 6 The dsp_pout in the figure is the output terminal of the DSP (i.e., the output of the signal filtering system), dsp_pout_en is the enable signal corresponding to the data, and dsp_p_clr ​​refers to clearing, that is, before the DSP performs each multiplication and accumulation operation, the P terminal of the DSP needs to be cleared once, and the result of the previous calculation cannot be accumulated into the current calculation.

[0149] Pout5 is the filtered data corresponding to the data point d5 obtained by the 6th sampling, that is, Pout5 = (d5 + d0) * H0 + (d4 + d1) * H1 + (d3 + d2) * H2, and Pout6 is the filtered data corresponding to the data point d6 obtained by the 7th sampling, that is, Pout6 = (d6 + d1) * H0 + (d5 + d2) * H1 + (d4 + d3) * H2, H0 is the first-order filter coefficient, H1 is the second-order filter coefficient, and H2 is the third-order filter coefficient.

[0150] In any embodiment of the present application, the data point obtained by the i-th sampling can be stored in the first memory 200 at address [(i mod N) -1], where mod is a modulo operation and i is a positive integer. When N is an odd number, the DSP 100 can be used to perform the following operations:

[0151] 1) When the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory 200, the first data stored in each first address is read from the second port 201 based on the first port 101; wherein the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N-1) / 2] mod N}.

[0152] For example, taking N=7 as an example, in the first sampling, the first addresses read may include: address1, address2, address3, address4; in the second sampling, the first addresses read may include: address2, address3, address4, address5; in the third sampling, the first addresses read may include: address3, address4, address5, address6, etc., which are not listed here one by one.

[0153] 2) Reading the second data stored at each second address from the fourth port 202 based on the third port 102, wherein the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N]..., address[(i+(N+1) / 2)mod N].

[0154] For example, taking N=7 as an example, in the first sampling, the first address read may include: address0, address6, address5; in the second sampling, the first address read may include: address1, address0, address6; in the third sampling, the first address read may include: address2, address1, address0, etc., which are not listed here one by one.

[0155] 3) Based on the fifth port 103 , (N+1) / 2 filter coefficients are read from the sixth port 301 .

[0156] 4) According to (N+1) / 2 filter coefficients, a target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0157] The target operation may include a pre-addition operation, a multiplication operation, and an accumulation operation.

[0158] In the embodiment of the present application, DSP100 can perform (N+1) / 2 iterations according to (N+1) / 2 filter coefficients, the first data stored at the read first address, and the second data stored at the read second address, and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0159] Among them, the first iterative process may include: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficients to obtain the output of the first iterative process.

[0160] The kth iteration process may include: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain the pre-addition result of the kth iteration process, performing a multiplication operation on the pre-addition result of the kth iteration process according to the kth order filter coefficient to obtain the intermediate result of the kth iteration process, and performing an accumulation operation on the output of the k-1th iteration process and the intermediate result of the kth iteration process to obtain the output of the kth iteration process; wherein k=2,3,…,(N-1) / 2.

[0161] The last iterative process may include: performing a multiplication operation on the first data stored in the read address{[(i mod N)+(N-1) / 2]mod N} according to the (N+1) / 2th order filter coefficient to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0162] As an example, taking N=7 as an example, the second memory 300 is used to store the first-order filter coefficient H0, the second-order filter coefficient H1, the third-order filter coefficient H2, and the fourth-order filter coefficient H3. The filtered data corresponding to the data point obtained by the first sampling can be: d0*H0.

[0163] The filtered data corresponding to the data point obtained by the second sampling can be: d1*H0+d0*H1.

[0164] The filtered data corresponding to the data point obtained by the third sampling can be: d2*H0+d1*H1+d2*H2.

[0165] The filtered data corresponding to the data point obtained by the fourth sampling can be: d3*H0+d2*H1+d1*H2+d0*H3.

[0166] The filtered data corresponding to the data point obtained by the 5th sampling can be: d4*H0+d3*H1+(d2+d0)*H2+d1*H3.

[0167] The filtered data corresponding to the data point obtained by the 6th sampling can be: d5*H0+(d4+d0)*H1+(d3+d1)*H2+d2*H3.

[0168] The filtered data corresponding to the data point obtained by the 7th sampling can be: (d6+d0)*H0+(d5+d1)*H1+(d4+d2)*H2+d3*H3.

[0169] The filtered data corresponding to the data point obtained by the 8th sampling can be: (d7+d1)*H0+(d6+d2)*H1+(d5+d3)*H2+d4*H3.

[0170] The filtered data corresponding to the data point obtained by the 9th sampling can be: (d8+d2)*H0+(d7+d3)*H1+(d6+d4)*H2+d5*H3. The filtered data corresponding to each data point obtained by subsequent sampling are not listed here one by one.

[0171] In summary, serial processing can be used to implement signal filtering in NB_IOT cells, greatly reducing the use of DSP resources and LUT resources. That is, when the sampling rate of the carrier signal is relatively low, only one real dual-port RAM, one ROM and one DSP are needed to implement the FIR filter function, and the resource occupation is low.

[0172] Figure 7 A flowchart of a signal filtering method provided in an embodiment of the present application.

[0173] The signal filtering method of the embodiment of the present application can be executed by the DSP100 in the above embodiment.

[0174] like Figure 7 As shown, the signal filtering method may include the following steps:

[0175] Step S701, whenever a data point is stored in the first memory, first data stored in at least one first storage address address is read from the first memory; wherein the data point is obtained by sampling a target signal, and the storage depth of the first memory is N.

[0176] Wherein, N is a positive integer greater than 1.

[0177] Step S702: read second data stored at least one second address from the first memory.

[0178] Step S703: read N-th order filter coefficients from the second memory.

[0179] Step S704: Based on the N-th order filter coefficient, a target operation is performed on the first data and the second data to obtain and output filtered data corresponding to a data point.

[0180] In any embodiment of the present application, the N-order filter coefficients are symmetric coefficients. When N is an even number, the second memory is used to store N / 2 filter coefficients, and / or when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients.

[0181] In any one of the embodiments of the present application, the data point obtained by the i-th sampling is stored in the first memory at address [(i mod N)-1], where mod is a modulo operation and i is a positive integer.

[0182] In any embodiment of the present application, the target operation includes a pre-addition operation, a multiplication operation and an accumulation operation.

[0183] In any embodiment of the present application, when N is an even number and the data point obtained by the i-th sampling is stored in the first memory at address [(i mod N)-1], for step S601, the first address read by DSP100 includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}, for step S602, the second address read by DSP100 includes: address [(i + N - 1) mod N], address [(i + N - 2) mod N], address [(i + N - 3) mod N], ..., address [(i + N / 2) mod N].

[0184] For step S703, DSP100 reads N / 2 filter coefficients from the second memory 300. For step S704, DSP100 can perform a target operation on the first data stored at the read first address and the second data stored at the read second address according to the N / 2 filter coefficients to obtain the filtered data corresponding to the data point obtained by the i-th sampling.

[0185] In any embodiment of the present application, when N is an even number, DSP100 can perform N / 2 iterations according to N / 2 filter coefficients, the first data stored at the read first address, and the second data stored at the read second address, and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0186] Among them, the first iterative process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficient to obtain the output of the first iterative process.

[0187] The j-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iteration process, performing a multiplication operation on the pre-addition result of the j-th iteration process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iteration process, and performing an accumulation operation on the output of the j-1-th iteration process and the intermediate result of the j-th iteration process to obtain the output of the j-th iteration process; wherein j=2, 3,…, N / 2.

[0188] In any embodiment of the present application, when N is an odd number and the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, for step S601, the first address read by DSP100 includes: address(i mod N), address{[(i mod N)+1]mod N}, address{[(i mod N)+2]mod N}, …, address{[(i mod N)+(N-1) / 2]mod N}; for step S602, the second address read by DSP100 includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N]…, address[(i+(N+1) / 2)mod N].

[0189] For step S703, DSP100 reads (N+1) / 2 filter coefficients from the second memory 300. For step S704, DSP100 can perform a target operation on the first data stored at the read first address and the second data stored at the read second address according to the (N+1) / 2 filter coefficients to obtain the filtered data corresponding to the data point obtained by the i-th sampling.

[0190] In any embodiment of the present application, when N is an odd number, DSP100 can perform (N+1) / 2 iterations according to (N+1) / 2 filter coefficients, the first data stored at the read first address, and the second data stored at the read second address, and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0191] Among them, the first iterative process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficient to obtain the output of the first iterative process.

[0192] The kth iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain the pre-addition result of the kth iteration process, performing a multiplication operation on the pre-addition result of the kth iteration process according to the kth order filter coefficient to obtain the intermediate result of the kth iteration process, and performing an accumulation operation on the output of the k-1th iteration process and the intermediate result of the kth iteration process to obtain the output of the kth iteration process; wherein k=2,3,…,(N-1) / 2.

[0193] The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(imodN)+(N-1) / 2]mod N} according to the (N+1) / 2th order filter coefficient to obtain the intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0194] In any one of the embodiments of the present application, the first memory is a block random access memory BRAM, and the second memory is a read-only memory ROM.

[0195] In any embodiment of the present application, the signal filtering method can be applied to an access network device, and the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

[0196] It should be noted that the explanation of the signal filtering system in the aforementioned embodiment is also applicable to the signal filtering method in this embodiment, and the implementation principle is similar, which will not be elaborated here.

[0197] The signal filtering method of the embodiment of the present application stores N-order filter coefficients through the second memory; stores each data point obtained by sampling the target signal through the first memory; and reads at least one first data stored at a first address from the first memory and at least one second data stored at a second address from the first memory through the DSP whenever a data point is stored in the first memory, and reads the N-order filter coefficients from the second memory, and performs a target operation on the first data and the second data based on the N-order filter coefficients to obtain and output the filtered data corresponding to a data point. Thus, it is possible to filter the target signal using only one first memory, one second memory and one DSP, and reduce resource occupancy. That is, in the present application, the target signal can be filtered based on a serial processing method, and the occupancy rate of DSP resources and LUT resources is low.

[0198] The technical solution provided in the embodiment of the present application can be applicable to a variety of systems, especially 5G systems. For example, the applicable system can be a global system of mobile communication (Global System of Mobile communication, referred to as GSM) system, code division multiple access (Code Division Multiple Access, referred to as CDMA) system, wideband code division multiple access (Wideband Code Division Multiple Access, referred to as WCDMA) general packet radio service (General Packet Radio Service, referred to as GPRS) system, long term evolution (long term evolution, referred to as LTE) system, LTE frequency division duplex (Frequency Division Duplex, referred to as FDD) system, LTE time division duplex (time division duplex, referred to as TDD) system, advanced long term evolution (Long Term Evolution Advanced, referred to as LTE-A) system, Universal Mobile Telecommunication System (Universal Mobile Telecommunication System, referred to as UMTS), Worldwide interoperability for Microwave Access (Worldwide interoperability for Microwave Access, referred to as WiMAX) system, 5G new air interface (NewRadio, referred to as NR) system, etc. These various systems include terminals and network equipment. The system may also include a core network part, such as an evolved packet system (EPS), a 5G system (5GS), etc.

[0199] With the above Figure 7 Corresponding to the signal filtering method provided in the embodiment, the present application also provides a signal filtering device. Figure 7 The signal filtering method provided in the embodiment corresponds to the signal filtering method, so the implementation method of the signal filtering method is also applicable to the signal filtering device provided in the embodiment of the present application, and will not be described in detail in the embodiment of the present application.

[0200] Figure 8 A schematic diagram of the structure of a signal filtering device provided in an embodiment of the present application.

[0201] like Figure 8 As shown, the signal filtering device 800 can be applied to the DSP 100 in the above embodiment, and includes: a first reading unit 810 , a second reading unit 820 , a third reading unit 830 and an execution unit 840 .

[0202] Among them, the first reading unit 810 is used to read the first data stored in at least one first storage address address from the first memory each time a data point is stored in the first memory; wherein the data point is obtained by sampling the target signal, and the storage depth of the first memory is N, and N is a positive integer greater than 1.

[0203] The second reading unit 820 is configured to read second data stored at least one second address from the first memory.

[0204] The third reading unit 830 is used to read the N-th order filter coefficients from the second memory.

[0205] The execution unit 840 is used to perform a target operation on the first data and the second data based on the N-th order filter coefficient to obtain and output filtered data corresponding to a data point.

[0206] In any embodiment of the present application, the N-order filter coefficients are symmetric coefficients. When N is an even number, the second memory is used to store N / 2 filter coefficients, and / or when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; the data point obtained by the i-th sampling is stored in the first memory at address[(i mod N)-1], where mod is a modulo operation, where i is a positive integer; the target operation includes a pre-addition operation, a multiplication operation, and an accumulation operation.

[0207] In any embodiment of the present application, when N is an even number and the data point obtained by the i-th sampling is stored in the first memory at address [(i mod N)-1], the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}; the second address includes: address [(i + N - 1) mod N], address [(i + N - 2) mod N], address [(i + N - 3) mod N], ..., address [(i + N / 2) mod N].

[0208] The third reading unit 830 is specifically used to read N / 2 filter coefficients from the second memory.

[0209] The execution unit 840 is specifically used to perform a target operation on the first data stored at the first address and the second data stored at the second address according to the N / 2 filter coefficients, so as to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0210] In any one of the embodiments of the present application, the execution unit 740 is specifically used to: execute N / 2 iterations according to N / 2 filter coefficients, the first data stored at the read first address, and the second data stored at the read second address; and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0211] Among them, the first iterative process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficient to obtain the output of the first iterative process.

[0212] The j-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iteration process, performing a multiplication operation on the pre-addition result of the j-th iteration process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iteration process, and performing an accumulation operation on the output of the j-1-th iteration process and the intermediate result of the j-th iteration process to obtain the output of the j-th iteration process; wherein j=2, 3,…, N / 2.

[0213] In any embodiment of the present application, when N is an odd number and the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N-1) / 2] mod N}; the second address includes: address [(i + N-1) mod N], address [(i + N-2) mod N], address [(i + N-3) mod N] ..., address [(i + (N + 1) / 2) mod N].

[0214] The third reading unit 830 is specifically used to read (N+1) / 2 filter coefficients from the second memory.

[0215] The execution unit 840 is specifically used to perform a target operation on the first data stored at the first address and the second data stored at the second address according to (N+1) / 2 filter coefficients to obtain filtered data corresponding to the data point obtained by the i-th sampling.

[0216] In any one of the embodiments of the present application, the execution unit 840 is specifically used to: execute (N+1) / 2 iterations according to (N+1) / 2 filter coefficients, the first data stored at the read first address, and the second data stored at the read second address; and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0217] Among them, the first iterative process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficient to obtain the output of the first iterative process.

[0218] The kth iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain the pre-addition result of the kth iteration process, performing a multiplication operation on the pre-addition result of the kth iteration process according to the kth order filter coefficient to obtain the intermediate result of the kth iteration process, and performing an accumulation operation on the output of the k-1th iteration process and the intermediate result of the kth iteration process to obtain the output of the kth iteration process; wherein k=2,3,…,(N-1) / 2.

[0219] The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(imodN)+(N-1) / 2]mod N} according to the (N+1) / 2th order filter coefficient to obtain the intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0220] In any one of the embodiments of the present application, the first memory is a block random access memory BRAM, and the second memory is a read-only memory ROM.

[0221] In any embodiment of the present application, the signal filtering device 800 can be applied to an access network device, and the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

[0222] It should be noted that the signal filtering device provided in the embodiment of the present application can achieve the above Figure 7 All the method steps implemented in the method embodiment can achieve the same technical effect, and the parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0223] In order to implement the above embodiment, the present application also proposes an access network device, wherein the access network device may include a digital signal processor DSP, a first memory and a second memory, wherein the first port of the DSP is connected to the second port of the first memory, the third port of the DSP is connected to the fourth port of the first memory, and the fifth port of the DSP is connected to the sixth port of the second memory; the second memory is used to store N-order filter coefficients; wherein N is a positive integer greater than 1; the storage depth of the first memory is N, and the first memory is used to store each data point obtained by sampling the target signal; the DSP is used to execute the above Figure 7 The signal filtering method shown.

[0224] It should be noted that the access network device provided in the embodiment of the present application can achieve the above Figure 7 All the method steps implemented in the method embodiment can achieve the same technical effect, and the parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0225] In order to implement the above embodiments, the present application also proposes an access network device.

[0226] Fig. 9 A schematic diagram of the structure of an access network device provided in an embodiment of the present application.

[0227] like Fig. 9 As shown, the access network device may include: a transceiver 900 , a processor 910 , and a memory 920 .

[0228] Among them, the memory 920 is used to store computer programs; the transceiver 900 is used to send and receive data under the control of the processor 910; the processor 910 is used to read the computer program in the memory 920 and perform the following operations: whenever a data point is stored in the first memory, read at least one first data stored in a first storage address address from the first memory; wherein the data point is obtained by sampling the target signal, and the storage depth of the first memory is N, and N is a positive integer greater than 1; read at least one second data stored in a second address from the first memory; read the Nth order filter coefficient from the second memory; based on the Nth order filter coefficient, perform the target operation on the first data and the second data to obtain and output the filtered data corresponding to the one data point.

[0229] The transceiver 900 is used to receive and send data under the control of the processor 910 .

[0230] Among them, Fig. 9 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 910 and various circuits of memory represented by memory 920 are linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 900 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, which transmission medium may include a wireless channel, a wired channel, an optical cable, and other transmission media. The processor 910 is responsible for managing the bus architecture and general processing, and the memory 920 may store data used by the processor 910 when performing operations.

[0231] The processor 910 may be a CPU, an ASIC, an FPGA or a CPLD, and the processor 910 may also adopt a multi-core architecture.

[0232] In a possible implementation form of the present application, the N-order filter coefficients are symmetric coefficients, and when N is an even number, the second memory is used to store N / 2 filter coefficients, and / or, when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; the data point obtained by the i-th sampling is stored in the first memory at address[(i mod N)-1], where mod is a modulo operation, where i is a positive integer; the target operation includes a pre-addition operation, a multiplication operation, and an accumulation operation.

[0233] In a possible implementation form of the present application, when N is an even number and the data point obtained by the i-th sampling is stored in address [(i mod N) - 1] in the first memory, the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}; the second address includes: address [(i + N - 1) mod N], address [(i + N - 2) mod N], address [(i + N - 3) mod N], ..., address [(i + N / 2) mod N].

[0234] The processor 910 executes reading N-order filter coefficients from the second memory, specifically: reading N / 2 filter coefficients from the second memory.

[0235] The processor 910 executes the target operation on the first data and the second data based on the N-order filter coefficients to obtain and output the filtered data corresponding to the one data point, specifically: according to the N / 2 filter coefficients, the target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain the filtered data corresponding to the data point obtained by the i-th sampling.

[0236] In a possible implementation form of the present application, the processor 910 executes the target operation on the first data stored at the first address and the second data stored at the second address according to the N / 2 filter coefficients to obtain the filtered data corresponding to the data point obtained by the i-th sampling, specifically: according to the N / 2 filter coefficients, the first data stored at the first address and the second data stored at the second address, perform N / 2 iterations; and use the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0237] Among them, the first iterative process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficients to obtain the output of the first iterative process.

[0238] The j-th iterative process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iterative process, performing a multiplication operation on the pre-addition result of the j-th iterative process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iterative process, and performing an accumulation operation on the output of the j-1-th iterative process and the intermediate result of the j-th iterative process to obtain the output of the j-th iterative process; wherein j=2, 3,…, N / 2.

[0239] In a possible implementation form of the present application, when N is an odd number and the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, the first address includes: address(i mod N), address{[(i mod N)+1]mod N}, address{[(i mod N)+2]mod N}, …, address{[(i mod N)+(N-1) / 2]mod N}; the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N]…, address[(i+(N+1) / 2)mod N].

[0240] The processor 910 executes reading N-order filter coefficients from the second memory, specifically: reading (N+1) / 2 filter coefficients from the second memory.

[0241] The processor 910 performs the target operation on the first data and the second data based on the N-order filter coefficient to obtain and output the filtered data corresponding to the one data point, specifically: according to the (N+1) / 2 filter coefficients, the target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain the filtered data corresponding to the data point obtained by the i-th sampling.

[0242] In a possible implementation form of the present application, the processor 910 performs a target operation on the first data stored at the first address and the second data stored at the second address according to the (N+1) / 2 filter coefficients to obtain filtered data corresponding to the data point obtained by the i-th sampling, specifically: performing (N+1) / 2 iterations according to the (N+1) / 2 filter coefficients, the first data stored at the first address and the second data stored at the second address; and using the output of the last iteration as the filtered data corresponding to the data point obtained by the i-th sampling.

[0243] Among them, the first iterative process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain the pre-addition result of the first iterative process, and performing a multiplication operation on the pre-addition result of the first iterative process according to the first-order filter coefficients to obtain the output of the first iterative process.

[0244] The kth iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain the pre-addition result of the kth iteration process, performing a multiplication operation on the pre-addition result of the kth iteration process according to the kth order filter coefficient to obtain an intermediate result of the kth iteration process, and performing an accumulation operation on the output of the k-1th iteration process and the intermediate result of the kth iteration process to obtain the output of the kth iteration process; wherein k=2,3,…,(N-1) / 2.

[0245] The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(i mod N)+(N-1) / 2]mod N} according to the filter coefficient of the (N+1) / 2th order to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

[0246] In a possible implementation form of the present application, the first memory is a block random access memory BRAM, and the second memory is a read-only memory ROM.

[0247] In a possible implementation form of the present application, the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

[0248] It should be noted that the access network device provided in the embodiment of the present application can achieve the above Figure 7 All the method steps implemented in the method embodiment can achieve the same technical effect, and the parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0249] It should be noted that each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0250] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program code.

[0251] In order to implement the above embodiments, the present application also proposes a processor-readable storage medium.

[0252] The processor-readable storage medium stores a computer program for causing the processor to execute the present application. Figure 7 The signal filtering method proposed in the embodiment.

[0253] Among them, the processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CD, DVD, BD, HVD, etc.), and semiconductor storage (such as ROM, EPROM, EEPROM, non-volatile memory (NANDFLASH), solid-state drive (SSD)), etc.

[0254] In order to implement the above embodiments, the present application also proposes a computer program product.

[0255] The computer program product includes a computer program which, when executed by a processor, implements the present application. Figure 7 The signal filtering method proposed in the embodiment.

[0256] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0257] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer executable instructions. These computer executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0258] These processor executable instructions may also be stored in a processor readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the processor readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0259] These processor-executable instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0260] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A signal filtering system, characterized in that: include: A digital signal processor DSP, a first memory and a second memory, wherein a first port of the DSP is connected to a second port of the first memory, a third port of the DSP is connected to a fourth port of the first memory, and a fifth port of the DSP is connected to a sixth port of the second memory; The second memory is used to store N-order filter coefficients; wherein N is a positive integer greater than 1; The storage depth of the first memory is N, and the first memory is used to store each data point obtained by sampling the target signal; The DSP is used to read at least one first data stored in a first storage address address from the second port based on the first port whenever a data point is stored in the first memory, and read at least one second data stored in a second address from the fourth port based on the third port, and read the N-order filter coefficient from the sixth port based on the fifth port, and perform a target operation on the first data and the second data based on the N-order filter coefficient to obtain and output the filtered data corresponding to the one data point.

2. The system according to claim 1, characterized in that The N-order filter coefficients are symmetric coefficients, and when N is an even number, the second memory is used to store N / 2 filter coefficients, and / or, when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; The data point obtained by the i-th sampling is stored in the first memory at address [(i mod N) - 1], where mod is a modulo operation and i is a positive integer; The target operation includes a pre-addition operation, a multiplication operation and an accumulation operation.

3. The system according to claim 2, characterized in that When N is an even number, the DSP is specifically used for: When the data point obtained by the i-th sampling is stored in the address [(i mod N) - 1] in the first memory, the first data stored in each first address is read from the second port based on the first port; wherein the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}; Reading the second data stored in each second address from the fourth port based on the third port; wherein the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N], ..., address[(i+N / 2)mod N]; Based on the fifth port, reading N / 2 filter coefficients from the sixth port; According to the N / 2 filter coefficients, a target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

4. The system according to claim 3, characterized in that The DSP is specifically used for: Performing N / 2 iterations according to the N / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; The output of the last iteration process is used as the filtered data corresponding to the data point obtained by the i-th sampling; The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process; The j-th iterative process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iterative process, performing a multiplication operation on the pre-addition result of the j-th iterative process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iterative process, and performing an accumulation operation on the output of the j-1-th iterative process and the intermediate result of the j-th iterative process to obtain the output of the j-th iterative process; wherein j=2, 3,…, N / 2.

5. The system according to claim 2, characterized in that When N is an odd number, the DSP is specifically used for: When the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, the first data stored in each first address is read from the second port based on the first port; wherein the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N-1) / 2] mod N}; Reading the second data stored in each second address from the fourth port based on the third port, wherein the second address includes: address[(i+N-1)mod N], address[(i+N-2)mod N], address[(i+N-3)mod N]..., address[(i+(N+1) / 2)mod N]; Based on the fifth port, read (N+1) / 2 filter coefficients from the sixth port; According to the (N+1) / 2 filter coefficients, a target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

6. The system according to claim 5, characterized in that The DSP is specifically used for: Performing (N+1) / 2 iterations according to the (N+1) / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; The output of the last iteration process is used as the filtered data corresponding to the data point obtained by the i-th sampling; The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process; The k-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain a pre-addition result of the k-th iteration process, performing a multiplication operation on the pre-addition result of the k-th iteration process according to the k-th order filter coefficient to obtain an intermediate result of the k-th iteration process, and performing an accumulation operation on the output of the k-1-th iteration process and the intermediate result of the k-th iteration process to obtain an output of the k-th iteration process; wherein k=2, 3, ..., (N-1) / 2; The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(imod N)+(N-1) / 2]mod N} according to the filter coefficient of the (N+1) / 2th order to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

7. The system according to any one of claims 1 to 6, characterized in that: The first memory is a block random access memory (BRAM), and the second memory is a read-only memory (ROM).

8. The system according to any one of claims 1 to 6, characterized in that: Applied to an access network device, the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

9. A signal filtering method, characterized in that: Applied to DSP, including: Whenever a data point is stored in the first memory, first data stored at least one first storage address address is read from the first memory; wherein the data point is obtained by sampling the target signal, and the storage depth of the first memory is N, where N is a positive integer greater than 1; Reading at least one second data stored at a second address from the first memory; Reading N-th order filter coefficients from the second memory; Based on the N-th order filter coefficients, a target operation is performed on the first data and the second data to obtain and output filtered data corresponding to the one data point.

10. The method according to claim 9, characterized in that The N-order filter coefficients are symmetric coefficients, and when N is an even number, the second memory is used to store N / 2 filter coefficients, and / or, when N is an odd number, the second memory is used to store (N+1) / 2 filter coefficients; The data point obtained by the i-th sampling is stored in the first memory at address [(i mod N) - 1], where mod is a modulo operation and i is a positive integer; The target operation includes a pre-addition operation, a multiplication operation and an accumulation operation.

11. The method according to claim 10, characterized in that When N is an even number, and the data point obtained by the i-th sampling is stored in the first memory at address [(i mod N) - 1], the first address includes: address (i mod N), address {[(i mod N) + 1] mod N}, address {[(i mod N) + 2] mod N}, ..., address {[(i mod N) + (N / 2 - 1)] mod N}; the second address includes: address [(i + N - 1) mod N], address [(i + N - 2) mod N], address [(i + N - 3) mod N], ..., address [(i + N / 2) mod N]; The step of reading the N-th order filter coefficients from the second memory comprises: Reading N / 2 filter coefficients from the second memory; The performing a target operation on the first data and the second data based on the N-order filter coefficient to obtain and output filtered data corresponding to the one data point includes: According to the N / 2 filter coefficients, a target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

12. The method according to claim 11, characterized in that The performing a target operation on the first data stored at the first address and the second data stored at the second address according to the N / 2 filter coefficients to obtain filtered data corresponding to the data point obtained by the i-th sampling includes: Performing N / 2 iterations according to the N / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; The output of the last iteration process is used as the filtered data corresponding to the data point obtained by the i-th sampling; The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process; The j-th iterative process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+j-1]mod N} and the second data stored at the address[(i+Nj)mod N] to obtain the pre-addition result of the j-th iterative process, performing a multiplication operation on the pre-addition result of the j-th iterative process according to the j-th order filter coefficient to obtain the intermediate result of the j-th iterative process, and performing an accumulation operation on the output of the j-1-th iterative process and the intermediate result of the j-th iterative process to obtain the output of the j-th iterative process; wherein j=2, 3,…, N / 2.

13. The method according to claim 10, characterized in that When N is an odd number, and the data point obtained by the i-th sampling is stored in the storage address [(i mod N)-1] in the first memory, the first address includes: address(i mod N), address{[(i mod N)+1] mod N}, address{[(i mod N)+2] mod N}, ..., address{[(i mod N)+(N-1) / 2] mod N}; the second address includes: address[(i+N-1) mod N], address[(i+N-2) mod N], address[(i+N-3) mod N] ..., address[(i+(N+1) / 2) mod N]; The step of reading the N-th order filter coefficients from the second memory comprises: Read (N+1) / 2 filter coefficients from the second memory; The performing a target operation on the first data and the second data based on the N-order filter coefficient to obtain and output filtered data corresponding to the one data point includes: According to the (N+1) / 2 filter coefficients, a target operation is performed on the first data stored at the first address and the second data stored at the second address to obtain filtered data corresponding to the data point obtained by the i-th sampling.

14. The method according to claim 13, characterized in that The performing a target operation on the first data stored at the first address and the second data stored at the second address according to the (N+1) / 2 filter coefficients to obtain filtered data corresponding to the data point obtained by the i-th sampling includes: Performing (N+1) / 2 iterations according to the (N+1) / 2 filter coefficients, the first data stored at the first address, and the second data stored at the second address; The output of the last iteration process is used as the filtered data corresponding to the data point obtained by the i-th sampling; The first iteration process includes: performing a pre-addition operation on the first data stored at the read address (i mod N) and the second data stored at the address [(i+N-1) mod N] to obtain a pre-addition result of the first iteration process, and performing a multiplication operation on the pre-addition result of the first iteration process according to the first-order filter coefficient to obtain an output of the first iteration process; The k-th iteration process includes: performing a pre-addition operation on the first data stored at the read address{[(i mod N)+k-1]mod N} and the second data stored at the address[(i+Nk)mod N] to obtain a pre-addition result of the k-th iteration process, performing a multiplication operation on the pre-addition result of the k-th iteration process according to the k-th order filter coefficient to obtain an intermediate result of the k-th iteration process, and performing an accumulation operation on the output of the k-1-th iteration process and the intermediate result of the k-th iteration process to obtain an output of the k-th iteration process; wherein k=2, 3, ..., (N-1) / 2; The last iterative process includes: performing a multiplication operation on the first data stored in the read address{[(imod N)+(N-1) / 2]mod N} according to the filter coefficient of the (N+1) / 2th order to obtain an intermediate result of the last iterative process, and performing an accumulation operation on the output of the (N-1) / 2th iterative process and the intermediate result of the last iterative process to obtain the output of the last iterative process.

15. The method according to any one of claims 9 to 14, characterized in that: The first memory is a block random access memory (BRAM), and the second memory is a read-only memory (ROM).

16. The method according to any one of claims 9 to 14, characterized in that: Applied to an access network device, the target signal includes an uplink signal received by the access network device, or the target signal includes a downlink signal to be sent by the access network device.

17. A signal filtering device, characterized in that: Applied to DSP, including: A first reading unit is used to read first data stored at least one first storage address address from the first memory whenever a data point is stored in the first memory; wherein the data point is obtained by sampling the target signal, and the storage depth of the first memory is N, where N is a positive integer greater than 1; A second reading unit, configured to read second data stored at least one second address from the first memory; A third reading unit, used for reading N-order filter coefficients from the second memory; An execution unit is used to perform a target operation on the first data and the second data based on the N-th order filter coefficient to obtain and output filtered data corresponding to the one data point.

18. An access network device, characterized in that: include: A digital signal processor DSP, a first memory and a second memory, wherein a first port of the DSP is connected to a second port of the first memory, a third port of the DSP is connected to a fourth port of the first memory, and a fifth port of the DSP is connected to a sixth port of the second memory; The second memory is used to store N-order filter coefficients; wherein N is a positive integer greater than 1; The storage depth of the first memory is N, and the first memory is used to store each data point obtained by sampling the target signal; The DSP is used to execute the method according to any one of claims 9 to 16.

19. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the method according to any one of claims 9 to 16.

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