Signal decoding method and device, electronic equipment and storage medium

Abstract

The invention discloses a signal decoding method and device, electronic equipment and a storage medium, the signal decoding method is applied to a state machine, the signal decoding method comprises the following steps: obtaining a to-be-decoded signal, the to-be-decoded signal comprising a plurality of level signals; and determining the current state of the state machine based on the current input level of the to-be-decoded signal, and decoding the to-be-decoded signal based on the current state. The signal decoding method is based on the algorithm of the state machine, the current state is determined according to the current input level, signal decoding is achieved through conversion among different states, the decoding mode is clear in logic, the fault problems such as program jamming are not prone to occurring, occupation of circuit resources is reduced, and meanwhile communication stability is kept.

Description

Technical Field

[0001] The present application relates to technical fields such as communication transmission and signal decoding, and in particular to a signal decoding method, device, electronic device and storage medium. Background Art

[0002] In the related art, the traditional decoding method uses a programming language to decode bit by bit data. This decoding method has unclear logic and is prone to problems such as freezing. There are also decoding chips, such as the HD1553 chip for automatic encoding and decoding. However, the HD1553 chip is expensive and requires more resources in the circuit. Summary of the invention

[0003] To this end, the purpose of the implementation mode of the present application is to propose a signal decoding method, device, electronic device, storage medium and computer program product, which is based on the algorithm of the state machine, determines the current state according to the current input level, and realizes signal decoding by converting between different states. This decoding method has clear logic, is not prone to program jams and other fault problems, reduces the occupation of circuit resources, and maintains communication stability.

[0004] An embodiment of the present application provides a signal decoding method, which is applied to a state machine, and the method includes: obtaining a signal to be decoded, wherein the signal to be decoded includes multiple level signals; determining a current state of the state machine based on a current input level of the signal to be decoded, and decoding the signal to be decoded based on the current state.

[0005] Exemplarily, the initial state of the state machine is a first preset state, and determining the current state of the state machine based on the current input level of the signal to be decoded includes: when the current state is the first preset state, updating the current state based on the pulse width of the current input level.

[0006] Exemplarily, the signal to be decoded includes high and low synchronization headers, and the updating of the current state based on the pulse width of the current input level includes: when the pulse width of the current input level is within a first preset pulse width interval, updating the current state to a second preset state; when the pulse width of the current input level is within a second preset pulse width interval, updating the current state to a third preset state; otherwise, maintaining the current state as the first preset state; wherein the first preset pulse width interval and the second preset pulse width interval are both associated with the pulse width of the high and low synchronization headers, and the pulse width value of the first preset pulse width interval is smaller than the pulse width value of the second preset pulse width interval.

[0007] Exemplarily, when the current state is the second preset state, the method further includes: when the pulse width of the current input level is within a third preset pulse width interval, updating the current state to the third preset state; otherwise, updating the current state to the first preset state; wherein the third preset pulse width interval is associated with the pulse width of the high and low synchronization heads, and the pulse width value of the third preset pulse width interval is greater than the pulse width value of the second preset pulse width interval.

[0008] Exemplarily, when the current state is the third preset state, the method further includes: when the pulse width of the current input level is within a fourth preset pulse width interval, maintaining the current state as the third preset state; otherwise, updating the current state to the first preset state; wherein the fourth preset pulse width interval is associated with the pulse width of the high and low synchronization heads, and the pulse width value of the first preset pulse width interval is smaller than the pulse width value of the fourth preset pulse width interval.

[0009] Exemplarily, decoding the signal to be decoded based on the current state includes: decoding the current input level based on the current state, saving the decoded current input level, and recording the level number in the current state.

[0010] Exemplarily, after decoding the current input level based on the current state, the method further includes: updating the current input level based on a next level of a signal to be decoded.

[0011] Exemplarily, when the current state is the third preset state, the method further includes: counting the number of levels in the third preset state, and setting a decoding flag when the number of levels is the preset number of levels.

[0012] Exemplarily, the method further includes: in a case where the decoded signal includes the decoding flag, converting the decoded signal based on a preset standard to maintain the same length as that required for communication with the signal to be decoded.

[0013] Exemplarily, the first preset state includes a high sync head state, the second preset state includes a low sync head state, and the third preset state includes a data bit state.

[0014] Another embodiment of the present application provides a signal decoding device, which includes: an acquisition module, used to acquire a signal to be decoded, wherein the signal to be decoded includes multiple level signals; a decoding module, used to determine a current state of a state machine based on a current input level of the signal to be decoded, and decode the signal to be decoded based on the current state.

[0015] Another embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method of any of the above embodiments when executing the computer program.

[0016] Another embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method of any of the above embodiments are implemented.

[0017] Another embodiment of the present application provides a computer program product, which includes instructions. When the instructions are executed by a processor of a computer device, the computer device is enabled to perform the steps of the method of any of the above embodiments.

[0018] In the above implementation, the signal decoding method is applied to a state machine, and the signal decoding method includes: obtaining a signal to be decoded, wherein the signal to be decoded includes multiple level signals; determining the current state of the state machine based on the current input level of the signal to be decoded, and decoding the signal to be decoded based on the current state. The signal decoding method of the present invention is based on the algorithm of the state machine, determines the current state according to the current input level, and realizes signal decoding by switching between different states. The decoding method has clear logic, is not prone to program jamming and other fault problems, reduces the occupation of circuit resources, and maintains communication stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flowchart of a signal decoding method provided in an embodiment of the present application;

[0020] Figure 2 A flowchart of a state machine implementation provided in an embodiment of the present application;

[0021] Figure 3 A flowchart of a signal decoding process provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a signal decoding device provided in an embodiment of the present application;

[0023] Figure 5 A block diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0025] In some examples, the traditional decoding method uses a programming language to decode bit by bit. This decoding method has unclear logic and is prone to problems such as freezing. There are also decoding chips, such as the HD1553 chip for automatic encoding and decoding. However, the HD1553 chip is expensive and requires more resources in the circuit.

[0026] Based on this, the present application proposes a decoding method based on a state machine, which reduces the occupation of circuit resources while maintaining communication stability.

[0027] Figure 1 It is a flowchart of a signal decoding method according to an embodiment of the present application.

[0028] As an example, Figure 1 As shown, the signal decoding method includes:

[0029] S101, obtaining a signal to be decoded, wherein the signal to be decoded includes a plurality of level signals.

[0030] S102, determining the current state of the state machine based on the current input level of the signal to be decoded, and performing decoding processing on the signal to be decoded based on the current state.

[0031] Exemplarily, the above signal decoding method is applied to a state machine. It can be understood that a state machine is a program implementation method that summarizes the operation process of an object into different operation states to generate different feedbacks, and there is a transfer relationship between states. For example, input object A, whose operation state can be divided into 1234. When object A runs in state 1, it gives feedback of state 1. When object A completes the feedback of state 1, it can update its own operation state to 2 and give feedback of state 2. And so on. The last state 4 can correspond to the end behavior of object A, and restore the operation state of A to 1.

[0032] Exemplarily, the signal to be decoded may be a 1553 signal. HD1553 is a serial data transmission standard, which belongs to the power supply communication bus technology. By encoding and decoding the data signal on the power supply bus, it replaces the traditional bus design of power supply signal separation. Due to its stable power supply and data transmission characteristics, HD1553 is widely used as a data transmission standard for drilling measurement instruments. The signal decoding method of the present application can be applied to the data transmission field of drilling measurement instruments to decode the 1553 signal. Of course, the signal decoding method of the present application can also be applied to other fields. The present application does not limit the signal to be decoded. For the convenience of explanation, the following example is taken as the signal to be decoded as a 1553 signal. The signal to be decoded includes multiple level signals. For example, the 1553 signal has at least one level jump in each bit period, that is, in one bit period, the jump edge is used to represent the data bit, wherein the general Manchester code standard is that the falling edge represents data 1 and the rising edge represents data 0. This encoding method ensures the stability of the signal and is conducive to long-distance transmission. A signal to be decoded is input, a current state of the state machine is determined based on a current input level of the signal to be decoded, and decoding processing is performed on the signal to be decoded based on the current state.

[0033] The signal decoding method of the present application is based on a state machine mechanism, and the current state of the state machine is determined according to the current input level of the signal to be decoded. After determining the current state, the signal to be decoded is decoded based on the current state. This state machine mechanism can lock the level signal in a state, the logic is clear, and it is not easy to get stuck, etc., which improves the decoding rate and reduces the response time. The present application is a software program that replaces hardware devices such as decoding chips, reduces the occupation of circuit resources, and simplifies the design of communication circuits. For example, the signal decoding method of the present application is used to decode 1553 signals, and hardware 1553 codec chips can be omitted to save costs.

[0034] Figure 2 It is an implementation flow chart of a state machine of an embodiment of the present application.

[0035] like Figure 2 As shown, the signal to be decoded is input into the state machine as an object, and a state judgment is performed based on the current input level of the signal to be decoded to determine the current state, state processing is performed based on the current state, and state transfer is performed in the current state, and then state judgment is performed again, and this cycle is repeated to achieve decoding of the signal to be decoded.

[0036] As an example, the initial state of the state machine is the first preset state, and the current state of the state machine is determined based on the current input level of the signal to be decoded, including: when the current state is the first preset state, updating the current state based on the pulse width of the current input level.

[0037] Exemplarily, the present application may set the initial state of the state machine to be the first preset state, the state machine initially maintains the first preset state and cyclically waits for the input of the signal to be decoded, and after obtaining the signal to be decoded, updates the current state according to the pulse width of the current input level of the signal to be decoded. It can be understood that the next state is determined according to the pulse width of the current input level of the signal to be decoded. The current state is a constantly changing process.

[0038] As an example, the signal to be decoded includes high and low synchronization heads, and the current state is updated based on the pulse width of the current input level, including: when the pulse width of the current input level is within the first preset pulse width interval, updating the current state to the second preset state; when the pulse width of the current input level is within the second preset pulse width interval, updating the current state to the third preset state; otherwise, maintaining the current state as the first preset state; wherein the first preset pulse width interval and the second preset pulse width interval are both associated with the pulse width of the high and low synchronization heads, and the pulse width value of the first preset pulse width interval is smaller than the pulse width value of the second preset pulse width interval.

[0039] Exemplarily, take the 1553 signal as an example, wherein the 1553 signal has two synchronization heads, the high and low synchronization heads occupy 3 bits, the signal bit occupies 16 bits, and the parity bit occupies 1 bit. In the 1553 signal characteristics, the pulse width of the high synchronization head and the low synchronization head are the same, represented by T. In the default state, the state machine is in the first preset state. When the current input level is received, the next state is determined according to the range of the pulse width of the current input level. When the pulse width of the current input level is within the first preset pulse width interval, the current state is updated to the second preset state. Among them, the first preset pulse width interval is associated with the pulse width of the high and low synchronization heads. For example, the first preset pulse width interval can be [0.25T, 0.75T]. If the pulse width of the current input level meets the first preset pulse width interval, it jumps to the second preset state. When the pulse width of the current input level is within the second preset pulse width interval, the current state is updated to the third preset state, and the second preset pulse width interval is also associated with the pulse width of the high and low synchronization heads. For example, the second preset pulse width interval can be [0.75T, T]. If the pulse width of the current input level meets the second preset pulse width interval, it jumps to the third preset state. If the current input level pulse width is not within the first preset pulse width interval and the second preset pulse width interval, the operating state is kept in the first preset state.

[0040] As an example, the first preset state includes a high sync header state, the second preset state includes a low sync header state, and the third preset state includes a data bit state.

[0041] According to the characteristics of the signal to be decoded, the present application divides the operating state into three states, wherein the first preset state may be a high synchronization head state, the second preset state may be a low synchronization head state, and the third preset state may be a data bit state. In the default state, the state machine is in a high synchronization head state and waits in a loop. In the high synchronization head state, it is determined whether the current input level pulse width is in the first preset pulse width interval, such as [0.25T, 0.75T]. If the current input level pulse width meets the requirements, it jumps to the low synchronization head state. If the current input level pulse width is between the second preset pulse widths, such as [0.75T, T], it jumps to the data bit state. If the level pulse width is not in the above intervals, the operating state is kept in the high synchronization head state.

[0042] As an example, when the current state is the second preset state, the signal decoding method further includes:

[0043] When the pulse width of the current input level is within the third preset pulse width interval, the current state is updated to the third preset state; otherwise, the current state is updated to the first preset state;

[0044] The third preset pulse width interval is associated with the pulse width of the high and low synchronization headers, and the pulse width value of the third preset pulse width interval is greater than the pulse width value of the second preset pulse width interval.

[0045] Exemplarily, when the current state is the second preset state, the next state is determined according to the pulse width of the current input level. When the pulse width of the current input level is within the third preset pulse width interval, the current state is updated to the third preset state, and the third preset pulse width interval is associated with the pulse width of the high and low synchronization heads. For example, the third preset pulse width interval can be [T, 1.5T]. If the pulse width of the current input level is within the third preset pulse width interval, the current state is updated to the third preset state, that is, jump to the third preset state. Otherwise, the current state is updated to the first preset state, that is, return to the first preset state.

[0046] Exemplarily, the first preset state may be a high sync head state, the second preset state may be a low sync head state, and the third preset state may be a data bit state. When the state machine is in the low sync head state, it is determined whether the pulse width of the current input level is in the third preset pulse width interval, for example, [T, 1.5T]. If the level pulse width meets the requirements, it jumps to the data bit state, otherwise the state is updated to the high sync head state.

[0047] As an example, when the current state is the third preset state, the signal decoding method also includes: when the pulse width of the current input level is within the fourth preset pulse width interval, maintaining the current state as the third preset state; otherwise, updating the current state to the first preset state; wherein the fourth preset pulse width interval is associated with the pulse width of the high and low synchronization heads, and the pulse width value of the first preset pulse width interval is smaller than the pulse width value of the fourth preset pulse width interval.

[0048] Exemplarily, when the current state is the third preset state, the next state is determined according to the pulse width of the current input level. When the pulse width of the current input level is within the fourth preset pulse width interval, the current state is maintained as the third preset state, and the fourth preset pulse width interval is associated with the pulse width of the high and low synchronization heads. For example, the fourth preset pulse width interval may be [0.75T, T]. If the pulse width of the current input level is within the fourth preset pulse width interval, the current state is maintained as the third preset state. Otherwise, the current state is updated to the first preset state, that is, the first preset state is returned.

[0049] Exemplarily, the first preset state may be a high sync head state, the second preset state may be a low sync head state, and the third preset state may be a data bit state. When the state machine is in the data bit state, it is determined whether the pulse width of the current input level is in a fourth preset pulse width interval, for example, [0.75T, T]. If the level pulse width meets the requirements, it is maintained in the data bit state, the current input level is updated, and it is continued to be determined whether the pulse width of the current input level is in the fourth preset pulse width interval. If not, the state is updated to the high sync head state.

[0050] As an example, decoding the signal to be decoded based on the current state includes: decoding the current input level based on the current state, saving the decoded current input level, and recording the level number in the current state.

[0051] Exemplarily, a signal to be decoded is input, the current state is determined according to the pulse width of the current input level, the duration of the current state is determined, the current input level is decoded based on the current state, and the decoded current input level is saved. It can be understood that the decoding process is to store the current level in the form of data 0, 1. For example, when the initial state is the first preset state, the current input level is saved, and jumping from the first preset state to the second preset state or jumping to the third preset state corresponds to storing the current input level. It can be understood that the current state is constantly converted, and the level of the signal to be decoded is processed bit by bit. Record the number of levels in the current state. For example, record the number of levels stored in the data bit state. Of course, the number of levels in the high synchronization state and / or the low synchronization head state can also be recorded.

[0052] As an example, after decoding the current input level based on the current state, the signal decoding method further includes: updating the current input level based on the next level of the signal to be decoded.

[0053] Exemplarily, it can be understood that the current input level is constantly changing. The signal decoding method of the present application processes each bit according to the data length of the signal to be decoded. After processing the previous level, the current input level is updated according to the next level of the signal to be decoded, and the next state is determined based on the current input level to achieve continuous conversion between states. The decoding operation is completed through this mechanism of conversion between states. The method of determining the current level with a clear state is more logically simple, which improves the decoding rate and reduces the response time.

[0054] Figure 3 This is a flowchart of signal decoding according to an embodiment of the present application.

[0055] like Figure 3 As shown, the signal to be decoded is input, and the signal to be decoded includes multiple levels. The decoded signal is, for example, a 1553 signal. The first bit of the 1553 signal is a high synchronization head. The high synchronization head state is entered, and the current input level is stored. The current input level is updated according to the next level of the signal to be decoded. The next state is determined according to the current input level. If the condition for jumping to the low synchronization head is met, it jumps to the low synchronization head state and stores the current input level, and continues to process the next level. If the condition for jumping to the data bit state is met, it jumps to the data bit state and stores the current input level. It should be noted that when jumping to the data bit state, if the current input level pulse width meets the condition between [0.75T, T], it is maintained in the data bit state, waiting for the pulse width judgment of the next level. If the pulse width does not meet the condition, it jumps to the high synchronization head state, and the cycle is repeated to complete the decoding of the signal to be decoded.

[0056] As an example, when the current state is the third preset state, the signal decoding method further includes: counting the number of levels in the third preset state, and setting a decoding flag when the number of levels is the preset number of levels.

[0057] Exemplarily, the third preset state may be a data bit state. Since the characteristic of the 1553 signal is 16 bits of information bits, the number of levels in the third preset state is counted. If the number of levels meets the preset number of levels, for example, the number of levels meets 16 bits, it means that the signal is decoded successfully, and a decoding flag may be set to indicate that the decoding is complete.

[0058] Exemplarily, the number of levels in the data bit state is accumulated. If the current level number is equal to the preset level number, it is considered that the current 1553 communication waveform is captured successfully, the decoding flag is set, and the operating state is updated to the high synchronization head state. Otherwise, it is considered that the data bit level capture has failed, and the operating state is updated to the high synchronization head state.

[0059] As an example, the signal decoding method further includes: when the decoded signal includes a decoding flag, converting the decoded signal based on a preset standard to keep the same length as that required for communication of the signal to be decoded.

[0060] Exemplarily, in the case where the decoded signal includes a decoding flag, that is, the decoding is successful, the decoded signal can be converted based on a preset standard, and the preset standard can be a Manchester code standard, wherein the Manchester code standard uses two bits to represent one bit, for example, the Manchester code standard is 32 bits before conversion and 16 bits after conversion. For example, if the decoding flag has been set in the decoded signal, the data can be decoded according to the Manchester code standard, that is, the current 1553 communication data content is finally obtained. And the length of the decoded signal finally obtained is the length required for the communication of the signal to be decoded.

[0061] The signal decoding method of the present application sets a plurality of preset states based on the characteristics of the signal to be decoded, determines the current state of the state machine according to the current input level of the signal to be decoded based on the state machine mechanism, and after determining the current state, decodes the signal to be decoded based on the current state. This state machine mechanism can lock the level signal in a state, has clear logic, is not prone to stuck conditions, improves the decoding rate, reduces the response time, and the present application is a software program that replaces hardware devices such as decoding chips, reduces the occupation of circuit resources, and simplifies the design of communication circuits.

[0062] It should be noted that the present application is not limited to the signal to be decoded, and the method can also be applied to other signals to be decoded. Different states are customized according to the characteristics of different signals to be decoded, so as to realize the signal decoding process through the conversion between states.

[0063] The present application also proposes a signal decoding device.

[0064] As an example, Figure 4 As shown, the signal decoding device includes: an acquisition module 401, used to acquire a signal to be decoded, wherein the signal to be decoded includes multiple level signals; a decoding module 402, used to determine the current state of the state machine based on the current input level of the signal to be decoded, and decode the signal to be decoded based on the current state.

[0065] The application also proposes a computer-readable storage medium.

[0066] In this embodiment, a computer program is stored on a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the above signal decoding method are implemented.

[0067] Figure 5 A block diagram of an electronic device provided for an embodiment of the present application.

[0068] An embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned signal decoding method when executing the computer program.

[0069] like Figure 5 As shown, for ease of understanding, the embodiment of the present application shows a specific electronic device.

[0070] Electronic devices are intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0071] like Figure 5 As shown, the device includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0072] Multiple components in the electronic device are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the electronic device to exchange signals / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0073] The computing unit 501 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods described above, such as the signal decoding method. For example, in some embodiments, the signal decoding method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on an electronic device via ROM 802 and / or a communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, the signal decoding method described above may be executed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the signal decoding method in any other appropriate manner (e.g., by means of firmware).

[0074] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this application, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0075] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0076] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0077] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0078] In addition, the terms "first", "second", etc. used in the embodiments of the present application are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present application can explicitly or implicitly indicate that at least one of the features is included in the embodiment. In the description of the present application, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0079] In this application, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. appearing in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific implementation situation.

[0080] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0081] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A signal decoding method, characterized in that: The method is applied to a state machine, and the method comprises: Acquire a signal to be decoded, wherein the signal to be decoded includes multiple level signals; The current state of the state machine is determined based on the current input level of the signal to be decoded, and the signal to be decoded is decoded based on the current state.

2. The signal decoding method according to claim 1, characterized in that: The initial state of the state machine is a first preset state, and the determining the current state of the state machine based on the current input level of the signal to be decoded includes: When the current state is the first preset state, the current state is updated based on the pulse width of the current input level.

3. The signal decoding method according to claim 2, characterized in that: The signal to be decoded includes a high and a low synchronization header, and the pulse width based on the current input level updates the current state, including: When the pulse width of the current input level is within the first preset pulse width interval, updating the current state to a second preset state; When the pulse width of the current input level is within the second preset pulse width interval, updating the current state to a third preset state; Otherwise, maintaining the current state as the first preset state; The first preset pulse width interval and the second preset pulse width interval are both associated with the pulse width of the high and low synchronization headers, and the pulse width value of the first preset pulse width interval is smaller than the pulse width value of the second preset pulse width interval.

4. The signal decoding method according to claim 3, characterized in that: When the current state is the second preset state, the method further includes: When the pulse width of the current input level is within a third preset pulse width interval, updating the current state to the third preset state; Otherwise, updating the current state to the first preset state; The third preset pulse width interval is associated with the pulse width of the high and low synchronization heads, and the pulse width value of the third preset pulse width interval is greater than the pulse width value of the second preset pulse width interval.

5. The signal decoding method according to claim 3, characterized in that: When the current state is the third preset state, the method further includes: When the pulse width of the current input level is within a fourth preset pulse width interval, maintaining the current state as the third preset state; Otherwise, updating the current state to the first preset state; The fourth preset pulse width interval is associated with the pulse width of the high and low synchronization heads, and the pulse width value of the first preset pulse width interval is smaller than the pulse width value of the fourth preset pulse width interval.

6. The signal decoding method according to any one of claims 1 to 5, characterized in that: The method further comprises: performing decoding processing on the signal to be decoded based on the current state, comprising: The current input level is decoded based on the current state, the decoded current input level is saved, and the level number in the current state is recorded.

7. The signal decoding method according to claim 6, characterized in that: After decoding the current input level based on the current state, the method further includes: The current input level is updated based on the next level of the signal to be decoded.

8. The signal decoding method according to any one of claims 3 to 5, characterized in that: When the current state is the third preset state, the method further includes: The number of levels in the third preset state is counted, and when the number of levels is a preset number of levels, a decoding flag is set.

9. The signal decoding method according to claim 8, characterized in that: The method further comprises: In the case where the decoded signal includes the decoding flag, the decoded signal is converted based on a preset standard to keep the same length as that required for communication with the signal to be decoded.

10. The signal decoding method according to claim 3 or 4, characterized in that: The first preset state includes a high sync header state, the second preset state includes a low sync header state, and the third preset state includes a data bit state.

11. A signal decoding device, characterized in that: The device comprises: An acquisition module, used for acquiring a signal to be decoded, wherein the signal to be decoded includes a plurality of level signals; The decoding module is used to determine the current state of the state machine based on the current input level of the signal to be decoded, and decode the signal to be decoded based on the current state.

12. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method described in any one of claims 1 to 10 when executing the computer program.

13. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 10 are implemented.

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