Radiation detector, integrated circuit, and radiation detection method

Abstract

A radiation detector according to the present invention is provided with a plurality of pixel circuits provided corresponding to each of a plurality of pixels arranged in a predetermined direction, and each having at least one detection system for reading carriers from the corresponding pixel. At least one detection system includes: a counter that counts a hit number of radiation; a first register for holding first data, which is a count value obtained by the counter; a second register that holds second data; an adder that generates third data by adding the first data and the second data; and a third register that holds third data. The second data is third data transferred from a third register of a pixel circuit provided corresponding to a pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits.

Description

Technical Field

[0001] One aspect of the present disclosure relates to a radiation detector, an integrated circuit, and a radiation detection method. Background Art

[0002] A radiation detector is known, which includes: a conversion unit, which includes a plurality of pixels that generate carriers according to incident radiation, and the plurality of pixels are arranged in a predetermined direction; and a plurality of pixel circuits (integrated circuits), which are respectively arranged corresponding to the plurality of pixels and read out carriers from the corresponding pixels (for example, refer to patent documents 1 to patent document 3). In the above-mentioned radiation detector, the plurality of pixel circuits are connected to each other, and each pixel circuit reads out the number of hits of the radiation counted by the counter in the pixel circuit of the previous stage, and loads it into the counter in each pixel circuit. Moreover, each pixel circuit adds the number of hits newly counted by the counter in each pixel circuit to the number of hits of the pixel circuit of the previous stage loaded. By performing the above actions in each pixel circuit in sequence, a TDI (Time Delay Integration) action is realized.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 4532743

[0006] Patent Document 2: Japanese Patent Publication No. 2009-540282

[0007] Patent Document 3: Japanese Patent Publication No. 2014-93616 Summary of the invention

[0008] The technical problem that the invention is intended to solve

[0009] However, in the radiation detectors described in Patent Documents 1 to 3, the period required for loading is the non-operation period of the counter, during which the operation of counting the number of hits of radiation is stopped. The longer the non-operation period of the counter is, the lower the radiation detection efficiency of the radiation detector is.

[0010] An object of one aspect of the present disclosure is to provide a radiation detector, an integrated circuit, and a radiation detection method that improve the detection efficiency of radiation.

[0011] Solutions to technical problems

[0012] A radiation detector according to one aspect of the present disclosure is: [1] "A radiation detector comprising: a conversion unit including a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixels being arranged in a predetermined direction; and a plurality of pixel circuits that are arranged corresponding to each of the plurality of pixels and each having at least one detection system that reads out carriers from the corresponding pixel, the at least one detection system comprising: a comparator that compares a first signal based on the amount of the carriers with a threshold value and outputs a second signal when the first signal exceeds the threshold value; a counter that counts the number of the second signals; a first register that holds a count value obtained by the counter, i.e., first data; a second register that holds second data; an adder that generates third data by adding the first data to the second data; and a third register that holds the third data, the second data being the third data transferred from the third register of the pixel circuit that is arranged corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits."

[0013] In the radiation detector described in [1] above, each detection system of a plurality of pixel circuits has a second register, an adder, and a third register. The second register holds the third data transferred from the third register in the pixel circuit corresponding to the pixel adjacent to the corresponding pixel as the second data. The adder generates the third data by adding the count value obtained by the counter, i.e., the first data, to the second data. The third register holds the generated third data. With such a configuration, it is not necessary to write (load) the count value in the pixel circuit of the previous stage into the counter of each pixel circuit. Therefore, the non-operating period of the counter can be shortened. Therefore, the operating period of the counter in each pixel circuit, i.e., the proportion of the period during which radiation can be detected in the entire operating period of the pixel circuit can be increased. In addition, in the case where the first register is not provided, the count value cannot be updated until the count value is maintained in the register of the subsequent stage (e.g., the third register), and the problem of the counter stopping during this period will occur. Since such a problem does not occur by providing the first register, the non-operating period of the counter can be further shortened. As described above, according to the radiation detector described in [1] above, it is possible to provide a radiation detector that improves the efficiency of radiation detection by increasing the ratio of the period during which radiation can be detected to the entire operation period.

[0014] The radiation detector of one aspect of the present disclosure may also be: [2] "A radiation detector as described in [1] above, wherein the adder includes at least one of the first register, the second register and the third register, and the at least one detection system has other registers other than the first register, the second register and the third register in addition to the adder."

[0015] The radiation detector of one aspect of the present disclosure may also be: [3] "A radiation detector as described in [1] or [2] above, wherein in each of the plurality of pixel circuits, the area of ​​the first region occupied by the analog circuit is larger than the area of ​​the second region occupied by the digital circuit, the analog circuit includes the comparator, and the digital circuit includes the counter, the first register, the second register, the adder, and the third register." In the first region, in order to suppress characteristic deviations of each component, at least one of the size of the component and the mounting interval between the components is sometimes changed. According to the radiation detector described in [3], since the area of ​​the first region is larger, the design freedom of the analog circuit can be improved. In addition, according to the radiation detector described in [1] above, the function of transferring the third data between pixel circuits (TDI function in the digital circuit) can be relatively simply constructed. Therefore, as with the radiation detector described in [3], the area of ​​the digital circuit can be reduced.

[0016] The radiation detector according to one aspect of the present disclosure may also be: [4] "a radiation detector as described in [3] above, wherein the area of ​​the first region occupies more than half of the total area of ​​each of the plurality of pixel circuits." According to the radiation detector described in [4], since the area of ​​the first region is large, the degree of freedom in designing the analog circuit can be increased.

[0017] The radiation detector of one aspect of the present disclosure may also be: [5] "A radiation detector as described in any one of [1] to [4] above, wherein each of the plurality of pixel circuits has a plurality of detection systems as the at least one detection system, and the threshold value of the comparator of the plurality of detection systems is a value different for each of the detection systems." According to the radiation detector described in [5], the radiation energy levels (the amount of carriers generated) of the radiation can be divided into a plurality of levels for each detection system for detection.

[0018] The radiation detector of one aspect of the present disclosure may also be: [6] "a radiation detector as described in [5] above, wherein the adder of the plurality of detection systems is provided individually for each of the detection systems." According to the radiation detector described in [6], detection processing can be performed in parallel in the plurality of detection systems. Therefore, the processing speed can be increased.

[0019] The radiation detector of one aspect of the present disclosure may also be: [7] "a radiation detector as described in [5] above, wherein the adders of the plurality of detection systems are shared by the plurality of detection systems." According to the radiation detector described in [7], since the adders are shared, the circuit area can be reduced.

[0020] The radiation detector of one aspect of the present disclosure may also be: [8] "A radiation detector as described in any one of [1] to [7] above, wherein the number of bits of the second register is equal to or greater than the sum of the number of bits of the first register and the number of bits obtained by expressing the number of the plurality of pixel circuits in binary, and the number of bits of the adder is the same as the number of bits of the second register." According to the radiation detector described in [8], since the number of bits of the adder is the same as the number of bits of the second register, addition processing can be performed in parallel for each bit. Therefore, the processing speed can be improved.

[0021] The radiation detector of one aspect of the present disclosure may also be: [9] "A radiation detector as described in any one of [1] to [8] above, wherein the number of bits of the second register is equal to or greater than the sum of the number of bits of the first register and the number of bits obtained by expressing the number of the plurality of pixel circuits in binary; the number of bits of the adder is less than the number of bits of the second register, and the adder repeatedly adds and outputs a portion of the bits of the first data in the first register and a portion of the bits of the second data in the second register corresponding to the portion of the bits, until all the bits of the first data are added." According to the radiation detector described in [9], since the number of bits of the adder is less than the number of bits of the second register, the circuit area can be reduced. On the other hand, the adder repeatedly adds and outputs a portion of the bits of the first data and a portion of the bits of the second data, until all the bits of the first data are added. Thus, even if the number of bits is small, addition processing can be performed.

[0022] The radiation detector of one aspect of the present disclosure may also be:

[10] "A radiation detector as described in [9] above, wherein the number of bits of the adder is 1 bit, and the adder has a fourth register for holding a carry signal." According to the radiation detector described in

[10] , the circuit area can be reduced, and even if the number of bits of the adder is 1 bit, carry calculation can be performed.

[0023] The radiation detector of one aspect of the present disclosure may also be:

[11] "A radiation detector as described in any one of [1] to

[10] above, wherein each of the plurality of pixel circuits further comprises: a charge sharing countermeasure circuit which, when dispersing the carriers generated by the incidence of the radiation to two or more of the pixel circuits and reading them out, determines the pixel corresponding to the position where the radiation is incident, corrects the amount of carriers in the pixel and evaluates it, or ignores the incidence of the radiation." According to the radiation detector described in

[11] , the reduction in energy resolution and image blurring caused by charge sharing can be suppressed.

[0024] The radiation detector of one aspect of the present disclosure may also be:

[12] "A radiation detector as described in any one of [1] to

[11] above, wherein the plurality of pixel circuits further include a switching unit for switching between an action of transferring the third data along the prescribed direction and an action of transferring the third data in a direction opposite to the prescribed direction." According to the radiation detector described in

[12] , data can be transferred bidirectionally in the plurality of pixel circuits.

[0025] The radiation detector of one aspect of the present disclosure may also be:

[13] "A radiation detector as described in any one of [1] to

[12] above, wherein each of the plurality of pixel circuits further comprises a shaping circuit disposed in front of the comparator, and the shaping circuit reduces the time constant of the first signal." According to the radiation detector described in

[13] , the response speed of the comparator can be increased by the shaping circuit. Thus, the non-operation period of the counter can be further shortened.

[0026] The radiation detector of one aspect of the present disclosure may also be:

[14] "A radiation detector as described in any one of [1] to

[13] above, wherein the plurality of pixel circuits include a first pixel circuit region and a second pixel circuit region; and the timing of holding the first data in the first register is different in the first pixel circuit region and the second pixel circuit region." According to the radiation detector described in

[14] , the risk of crosstalk can be reduced by making the timing of holding the first data in the first register different between the first pixel circuit region and the second pixel circuit region.

[0027] The radiation detector of one aspect of the present disclosure may also be:

[15] "As described in

[14] above, the radiation detector further comprises: a power supply that supplies a power supply voltage to each of the plurality of pixel circuits via a transmission line; and a control unit that sends a hold signal to each of the plurality of pixel circuits via a signal line, wherein the second pixel circuit region and the first pixel circuit region are arranged along a predetermined direction, and the direction in which the transmission line branches intersects with the direction in which the signal line branches and the predetermined direction." According to the radiation detector described in

[15] , since both the first pixel circuit region and the second pixel circuit region exist on each branched transmission line, the risk of crosstalk can be further reduced.

[0028] An integrated circuit according to one aspect of the present disclosure is:

[16] "An integrated circuit comprising: a plurality of pixel circuits, each of which is arranged corresponding to a plurality of pixels that generate carriers in response to incident radiation, and each of which has at least one detection system for reading out carriers from the corresponding pixel, wherein the plurality of pixels are arranged along a specified direction, and the at least one detection system comprises: a comparator that compares a first signal based on the amount of the carriers with a threshold value and outputs a second signal when the first signal exceeds the threshold value; a counter that counts the number of the second signal; a first register that holds the count value obtained by the counter, i.e., first data; a second register that holds the second data; an adder that generates third data by adding the first data to the second data; and a third register that holds the third data, wherein the second data is the third data transferred from the third register of the pixel circuit that is arranged corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits."

[0029] In the integrated circuit described in

[16] above, each detection system of a plurality of pixel circuits has a second register, an adder and a third register. The second register holds the third data transferred from the third register in the pixel circuit corresponding to the pixel adjacent to the corresponding pixel as the second data. The adder generates the third data by adding the count value obtained by the counter, i.e., the first data, to the second data. The third register holds the generated third data. With such a configuration, it is not necessary to write (load) the count value in the pixel circuit of the previous stage into the counter of each pixel circuit. Therefore, the non-operation period of the counter can be shortened. Therefore, the proportion of the operation period of the counter in each pixel circuit, i.e., the period during which radiation can be detected, in the entire operation period of the pixel circuit can be increased. In addition, in the case where the first register is not set, the count value cannot be updated until the count value is held in the register of the subsequent stage (e.g., the third register), and the problem of the counter stopping during this period will occur. Since such a problem will not occur by setting the first register, the non-operation period of the counter can be further shortened. As described above, according to the integrated circuit described in the above

[16] , it is possible to provide an integrated circuit that improves the efficiency of radiation detection by increasing the proportion of the period during which radiation can be detected in the entire operation period.

[0030] One aspect of the present disclosure is a radiation detection method as follows:

[17] "A radiation detection method, comprising: a step of generating carriers in response to incident radiation in a plurality of pixels arranged along a predetermined direction; a step of reading out carriers from the corresponding pixels in a plurality of pixel circuits respectively arranged corresponding to the plurality of pixels; a step of comparing a first signal based on the amount of the carriers with a threshold value and outputting a second signal when the first signal exceeds the threshold value; a step of counting the number of the second signals; a step of storing the count value obtained by the counting step, i.e., the first data, in a first register; a step of storing the second data in a second register; a step of generating a third data by adding the first data to the second data; and a step of storing the third data in a third register, wherein the second data is the third data transferred from the third register of the pixel circuit corresponding to the pixel adjacent to the corresponding pixel in each of the plurality of pixel circuits."

[0031] The radiation detection method described in

[17] above comprises: a step of retaining the third data transferred from the third register in the pixel circuit corresponding to the pixel adjacent to the corresponding pixel as the second data in the second register; a step of generating the third data by adding the count value obtained by the counting step, that is, the first data, to the second data; and a step of retaining the generated third data in the third register. Here, the counting step is performed by the counter of each pixel circuit. With such a configuration, it is not necessary to write (load) the count value in the pixel circuit of the previous stage into the counter of each pixel circuit. Therefore, the non-operation period of the counter can be shortened. Therefore, the proportion of the operation period of the counter in each pixel circuit, that is, the period during which radiation can be detected, in the entire operation period of the pixel circuit can be increased. In addition, in the case where the first register is not provided, the count value cannot be updated until the count value is maintained in the register of the subsequent stage (for example, the third register), and the problem of the counter stopping during this period will occur. Since such a problem does not occur by providing the first register, the non-operation period of the counter can be further shortened. As described above, according to the radiation detection method described in

[17] above, it is possible to provide a radiation detection method that improves the efficiency of radiation detection by increasing the ratio of the period during which radiation can be detected to the entire operation period.

[0032] [Effects of the Invention]

[0033] According to one aspect of the present invention, it is possible to provide a radiation detector, an integrated circuit, and a radiation detection method that improve the efficiency of radiation detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a diagram showing the configuration of the radiation detector according to the first embodiment.

[0035] Figure 2 It is shown Figure 1 A top view showing the arrangement of a plurality of pixel electrode sections on the back side of a conversion section.

[0036] Figure 3 It is shown Figure 1 A diagram showing the configuration of each pixel circuit.

[0037] Figure 4 yes Figure 1 Circuit block diagram of each pixel circuit shown.

[0038] Figure 5 It is a diagram showing an example of charge sharing correction.

[0039] Figure 6 yes Figure 4 An example of a circuit diagram of a counter is shown.

[0040] Figure 7 yes Figure 4 Circuit diagram of the pixel circuit shown.

[0041] Figure 8 It is shown Figure 7 A diagram showing the detailed structure of the pixel circuit shown.

[0042] Fig. 9 It is used to illustrate Figure 7 A diagram showing TDI operation in a pixel circuit is shown.

[0043] Fig.10 It is used to illustrate Figure 7 A diagram showing TDI operation in a pixel circuit is shown.

[0044] Fig.11 It is used to illustrate Figure 7 A diagram showing TDI operation in a pixel circuit is shown.

[0045] Fig.12 It is used to illustrate Figure 7 A diagram showing TDI operation in a pixel circuit is shown.

[0046] Fig.13 yes Figure 7 An example of a circuit diagram of an adder is shown.

[0047] Fig.14 yes Figure 7 An example of a circuit diagram of each register shown.

[0048] Fig.15 It is a diagram for explaining a radiation detection method using a radiation detector.

[0049] Fig.16 This is a diagram showing the detailed structure of a pixel circuit of the pixel circuit according to the second embodiment.

[0050] Fig.17 yes Fig.16 An example of a circuit diagram of a selector circuit is shown.

[0051] Fig.18 It is used to illustrate Fig.16 The diagram shows the configuration of the input and output terminals of an adder.

[0052] Fig.19 This is a diagram for explaining the TDI operation in the pixel circuit according to the second embodiment.

[0053] Fig. 20 This is a diagram for explaining the TDI operation in the pixel circuit according to the second embodiment.

[0054] Fig.21 This is a diagram for explaining the TDI operation in the pixel circuit according to the second embodiment.

[0055] Fig. 22 : is a circuit block diagram of a pixel circuit involved in a modification.

[0056] Fig.23 yes Fig. 22 Circuit diagram of the pixel circuit shown.

[0057] Fig.24 yes Fig. 22 Circuit diagram of the pixel circuit shown.

[0058] Fig.25 It is a diagram for explaining the transfer direction of the third data in the pixel circuit of the modification example.

[0059] Fig.26 It is a diagram for explaining the transfer direction of the third data in the pixel circuit of the modification example.

[0060] Fig. 27 It is a diagram for explaining the transfer direction of the third data in the pixel circuit of the modification example.

[0061] Fig.28 It is a diagram for explaining the transfer direction of the third data in the pixel circuit of the modification example.

[0062] Fig.29 It is a diagram for explaining the transfer direction of the third data in the pixel circuit of the modification example.

[0063] Fig.30 This is a diagram showing the detailed structure of a pixel circuit of a pixel circuit according to a modified example.

[0064] Fig.31 This is a diagram showing the detailed structure of a pixel circuit of a pixel circuit according to a modified example.

[0065] Fig.32 This is a diagram showing an example of a conversion unit, a power supply, and a control unit.

[0066] Fig.33 (a) to (c) are diagrams for explaining the first hold signal, the counter operation signal, and the counter reset signal.

[0067] Fig.34 This is a diagram showing an example of a plurality of pixel circuits divided into a first pixel circuit region and a second pixel circuit region.

[0068] Fig.35 (a) to (d) are diagrams for explaining the first hold signal and the second hold signal.

[0069] Fig.36(a) and (b) are diagrams for explaining an example of a first pixel circuit region and a second pixel circuit region.

[0070] Fig.37 (a) and (b) are diagrams for explaining an example of a first pixel circuit region and a second pixel circuit region.

[0071] Fig.38 (a) and (b) are diagrams for explaining an example of a first pixel circuit region and a second pixel circuit region.

[0072] Fig.39 (a) to (e) are diagrams for explaining the first hold signal, the second hold signal, and the third hold signal.

[0073] Fig.40 This is a diagram for explaining an example of a first pixel circuit region, a second pixel circuit region, and a third pixel circuit region.

[0074] Explanation of symbols:

[0075] 1 ... radiation detector; 2 ... conversion unit; 2c ... pixel; 4 ... integrated circuit; 40, 40-1, 40-2, 40-3, 40A ... pixel circuit; 41 ... first region; 42 ... second region; 44a, 44b ... shaping circuit; 45 ... charge sharing countermeasure circuit; 46 ... comparator; 47 ... counter; 48a, 48a-1, 48a-2 ... first register; 48b, 48b-1, 48b-2 ... second register; 48c, 48d ... second register; 8c-1, 48c-2, 48e...adders; 48d, 48d-1, 48d-2...third register; 48i...fourth register; 49...detection system; 401...first pixel circuit area; 402...second pixel circuit area; 51...signal line; 61...transmission line; D1...first data; D2...second data; D3...third data; PS1...first pulse signal; PS2...second pulse signal; R...radiation; Th...threshold. DETAILED DESCRIPTION

[0076] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are given to the same or corresponding parts in each drawing, and repeated descriptions are omitted.

[0077] [First embodiment]

[0078] Figure 1 1 is a diagram showing the structure of the radiation detector 1 according to the first embodiment. Figure 1 As shown, the radiation detector 1 includes a conversion unit 2 , a plurality of pixel electrode units 3 , and an integrated circuit 4 .

[0079] The conversion part 2 is a block-shaped or layered component that absorbs radiation R to generate carriers. The radiation R is, for example, X-rays, neutron rays, α rays, β rays, or γ rays. The conversion part 2 is composed of a material including, for example, at least one of CdTe, CdZnTe, GaAs, InP, TlBr, HgI2, PbI2, Si, Ge, and a-Se. The conversion part 2 extends along a plane intersecting the incident direction of the radiation R. The conversion part 2 has a front face 2a and a back face 2b facing oppositely. In one example, the front face 2a is parallel to the back face 2b. When observed from the incident direction of the radiation R, the planar shape of the conversion part 2 is, for example, a rectangle or a square. The length of the long side of the conversion part 2 when the planar shape of the conversion part 2 is a rectangle, or the length of one side of the conversion part 2 when the planar shape of the conversion part 2 is a square, for example, is in the range of 1 mm to 500 mm. On the front face 2a, a bias electrode 21 as a common electrode is provided in a manner covering the entire surface of the front face 2a. The radiation R that has passed through the bias electrode 21 is incident on the front surface 2 a.

[0080] The pixel electrode sections 3 are conductive films provided on the back surface 2b of the conversion section 2. The pixel electrode sections 3 are, for example, metal films. A high bias voltage is applied between the pixel electrode sections 3 and the bias electrode 21 to deplete the conversion section 2. Figure 2 It is a top view showing the configuration of multiple pixel electrode portions 3 on the back side 2b of the conversion portion 2. The multiple pixel electrode portions 3 are arranged in a two-dimensional shape of M rows × N columns when viewed from the incident direction of the radiation R. M and N are integers greater than 2. The two-dimensional shape is, for example, a matrix shape. Each of the M×N pixel electrode portions 3 forms a pixel 2c of M rows and N columns in the conversion portion 2. In other words, in the conversion portion 2, the multiple pixels 2c are arranged along the row direction and the column direction. In the multiple pixels 2c, carriers are generated in response to the incident radiation R. Each pixel electrode portion 3 collects the carriers generated in the corresponding pixel 2c. The radiation detector 1 performs a TDI action that accumulates the carriers generated in each pixel 2c along the column direction, i.e., the first direction A1 (prescribed direction) for each column. Figure 2 In the example of FIG. 2 , the radiation detector 1 accumulates carriers generated in the pixel 2 c - 1 , the pixel 2 c - 2 , the pixel 2 c - 3 , . . . , the pixel 2 c -M.

[0081] Refer again Figure 1. The integrated circuit 4 has a plurality of pixel circuits (M×N pixel circuits) 40 connected to each of the plurality of pixel electrode portions 3. The integrated circuit 4 is implemented, for example, by an ASIC (Application Specific Integrated Circuit). Each of the plurality of pixel circuits 40 is electrically connected to each of the plurality of pixel electrode portions 3 through a bump joint B1. Each of the plurality of pixel circuits 40 is provided corresponding to each of the plurality of pixels 2c. Each pixel circuit 40 reads out carriers from the corresponding pixel 2c. Specifically, each pixel circuit 40 detects carriers collected in the corresponding pixel electrode portion 3. Each pixel circuit 40 counts the number of hits of radiation based on the detected carriers.

[0082] Figure 3 It is shown Figure 1 The figure shows the structure of each pixel circuit 40. When observed from the incident direction of the radiation R, the planar shape of each pixel circuit 40 is, for example, a square. The length of one side is, for example, 50μm to 250μm. Each pixel circuit 40 is composed of a first region 41 occupied by an analog circuit and a second region 42 occupied by a digital circuit. The area of ​​the first region 41 is larger than the area of ​​the second region 42. The area of ​​the first region 41 is more than half of the overall area of ​​each pixel circuit 40. In the center of each pixel circuit 40, a pad P is provided in a manner opposite to each pixel electrode portion 3. The pad P is electrically connected to each pixel electrode portion 3 through a bump joint B1.

[0083] Figure 4 yes Figure 1 The circuit block diagram of each pixel circuit 40 shown in FIG. 1 includes an amplifier 43, shaping circuits 44a, 44b, a charge sharing countermeasure circuit 45, and a comparator 46. The second area 42 includes a counter 47, a pixel circuit 48, and an AND circuit AN. Each pixel circuit 40 includes a detection system 49. A detection system 49 includes a comparator 46, a counter 47, a pixel circuit 48, and an AND circuit AN. A detection system 49 reads carriers from the corresponding pixel 2c and counts the number of hits of the radiation R.

[0084] The wiring connection of the circuit blocks of each pixel circuit 40 is described. The input terminal of the amplifier 43 is connected to the pad P. The output terminal of the amplifier 43 is connected to the input terminal of the shaping circuit 44a and the input terminal of the shaping circuit 44b, respectively. The output terminal of the shaping circuit 44a is connected to the charge sharing countermeasure circuit 45. The charge sharing countermeasure circuit 45 is connected to one of the input terminals of the AND circuit AN. The output terminal of the shaping circuit 44b is connected to the inverting input terminal or the non-inverting input terminal of the comparator 46. The output terminal of the comparator 46 is connected to the other input terminal of the AND circuit AN. The output terminal of the AND circuit AN is connected to the input terminal of the counter 47. The output terminal of the counter 47 is connected to the pixel point circuit 48.

[0085] The amplifier 43 outputs a first pulse signal PS1 (first signal) corresponding to the amount of carriers collected in each pixel electrode portion 3. The first pulse signal PS1 is, for example, a voltage pulse having a voltage value proportional to the amount of carriers. The first pulse signal PS1 has a specified time constant and requires a certain rise time before reaching a voltage value proportional to the amount of carriers. The rise time is less than tens of ns, for example, 10ns. The shaping circuits 44a and 44b remove the high-frequency components and low-frequency components of the first pulse signal PS1. By reducing the time constant of the first pulse signal PS1, the fall time of the first pulse signal PS1 becomes steeper.

[0086] The shaping circuit 44 b , the charge sharing countermeasure circuit 45 , and the comparator 46 perform charge sharing correction. Figure 5 is a diagram showing an overview of charge sharing correction. Figure 5 , the figure shows the pixel electrode portion 3e corresponding to the pixel circuit 40 to which the pixel electrode portion 3e belongs, and eight pixel electrode portions 3a, 3b, 3c, 3d, 3f, 3g, 3h, and 3i surrounding the pixel electrode portion 3e. The charge sharing correction includes an energy correction c1 and a position correction c2.

[0087] The energy correction c1 is described with reference to the pixel electrode portion 3e. First, the first pulse signal PS1 is copied to the adjacent pixels (pixel electrode portions 3a, 3b, 3d) of the pixel electrode portion 3e by a replica circuit (not shown) provided in the rear stage of the amplifier 43 (copy processing c11). Next, the shaping circuit 44b adds the replica signal from the adjacent pixels (pixel electrode portions 3f, 3h, 3i) to the first pulse signal PS1 of the pixel electrode portion 3e, a total of 4 pixels, to generate a corrected first pulse signal PS1 (summing processing c12). Thus, the shaping circuit 44b corrects the amount of carriers by adding the amount of carriers collected in the pixel electrode portion 3e corresponding to the pixel circuit 40 to which it belongs to the sum of the amount of carriers collected in the three pixel electrode portions 3f, 3h, 3i adjacent to the pixel electrode portion 3. In the shaping circuit 44b, the number of pixel electrode portions to which the amount of carriers is added is not limited to 3. For example, the shaping circuit 44b may also correct the amount of carriers by adding the amount of carriers collected in the pixel electrode portion 3e corresponding to the pixel circuit 40 to which it belongs to the sum of the amounts of carriers collected in the eight pixel electrode portions 3a, 3b, 3c, 3d, 3f, 3g, 3h, and 3i adjacent to the pixel electrode portion 3e. Alternatively, the shaping circuit 44b may also correct the amount of carriers by adding the amount of carriers collected in the pixel electrode portion 3e corresponding to the pixel circuit 40 to which it belongs to the sum of the amounts of carriers collected in two pixel electrode portions (for example, the pixel electrode portions 3f and 3h).

[0088] Next, the comparator 46 discriminates the corrected first pulse signal PS1 by comparing the corrected first pulse signal PS1 with the threshold value Th (discriminate processing c13). The corrected first pulse signal PS1 is input from the shaping circuit 44b to one of the inverting input terminal and the non-inverting input terminal of the comparator 46, and the threshold value Th is input to the other. The comparator 46 compares the corrected first pulse signal PS1 with the threshold value Th. Specifically, when the value of the corrected first pulse signal PS1 is greater than the threshold value Th, the comparator 46 outputs the second pulse signal PS2 (second signal). The second pulse signal PS2 is, for example, a high-level voltage signal. It corresponds to Figure 5 In the judgment process c13 of "H". When the value of the first pulse signal PS1 is less than the threshold value Th, the comparator 46 does not output the second pulse signal PS2. This corresponds to Figure 5The output of the second pulse signal PS2 once can be called a hit of radiation once. Next, the OR circuit (not shown) provided in the front stage of the counter 47 calculates the logical OR of the second pulse signal PS2 of the pixel electrode portion 3e and the second pulse signal PS2 of the adjacent pixels (pixel electrode portions 3a, 3b, 3d) of the pixel electrode portion 3e (OR processing c14). The OR processing c14 is implemented to eliminate the ambiguity caused by the combination of the charge sharing mode and the addition set during the summing processing c12.

[0089] The position correction c2 is described with reference to the pixel electrode portion 3e. When the carriers generated by the incident radiation R are dispersed to two or more pixel electrode portions 3 and collected, the charge sharing countermeasure circuit 45 determines the pixel electrode portion 3 that collects the most carriers as the pixel electrode portion 3 corresponding to the position where the radiation R is incident. Specifically, the charge sharing countermeasure circuit 45 copies the first pulse signal PS1 output from the shaping circuit 44a to the adjacent pixels (pixel electrode portions 3a, 3b, 3c, 3d, 3f, 3g, 3h, 3i), and compares the copied signal received from the adjacent pixels (pixel electrode portions 3a, 3b, 3c, 3d, 3f, 3g, 3h, 3i) with the first pulse signal PS1 of the pixel electrode portion 3e (comparison processing c21). Furthermore, the charge sharing countermeasure circuit 45 determines whether the pixel electrode portion 3e corresponding to the pixel circuit 40 to which it belongs is the pixel electrode portion 3 corresponding to the position where the radiation R is incident. Specifically, the charge sharing countermeasure circuit 45 determines whether the magnitude of the first pulse signal PS1 of the pixel electrode portion 3e is greater than that of all adjacent pixels (selection process c22). When it is determined that the magnitude of the first pulse signal PS1 of the pixel electrode portion 3e is greater than that of the first pulse signal PS1 of all adjacent pixels, the output signal of the charge sharing countermeasure circuit 45 from the pixel electrode portion 3e, that is, the third pulse signal PS3, becomes "H". The charge sharing countermeasure circuit 45 can be implemented by, for example, an electronic circuit including a logic circuit.

[0090] After the energy correction c1 and the position correction c2, the AND circuit AN provided at the front stage of the counter 47 calculates the logical product of the second pulse signal PS2 obtained by the OR process and the third pulse signal PS3 output from the charge sharing countermeasure circuit 45. When the third pulse signal PS3 is "H", the second pulse signal PS2 of the pixel electrode portion 3e becomes active (AND process c3) and is sent to the counter 47 at the back stage. In other words, in the selection process c22, when it is determined that the pixel electrode portion 3e corresponding to the pixel circuit 40 to which it belongs is the pixel electrode portion 3 corresponding to the position where the radiation R is incident, the charge sharing countermeasure circuit 45 sets the output of the comparator 46 to be valid. On the other hand, when it is determined that the pixel electrode portion 3e corresponding to the pixel circuit 40 to which it belongs is not the pixel electrode portion 3 corresponding to the position where the radiation R is incident, the charge sharing countermeasure circuit 45 sets the output of the comparator 46 to be invalid. The addition operation of the shaping circuit 44b and the charge sharing countermeasure circuit 45 can be omitted from the pixel circuit 40. In this case, the uncorrected first pulse signal PS1 is input from the shaping circuit 44 b to one of the inverting input terminal and the non-inverting input terminal of the comparator 46 .

[0091] The counter 47 counts the number of the second pulse signals PS2 output. In other words, the counter 47 counts the number of hits of the radiation. The counted value is output to the pixel circuit 48. The counter 47 is, for example, a 4-bit up counter or a down counter. Figure 6 In the example, 4-stage flip-flops F1 to F4 are used. In the case of an up-counting counter, the output ( / Q) of the 1st-stage flip-flop F1 is connected to the input (CLK) of the 2nd-stage flip-flop F2. Similarly, the output ( / Q) of the 2nd-stage flip-flop F2 is connected to the input (CLK) of the 3rd-stage flip-flop F3. The 3rd-stage flip-flop F3 is the same as the 4th-stage flip-flop F4. The output ( / Q) of the 1st-stage flip-flop F1 switches at the falling timing of CLK. The output ( / Q) of the 2nd-stage flip-flop F2 switches at the falling timing of Q0. The output ( / Q) of the 3rd-stage flip-flop F3 switches at the falling timing of Q1. The output ( / Q) of the 4th-stage flip-flop F4 switches at the falling timing of Q2.

[0092] Figure 7 yes Figure 44 is a circuit diagram of a pixel circuit 48 shown in FIG. The pixel circuit 48 includes a first register 48a, a second register 48b, an adder 48c, and a third register 48d. The first register 48a holds the count value output from the counter 47, that is, the first data D1. The first data D1 indicates the number of second pulse signals PS2 counted by the counter 47. The wiring between the counter 47 and the first register 48a is, for example, a parallel wiring including wiring having the same number of bits as the maximum count value of the counter 47. In this case, the first register 48a simultaneously holds the first data D1 of all bits at any timing. The wiring between the counter 47 and the first register 48a may also be a series wiring.

[0093] The second register 48b holds the second data D2. The adder 48c generates the third data D3 by adding the first data D1 and the second data D2. The third register 48d holds the generated third data D3. The plurality of pixel circuits 40 transfer the third data D3 between the pixel circuits 40 corresponding to the pixels 2c, as a signal along the plurality of pixels 2c. Figure 2 The specific means for accumulating carriers in the first direction A1 (prescribed direction) shown in FIG. That is, the TDI operation for accumulating carriers generated in each pixel 2c along the first direction A1 is performed by transferring the third data D3 in each pixel circuit 40 corresponding to each pixel 2c. Figure 2 To illustrate. The pixel circuit 40 corresponding to the pixel 2c-1 transfers the third data D3 to the pixel circuit 40 corresponding to the pixel 2c-2 adjacent to the pixel 2c-1. And, the pixel circuit 40 corresponding to the pixel 2c-2 maintains the transferred third data D3 as the second data D2. Thereafter, the pixel circuit 40 corresponding to the pixel 2c-2 adds the first data D1 maintained in the first register 48a of the pixel circuit 40 corresponding to the pixel 2c-2 to the second data D2. On top of this, the pixel circuit 40 corresponding to the pixel 2c-2 maintains the added value as the third data D3, and transfers the third data D3 to the pixel circuit 40 corresponding to the pixel 2c-3 adjacent to the pixel 2c-2. This action is repeated until the pixel circuit 40 corresponding to the pixel 2c-M of the last row. Here, the second data D2 is a pixel 2c (in the first direction A1) adjacent to the corresponding pixel 2c in each of the plurality of pixel circuits 40. Figure 2 In the figure, when viewed from the pixel 2c-2, the third data D3 is transferred from the third register 48d of the pixel circuit 40 corresponding to the pixel 2c-1).

[0094] Figure 8 It is shown Figure 7 A0 to A0 are diagrams showing the detailed configuration of the pixel circuit 48. X-1Indicates the bit of the first register 48a. The number of bits of the first register 48a is the maximum count value of the counter 47, that is, X bits. Y+X-1 Indicates the bits of the second register 48b. S0 to S Y+X-1 Indicates the bit of the third register 48d. The number of bits of the second register 48b and the third register 48d is X+Y bits. Here, Y is a value obtained by representing the number of rows of the plurality of pixel circuits 40, i.e., M, in binary. For example, when the number of rows of M is 64, Y=6. The X+Y bits are the maximum number of bits required to add the first data D1 of each pixel circuit 40 to the third data D3 (the second data D2 in each pixel circuit 40) transferred from the third register 48d. The number of bits of the adder 48c is X+Y bits, which is the same number as the number of bits of the second register 48b and the third register 48d. In the present embodiment, the adder 48c performs addition processing in parallel for each bit. For example, the adder 48c adds the lowest bit A0 of the first register 48a and the lowest bit B0 of the second register 48b to the lowest bit 0 of the adder 40c, and keeps the added value in the lowest bit S0 of the third register 48d. The adder 40c performs such addition processing in parallel on all bits (least significant bit 0 to most significant bit Y+X-1).

[0095] Figures 9 to 12 It is used to illustrate Figure 7 The TDI operation of the pixel circuit 40 is shown in FIG. 4. Since the adder 48c performs addition processing in parallel from the 1st bit to the (X+Y)th bit, Figures 9 to 12 In , adder 48c is labeled as 0~Y+X-1. Figures 9 to 12 In the embodiment, the pixel circuit 40-1, the pixel circuit 40-2, and the pixel circuit 40-3 in the plurality of pixel circuits 40 are arranged in the column direction. The third data D3 of the pixel circuit 40-1 is transferred to the pixel circuit 40-2, and the third data D3 of the pixel circuit 40-2 is transferred to the pixel circuit 40-3. The timing of holding the data D1, D2, and D3 can be arbitrarily set for each register 48a, 48b, and 48d in each pixel circuit 40. When holding the data D1, D2, and D3, the output of each register 48a, 48b, and 48d is updated to the data D1, D2, and D3.

[0096] The operation in each pixel circuit 40 is described. This operation is performed simultaneously in the pixel circuit 40-1, the pixel circuit 40-2, and the pixel circuit 40-3. Fig. 9 As shown, the first register 48a of each pixel circuit 40 holds the first data D1 and outputs it to the adder 48c. At this time, the second register 48b does not hold the second data D2. When the first data D1 is input, the output of the adder 48c is automatically updated. Therefore, at this stage, an invalid value is output from the adder 48c.

[0097] Then, if Fig.10 As shown, the second register 48b holds the third data D3 transferred from the pixel circuit 40 of the previous row (for example, the pixel circuit 40-1 when viewed from the pixel circuit 40-2) as the second data D2, and outputs the second data D2 to the adder 48c. The adder 48c outputs the third data D3 obtained by adding the first data D1 and the second data D2. At this time, the third register 48d does not hold the third data D3 yet. The second register 48b can hold the second data D2 before the first register 48a holds the first data D1.

[0098] Then, if Fig.11 As shown, the third register 48d holds the third data D3 and outputs the third data D3 to the pixel circuit 40 in the next row (for example, the pixel circuit 40-3 when viewed from the pixel circuit 40-2).

[0099] Here, if it is assumed that there is no first register 48a, the counter 47 must be stopped until the first data D1 and the second data D2 are added by the adder 48c and the third data D3 is held in the third register. Therefore, in order to extend the counting operation period of the counter 47, the first register 48a is provided. Fig.12 As shown, assuming that there is no third register 48d, when the second register 48b holds the second data D2, the second data D2 will be continuously output to the pixel circuits 40 of all subsequent rows as the third data D3. In this case, according to the above sequence, it is difficult to add the first data D1 at an appropriate timing. In other words, the output of the adder 48c will change in the timing when the second register 48b holds the second data D2. As a result, it is difficult to perform the TDI action because it is impossible to simultaneously transfer the value counted by the counter 47 to the pixel circuit 40 of the next row in all pixel circuits 40. The same is true when there is no second register 48b. Therefore, in order to properly perform the TDI action, the second register 48b and the third register 48d are provided.

[0100] Fig.13 yes Figure 7 An example of a circuit diagram of an adder 48c shown in FIG. 4 is a full adder that receives three input signals A, B, and C and performs binary addition. The adder 48c is a complex logic circuit composed of 28 transistors Tr. As output signals, the addition result SUM and the carry signal CARRY to the higher bit can be obtained. Fig.14 yes Figure 7An example of a circuit diagram of each register 48a, 48b, 48d shown. Each register 48a, 48b, 48d is a D latch circuit including a clocked inverter In1 and an inverter In2. Each register 48a, 48b, 48d requires a total of 11 transistors. The input and output of each register 48a, 48b, 48d are composed of an input signal (D), a latch enable signal (LE) and an output (Q). When the latch enable signal (LE) is at a low level, the previous output (Q) is maintained. When the latch enable signal (LE) is at a high level, the output has the same logic as the input logic.

[0101] Fig.151 is a diagram for explaining a radiation detection method using a radiation detector 1. The radiation detection method includes steps ST1 to ST12. In step ST1, carriers are generated in a plurality of pixels 2c arranged along a first direction A1 in response to incident radiation R. Next, in step ST2, carriers are read from corresponding pixels 2c in a plurality of pixel circuits 40 provided corresponding to each of the plurality of pixels 2c. Next, in step ST3, a first pulse signal PS1 based on the amount of carriers is compared with a threshold value Th, and a second pulse signal PS2 is output when the first pulse signal PS1 exceeds the threshold value Th. This step ST3 is performed by a comparator 46. Next, in step ST4, the number of second pulse signals PS2 is counted. This step ST4 is performed by a counter 47. Next, in step ST5, the count value obtained by the counter 47, i.e., the first data D1, is held in a first register 48a. Next, in step ST6, the second data D2 is held in a second register 48b. Step ST6 may be performed before step ST5. Next, in step ST7, the first data D1 and the second data D2 are added to each other. In this step ST7, the third data D3 is generated by adding the first data D1 and the second data D2 to each other. This step ST7 is performed by the adder 48c. Next, in step ST8, the third data D3 is maintained in the third register 48d. Here, the second data D2 is the third data D3 transferred from the third register 48d of the pixel circuit 40 corresponding to the pixel 2c adjacent to the corresponding pixel 2c in each of the plurality of pixel circuits 40. Next, in step ST9, the third data D3 is transferred to the pixel circuit 40 of the subsequent stage. Next, in step ST10, it is determined whether the above steps ST1 to ST9 are completed until the pixel circuit 40 corresponding to the pixel 2c of the last row. If steps ST1 to ST9 have not been completed by the pixel circuit 40 corresponding to the pixel 2c of the last row (step ST10; NO), the target pixel 2c is moved to the next stage by one (step ST11), and steps ST1 to ST9 are performed again. On the other hand, if steps ST1 to ST9 have been completed by the pixel circuit 40 corresponding to the pixel 2c of the last row (step ST10; YES), in step ST12, the third data D3 is output to the outside of the radiation detector 1. The series of steps using the radiation detection method ends with step ST12.

[0102] [Function and Effect]

[0103] In the radiation detector 1 and the integrated circuit 4, the detection system 49 of each of the plurality of pixel circuits 40 has a second register 48b, an adder 48c, and a third register 48d. The second register 48b holds the third data D3 transferred from the third register 48d in the pixel circuit 40 corresponding to the pixel 2c adjacent to the corresponding pixel 2c as the second data D2. The adder 48c generates the third data D3 by adding the count value obtained by the counter 47, i.e., the first data D1, to the second data D2. The third register 48d holds the generated third data D3. With such a configuration, it is not necessary to write (load) the count value in the pixel circuit 40 of the previous stage into the counter 47 of each pixel circuit 40. Therefore, the non-operation period of the counter 47 can be shortened. Therefore, the proportion of the operation period of the counter 47 in each pixel circuit 40, i.e., the period in which the radiation R can be detected, in the entire operation period of the pixel circuit 40 can be increased. Furthermore, if the first register 48a is not provided, the count value cannot be updated until the count value is held in a subsequent register (e.g., the third register 48d), and the problem of the operation of the counter 47 being stopped during this period may occur. Since such a problem does not occur by providing the first register 48a, the non-operation period of the counter 47 can be further shortened. As described above, according to the radiation detector 1, it is possible to provide a radiation detector 1 and an integrated circuit 4 that can improve the detection efficiency of the radiation R by increasing the ratio of the period in which the radiation R can be detected to the entire operation period.

[0104] In the radiation detector 1, in each of the plurality of pixel circuits 40, the area of ​​the first region 41 occupied by the analog circuit including the comparator 46 is larger than the area of ​​the second region 42 occupied by the digital circuit including the counter 47, the first register 48a, the second register 48b, the adder 48c and the third register 48d. In the first region 41, in order to suppress the characteristic deviation of each element, at least one of the size of the element and the mounting interval between the elements may be changed. According to the radiation detector 1, since the area of ​​the first region 41 is large, the degree of freedom in designing the analog circuit can be increased. In addition, the function of transferring the third data D3 between the pixel circuits 40 (TDI function in the digital circuit) can be configured relatively simply. Therefore, the area of ​​the digital circuit can be reduced.

[0105] In the radiation detector 1, the area of ​​the first region 41 occupies more than half of the entire area of ​​each of the plurality of pixel circuits 40. Thus, since the area of ​​the first region 41 is large, the degree of freedom in designing analog circuits can be increased.

[0106] In the radiation detector 1, the number of bits of the second register 48b is the sum X+Y of the number of bits X of the first register 48a and the number of bits Y obtained by expressing the number of the plurality of pixel circuits 40 in binary, and the number of bits of the adder 48c is the same as the number of bits X+Y of the second register 48b. Thus, since the number of bits X+Y of the adder 48c is the same as the number of bits X+Y of the second register 48b, addition processing can be performed in parallel for each bit. Therefore, the processing speed can be improved.

[0107] In the radiation detector 1, each of the plurality of pixel circuits 40 further includes a charge sharing countermeasure circuit 45 which, when carriers generated by the incidence of radiation R are dispersed to two or more pixel circuits 40 and read out, determines the pixel 2c corresponding to the position where the radiation R is incident, corrects the amount of carriers in the pixel 2c and evaluates it, or ignores the incidence of the radiation R. This can suppress a reduction in energy resolution and blurring of the image due to charge sharing.

[0108] In the radiation detector 1, each of the plurality of pixel circuits 40 further includes a shaping circuit 44a, 44b provided at a preceding stage of the comparator 46, and the shaping circuit 44a, 44b reduces the time constant of the first signal PS1. Thus, the response speed of the comparator 46 can be increased by the shaping circuit 44a, 44b, thereby further shortening the non-operation period of the counter 47.

[0109] In the radiation detection method using the radiation detector 1, there are: step ST6, which holds the third data D3 transferred from the third register 48d in the pixel circuit 40 corresponding to the pixel 2c adjacent to the corresponding pixel 2c as the second data D2 in the second register 48b; step ST7, which generates the third data by adding the count value obtained by the step ST4 of counting, that is, the first data, to the second data; and step ST8, which holds the generated third data D3 in the third register 48d. Here, the step ST4 of counting is performed by the counter 47 of each pixel circuit 40. With such a configuration, it is unnecessary to write (load) the count value in the pixel circuit 40 of the previous stage into the counter 47 of each pixel circuit 40. Therefore, the non-operation period of the counter 47 can be shortened. Therefore, the ratio of the operation period of the counter 47 in each pixel circuit 40, that is, the period in which the radiation R can be detected, to the entire operation period of the pixel circuit 40 can be increased. Furthermore, if the first register 48a is not provided, the count value cannot be updated until the count value is held in a subsequent register (e.g., the third register 48d), and the problem of the operation of the counter 47 being stopped during this period may occur. Since such a problem does not occur by providing the first register 48a, the non-operation period of the counter 47 can be further shortened. As described above, according to the radiation detection method using the radiation detector 1, a radiation detection method can be provided that improves the detection efficiency of radiation by increasing the ratio of the period in which radiation can be detected to the entire operation period.

[0110] [Second embodiment]

[0111] Fig.164 is a diagram showing the detailed structure of the pixel circuit 48A of the pixel circuit 40 of the second embodiment. Only the points different from the first embodiment are described. The pixel circuit 48A has an adder 48e instead of the adder 48c of the first embodiment. The number of bits of the adder 48e is less than the number of bits Y of the second register 48b, which is 1 bit in the present embodiment. The adder 48e includes a fourth register 48i for holding a carry signal. The pixel circuit 48A includes a plurality of first selector circuits 48f, a plurality of second selector circuits 48g, a plurality of third selector circuits 48h, a plurality of fourth selector circuits 48k, and a plurality of fifth selector circuits 48j. Each of the plurality of first selector circuits 48f corresponds to each of the X bits of the first register 48a. Each of the plurality of second selector circuits 48g and each of the plurality of fifth selector circuits 48j corresponds to each of the X+Y bits of the second register 48b. Each of the plurality of third selector circuits 48h and each of the plurality of fourth selector circuits 48k corresponds to each of the X+Y bits of the third register 48d. The plurality of fourth selector circuits 48k are connected in series with the plurality of fifth selector circuits 48j of the pixel circuits 40 of the next row.

[0112] A bit selection signal is input to a plurality of first selector circuits 48f, a plurality of second selector circuits 48g, a plurality of third selector circuits 48h, a plurality of fourth selector circuits 48k, and a plurality of fifth selector circuits 48j. The bit selection signal is sent, for example, from an external control circuit. The first data D1 is always input to each of the plurality of first selector circuits 48f from the bit of the corresponding first register 48a. When the bit selection signal is input, each of the plurality of first selector circuits 48f outputs a portion of the bits of the first data D1 from the bit of the corresponding first register 48a to the adder 48e. Specifically, the plurality of first selector circuits 48f select bits from A0 to A1. X-1 The first data D1 is outputted sequentially from the least significant bit A0 in the second register 48b. The second data D2 is always inputted to each of the plurality of second selector circuits 48g from the bit of the corresponding second register 48b. When the bit selection signal is inputted, each of the plurality of second selector circuits 48g outputs a part of the bit of the second data D2 from the bit of the corresponding second register 48b to the adder 48e. Specifically, the plurality of second selector circuits 48g output the second data D2 from the bit of the corresponding second register 48b to the adder 48e. Y+X-1 The second data D2 is output sequentially starting from the lowest bit B0 in the data.

[0113] The adder 48e adds the first data D1 and the second data D2 in order from the least significant bit. In other words, the adder 48e repeatedly adds and outputs a portion of the bits of the first data D1 in the first register 48a and a portion of the bits of the second data D2 in the second register 48b corresponding to the portion of the bits until all the bits A0 to A1 of the first data D1 are added. X-1The carry generated at this time is held in the fourth register 48i and is reflected in the addition of the higher bits. X-1 and B0 to B of the second data D2 X-1 After the addition, the adder 48e performs a carry signal or 0 and the remaining bit B of the second data D2. X ~B Y+X-1 The carry signal here refers to the highest bit A in the first data D1. X-1 and bit B of the second data D2 X-1 After the carry signal is added to the corresponding bit of the second data D2, the adder 48e adds 0 to the second data D2 until the highest bit B of the second data D2 is reached. Y+X-1 In the second embodiment, even if the data D1, D2, D3 are held in the registers 48a, 48b, 48d, unless the bit to be outputted by the bit selection signal is specified, the outputs of the registers 48a, 48b, 48d are not updated and indefinite values ​​can be outputted.

[0114] The addition result is input from the adder 48e to each of the plurality of third selector circuits 48h. When a bit selection signal is input, each of the plurality of third selector circuits 48h outputs the addition result to the corresponding bit of the third register 48d. Thus, each of the plurality of third registers 48d stores each bit of the third data D3, which is the addition result of the first data D1 and the second data D2. The third data D3 is input from the corresponding bit of the third register 48d to each of the plurality of fourth selector circuits 48k. When a bit selection signal is input, each of the plurality of fourth selector circuits 48k outputs the bit data of the third data D3 from the corresponding bit of the third register 48d to the next row of pixel circuits 40. Specifically, the plurality of fourth selector circuits 48k sequentially output bits S0 to S1 stored in the third register 48d, starting from the lowest bit S0. Y+X-1 The third data D3.

[0115] Each bit of the third data D3 is sequentially input to each of the plurality of fifth selector circuits 48j from the plurality of fourth selector circuits 48k of the pixel circuit 40 of the previous row. A bit selection signal is input to each of the plurality of fifth selector circuits 48j at the same timing as the bit selection signal input to the corresponding fourth selector circuit 48k. When the bit selection signal is input, each of the plurality of fifth selector circuits 48j outputs a part of the bits of the third data D3 to the corresponding bit of the second register 48b.

[0116] Fig.17 yes Fig.16The circuit diagram of the selector circuits 48f, 48g, 48h, 48k, and 48j shown in FIG. The selector circuits 48f, 48g, 48h, 48k, and 48j are complex logic circuits composed of four transistors Tr. A bit selection signal is input to the Sel terminal. Part of the bits of each data D1, D2, and D3 are input to the In terminal from each register 48a, 48b, and 48d. When the bit selection signal is input to the Sel terminal, the selector circuits 48f, 48g, 48h, 48k, and 48j output part of the bits of each data D1, D2, and D3 from the OUT terminal.

[0117] Here, the pixel circuit 48 ( Figure 8 ) and the number of transistors required for the pixel circuit 48A of the second embodiment ( Fig.16 ) The number of transistors required is calculated roughly, and the maximum count value of the counter 47, that is, the X bit, is set to 12 bits, and the Y bit obtained by representing the number of rows of the plurality of pixel circuits 40 in binary, that is, M, is set to 6 bits. In the pixel point circuit 48 of the first embodiment and the pixel point circuit 48A of the second embodiment, the number of transistors required to constitute the first register 48a is 132 (number of bits: 12 × number of transistors: 11). In the pixel point circuit 48 of the first embodiment and the pixel point circuit 48A of the second embodiment, the number of transistors required to constitute the second register 48b and the third register 48d, respectively, is 198 (number of bits: 18 × number of transistors: 11). The number of transistors required to constitute the adder 48c of the first embodiment is 504 (number of bits: 18 × number of transistors: 28), and the number of transistors required to constitute the adder 48e of the second embodiment is 28 (number of bits: 1 × number of transistors: 28). In the pixel point circuit 48A of the second embodiment, 192 transistors are required to constitute a plurality of first selector circuits 48f, a plurality of second selector circuits 48g, and a plurality of third selector circuits 48h (total number of bits: 48×number of transistors: 4). In addition, in the pixel point circuit 48A of the second embodiment, 11 transistors are required to constitute the fourth register 48i included in the adder 48e (number of bits: 1×number of transistors: 11). As described above, the total number of transistors required for the pixel point circuit 48 of the first embodiment is 1032, and the total number of transistors required for the pixel point circuit 48A of the second embodiment is 759. The pixel point circuit 48A of the second embodiment has a number of transistors reduced by about 30% compared to the pixel point circuit 48 of the first embodiment.

[0118] Fig.18 It is used to illustrate Fig.161 is a diagram showing the configuration of the input and output terminals of the adder 48e. In the adder 48e, a NOR element N1 is mounted on the input terminal 48e-1 to which the first data D1 is input from the first register 48a. In the adder 48e, a NOR element N2 is mounted on the input terminal 48e-2 to which the second data D2 is input from the second register 48b. The NOR element N1 and the NOR element N2 have a function of switching between enable and disable. When the enable signal enb1 is input to the NOR element N1 (the NOR element N1 becomes enabled), the first data D1 is input to the input terminal 48e-1. On the other hand, when the enable signal enb1 is not input to the NOR element N1 (the NOR element N1 becomes disabled), "0" is input to the input terminal 48e-1. When the enable signal enb2 is input to the NOR element N2 (the NOR element N2 becomes enabled), the second data D2 is input to the input terminal 48e-2. On the other hand, when the enable signal enb2 is not input to the NOR element N2 (the NOR element N2 becomes disabled), "0" is input to the input terminal 48e-2. When both the NOR element N1 and the NOR element N2 are enabled, the third data D3 is output from the output terminal 48e-3 of the adder 48e. However, when only one of the NOR element N1 and the NOR element N2 is enabled, the first data D1 and the second data D2 that become enabled are output from the output terminal 48e-3. Instead of the NOR element N1 and the NOR element N2, other logic circuits that output the first data D1 only when the enable signal enb1 (input is 1) is input may be used.

[0119] Figure 19 to Figure 21 2 is a diagram for explaining the TDI operation of the pixel circuit 40 of the second embodiment. The arrangement of the pixel circuit 40-1, the pixel circuit 40-2, and the pixel circuit 40-3, and the transfer direction of the third data D3 are the same as those of the first embodiment. Fig.19 As shown, first, the first register 48a of each pixel circuit 40 holds the first data D1. At this time, the NOR element N1 is set to be disabled. Therefore, an invalid value is output from the adder 48e. When the NOR element N1 is set to be enabled, since the output of the NOR element N1 changes due to the output of the first register 48a, an indefinite value may be output from the adder 48e, but as long as the indefinite value is not held by the third register 48d, there is no doubt that the indefinite value will be transferred to the subsequent pixel circuit 40, so it will not be a particular problem.

[0120] Then, if Fig. 20As shown, the least significant bit of each data D1, D2, and D3 is output from each register 48a, 48b, and 48d. The specific operation is described by taking the pixel circuit 40-1 as an example. When the bit selection signal is input, the fourth selector circuit 48k of the pixel circuit 40-1 outputs the least significant bit S0 of the third data D3 from the third register 48d of the pixel circuit 40-1 to the fifth selector circuit 48j of the pixel circuit 40-2. When the bit selection signal is input, the fifth selector circuit 48j of the pixel circuit 40-2 outputs the least significant bit S0 of the third data D3 to the second register 48b of the pixel circuit 40-2. The second register 48b of the pixel circuit 40-2 maintains the least significant bit S0 of the transferred third data D3 as the least significant bit B0 of the second data D2. Here, the bit selection signal is also sent to the selector circuits 48f and 48g at the same time. Thus, when the bit selection signal is input, the first selector circuit 48f of the pixel circuit 40-1 outputs the least significant bit A0 of the first data D1 from the first register 48a of the pixel circuit 40-1 to the adder 48e. When the bit selection signal is input, the second selector circuit 48g of the pixel circuit 40-1 outputs the least significant bit B0 of the second data D2 from the second register 48b of the pixel circuit 40-1 to the adder 48e. At this time, the NOR element N1 and the NOR element N2 are set to be disabled so that the adder 48e does not operate.

[0121] Then, if Fig.21 As shown, the NOR element N1 and the NOR element N2 are set to be enabled. As a result, the adder 48e generates the lowest bit S0 of the third data D3 by adding the lowest bit A0 of the first data D1 and the lowest bit B0 of the second data D2. The lowest bit S0 is input from the adder 48e to the third selector circuit 48h. When the bit selection signal is input, the third selector circuit 48h outputs the lowest bit S0 to the corresponding bit of the third register 48d. The third register 48d holds the lowest bit S0 of the third data D3. Fig.19 and Fig. 20 The above process is repeated from the lowest bit A0, B0, S0 of each data D1, D2, D3 to the highest bit A0, B0, S ... X-1 , B Y+X-1 , S Y+X-1 In this process, the adder 48e repeatedly adds and outputs a portion of the bits of the first data D1 and a portion of the bits of the second data D2 until all the bits X of the first data D1 are added. X-1 and B0 to B of the second data D2 X-1 After the addition, the adder 48e performs a carry signal or 0 and the remaining bit B of the second data D2. X ~B Y+X-1That is, after the adder 48e adds the carry signal to the corresponding bit of the second data D2, it adds 0 to the second data D2 until the highest bit B of the second data D2 is reached. Y+X-1 until.

[0122] The pixel circuit 40 of the second embodiment can also function as a global shutter in addition to the TDI operation. In this case, the timing for keeping the first data D1 in the first register 48a is the same in all pixel circuits 40. And, for example, when the first data D1 is read out from the pixel circuit 40-1, the NOR element N1 of the adder 48e in the pixel circuit 40-1 is set to be enabled, and on the other hand, the NOR element N2 is set to be disabled. Then, the NOR element N1 of the adder 48e in each pixel circuit 40 from the pixel circuit 40-2 of the next row to the pixel circuit 40 of the last row is set to be disabled, and on the other hand, the NOR element N2 is set to be enabled. As a result, the addition process is not performed in each pixel circuit 40 from the pixel circuit 40-2 to the pixel circuit 40 of the last row, and the first data D1 of the pixel circuit 40-1 is sequentially transferred to the pixel circuit 40 of the next row. Then, the first data D1 of the pixel circuit 40-1 is read out from the pixel circuit 40 of the last row. The above-mentioned operation is repeated from the pixel circuit 40 of the first row until the pixel circuit 40 of the last row. By making the pixel circuit 40 of the second embodiment function as a global shutter, the operation of reading out a two-dimensional image can be performed. Alternatively, the pixel circuit 40 of the second embodiment can also function as a rolling shutter. In this case, for example, in the above-mentioned global shutter operation, the timing of maintaining the first data D1 in the first register 48a is shifted between each pixel circuit 40 through a delay circuit or the like. Specifically, relative to the timing of maintaining the first data D1 in the first register 48a in the pixel circuit 40-1, the timing of maintaining the first data D1 in the first register 48a in the pixel circuit 40-2 is delayed. Similarly, the timing at which the pixel circuit 40-3 holds the first data D1 in the first register 48a is delayed relative to the timing at which the pixel circuit 40-2 holds the first data D1 in the first register 48a. As a result, the timing at which the first data D1 is read out from each pixel circuit 40 gradually shifts along the pixel arrangement direction.

[0123] [Function and Effect]

[0124] In the radiation detector 1, the number of bits of the second register 48b is equal to or greater than the sum X+Y of the number of bits X of the first register 48a and the number of bits Y obtained by expressing the number of the plurality of pixel circuits 40 in binary, the number of bits of the adder 48e is smaller than the number of bits X+Y of the second register 48b, and the adder 48e repeatedly performs the operation of adding and outputting a portion of the bits of the first data D1 of the first register 48a and a portion of the bits of the second data D2 of the second register 48b corresponding to the portion of the bits until all the bits of the first data D1 are added. Thus, since the number of bits of the adder 48e is smaller than the number of bits of the second register 48b, the circuit area can be reduced. On the other hand, the adder 48e repeatedly performs the operation of adding and outputting a portion of the bits of the first data D1 and a portion of the bits of the second data D2 until all the bits of the first data D1 are added, so that the addition process can be performed even if the number of bits is small.

[0125] In the radiation detector 1, the adder 48e has a bit number of 1 and includes a fourth register 48i for holding a carry signal. This can reduce the circuit area and perform carry calculation even if the adder 48e has a bit number of 1.

[0126] [Modifications]

[0127] The present disclosure is not limited to the above-described embodiment. Each pixel circuit 40 may include a plurality of detection systems. Fig. 224 is a circuit block diagram of a pixel circuit 40A of a modified example. Only the points different from the first embodiment and the second embodiment are described. Each pixel circuit 40A replaces the detection system 49 of the pixel circuit 40, thereby having a first detection system 49a and a second detection system 49b. The first detection system 49a includes a first comparator 46a instead of the comparator 46 of the detection system 49. The first detection system 49a includes a first AND circuit ANa instead of the AND circuit AN. The first detection system 49a includes a first counter 47a instead of the counter 47. The second detection system 49b includes a second comparator 46b instead of the comparator 46 of the detection system 49. The second detection system 49b includes a second AND circuit ANb instead of the AND circuit AN. The second detection system 49b includes a second counter 47b instead of the counter 47. The first detection system 49a and the second detection system 49b include common pixel point circuits 48B and 48C instead of the pixel point circuits 48 and 48A. The output terminal of the shaping circuit 44b is connected to one of the inverting input terminal and the non-inverting input terminal of the first comparator 46a, and one of the inverting input terminal and the non-inverting input terminal of the second comparator 46b, respectively. The charge sharing countermeasure circuit 45 is connected to one of the input terminals of the first AND circuit ANa and one of the input terminals of the second AND circuit ANb. The output terminal of the first comparator 46a is connected to the other of the input terminals of the first AND circuit ANa. The output terminal of the second comparator 46b is connected to the other of the input terminals of the second AND circuit ANb. The output terminal of the first AND circuit ANa is connected to the input terminal of the first counter 47a. The output terminal of the second AND circuit ANb is connected to the input terminal of the second counter 47b. The output terminal of the first counter 47a and the output terminal of the second counter 47b are connected to the common pixel circuits 48B and 48C. The first threshold Th1 is input to the other of the inverting input terminal and the non-inverting input terminal of the first comparator 46a. The second threshold Th2 is input to the other of the inverting input terminal and the non-inverting input terminal of the second comparator 46b. If the second threshold Th2 is a value different from the first threshold Th1, the second threshold Th2 may be larger or smaller than the first threshold Th1.

[0128] Fig.23 and Fig.24 yes Fig. 22 Circuit diagram of pixel circuits 48B and 48C shown. Fig.23 4 is a circuit diagram of a pixel circuit 48B in which adders 48c-1 and 48c-2 of a first detection system 49a and a second detection system 49b are provided individually for each detection system. Fig.23As shown, the first detection system 49a includes a first register 48a-1, a second register 48b-1, an adder 48c-1, and a third register 48d-1 inside the pixel circuit 48. The operation of each register 48a-1, 48b-1, and 48d-1 is the same as the operation of each register 48a, 48b, and 48d in the first embodiment or the second embodiment. The operation of the adder 48c-1 is the same as the operation of the adder 48c in the first embodiment or the adder 48e in the second embodiment. The second detection system 49b includes a first register 48a-2, a second register 48b-2, an adder 48c-2, and a third register 48d-2 inside the pixel circuit 48. The operations of the registers 48a-2, 48b-2, 48d-2 and the adder 48c-2 are the same as the operations of the registers 48a-1, 48b-1, 48d-1 and the adder 48c-1 of the first detection system 49a. The first detection system 49a counts the number of hits of the radiation R based on the comparison result of the first threshold value Th1 and the first pulse signal PS1 using the first counter 47a. The first detection system 49a counts the number of hits of the radiation R based on the comparison result of the first threshold value Th1 and the first pulse signal PS1. Figure 2 The third data D3 is sequentially transferred (TDI operation) between the pixel circuits 40A corresponding to the pixels 2c adjacent to each other in the first direction A1 shown in the figure. The second detection system 49b counts the number of hits of the radiation R based on the comparison result between the second threshold value Th2 and the first pulse signal PS1 using the second counter 47b. Then, the second detection system 49b sequentially transfers (TDI operation) the third data D3 between the pixel circuits 40A corresponding to the pixels 2c adjacent to the corresponding pixel 2c in the first direction A1. Fig.24 4 is a circuit diagram of a pixel circuit 48C when the adder 48c of the first detection system 49a and the adder 48c of the second detection system 49b are shared. Fig.23 The common adder 48c does not perform the addition processing in the first detection system 49a and the addition processing in the second detection system 49b at the same time. For example, during the addition processing in the first detection system 49a, the common adder 48c does not receive input from the second detection system 49b.

[0129] According to the radiation detector 1 having each pixel circuit 40A of the above-mentioned modification, the energy level of the radiation R (the amount of carriers generated) can be detected by the first detection system 49a and the second detection system 49b. In the case where the adders 48c-1 and 48c-2 of the first detection system 49a and the second detection system 49b are individually provided for each detection system, the detection processing can be performed in parallel in a plurality of detection systems, and the processing speed can be improved. In the case where the adder 48c of the first detection system 49a and the second detection system 49b is shared, the area of ​​each pixel circuit 40 can be reduced. Each pixel circuit 40A can have at least one detection system, or can have three or more detection systems.

[0130] In the first embodiment and the second embodiment, the adders 48c and 48e and the registers 48a, 48b and 48d are described as other independent components, but the adders 48c and 48e may also have at least one function of the registers 48a, 48b and 48d. For example, the adders 48c and 48e have the function of the first register 48a, and the adders 48c and 48e may also hold the first data D1 output from the counter 47. In other words, the adders 48c and 48e may include at least one of the first register 48a holding the first data D1, the second register 48b holding the second data D2, and the third register 48d holding the third data D3. In this case, the detection system 49 has other registers other than the adders 48c and 48e except for at least one of the first register 48a, the second register 48b and the third register 48d. In the above-described configuration, the radiation detector 1 and the integrated circuit 4 can also exert the same functions and effects as those of the embodiment.

[0131] The conversion unit 2, the plurality of pixel electrode units 3 and the integrated circuit 4 may also be formed on the same substrate (monolithic). Alternatively, the conversion unit 2, the plurality of pixel electrode units 3 and the integrated circuit 4 may also be formed on different substrates respectively and bonded to each other by bump bonding or the like (hybrid). The radiation detector 1 may be a direct conversion type that directly converts the radiation R into an electrical signal (first pulse signal PS1), or may be an indirect conversion type that converts via a scintillator by further comprising a scintillator. The number of bits of the second register 48b and the third register 48d may be a number greater than X+Y bits.

[0132] Figure 25 to Figure 29 4 is a diagram for explaining the transfer direction of the third data D3 of the pixel circuit 40 of the modified example. Fig.25As shown, the radiation detector 1 can switch between the first TDI action and the second TDI action. The first TDI action is a TDI action that transfers the carriers generated in each pixel 2c to the adjacent pixel 2c column by column along the first direction A1. The first TDI action is, for example, an action of transferring from pixel 2c-2 to pixel 2c-3. The second TDI action is a TDI action that transfers to the adjacent pixel 2c along the second direction A2, which is the opposite direction of the first direction. The second TDI action is, for example, an action of transferring from pixel 2c-2 to pixel 2c-1. Fig.26 and Fig. 27 FIG. 4 shows a pixel circuit 48 of the pixel circuit 40 according to the first embodiment. Fig.28 and Fig.29 The pixel circuit 48A of the pixel circuit 40 of the second embodiment is shown. In the first and second embodiments, the plurality of pixel circuits 40 can switch the transfer direction of the third data D3 by switching the transfer direction of the carriers of the plurality of pixels 2c between the first direction A1 and the second direction A2. The switching of the transfer direction of the third data D3 can be performed, for example, by using a plurality of switching switches SW (switching units) having the same number of bits as the second register 48b and the third register 48d, X+Y bits. Fig.26 and Fig.28 As shown in FIG. 1 , the plurality of switching switches SW can set the transfer direction of the third data D3 in such a manner that the transfer direction of the carriers of the plurality of pixels 2c becomes the first direction A1. Fig. 27 and Fig.29 As shown, the plurality of switching switches SW can also set the transfer direction of the third data D3 in such a way that the transfer direction of the carriers of the plurality of pixels 2c becomes the second direction A2. In other words, the plurality of switching switches SW switches between the action of transferring the third data D3 in such a way that the transfer direction of the carriers becomes the first direction A1 and the action of transferring the third data D3 in such a way that the transfer direction of the carriers becomes the second direction A2. Switching the transfer direction between the first direction A1 and the second direction A2 by using the plurality of switching switches SW can be performed at any timing or in response to the passage of a specified time. By providing a plurality of switching switches SW, the third data D3 can be transferred bidirectionally in the plurality of pixel circuits 40. Figure 26 to Figure 29 In the figure, only the pixel circuit 40 is shown, but this modification can also be applied to the pixel circuit 40A. In this case, the plurality of switches SW switch between the operation of transferring the third data D3 in a manner that the transfer direction of the carrier becomes the first direction A1 and the operation of transferring the third data D3 in a manner that the transfer direction of the carrier becomes the second direction A2 in the first detection system 49a and the second detection system 49b, respectively.

[0133] Fig.30FIG. 4 is a diagram showing a detailed configuration of a pixel circuit 48D of a pixel circuit 40 of a modified example. Only points different from the pixel circuit 48A of the second embodiment are described. Fig.29 As shown, in the pixel circuit 48D, the third register 48d and the second register 48b of the pixel circuit 40 of the next row can be directly connected in parallel without passing through a plurality of fourth selector circuits 48k and a plurality of fifth selector circuits 48j. In this case, the third data D3 is directly output from each bit of the third register 48d to the corresponding bit of the second register 48b of the pixel circuit 40 of the next row.

[0134] Fig.31 FIG. 4 is a diagram showing a detailed configuration of a pixel circuit 48E of a pixel circuit 40 of a modified example. Only points different from the pixel circuit 48A of the second embodiment are described. Fig.30 As shown, in the pixel circuit 48E, the number of bits of the adder 48e is X+1. The adder 48e performs the addition processing of the first data D1 and the second data D2 in parallel from bit 0 to bit X-1. The adder 48e sends the addition results from bit 0 to bit X-1 in parallel to the corresponding bits of the third selector circuit 48h. X-1 After the addition, the adder 48e adds the carry signal at the X+1th bit (Addx) of the adder 48e and the remaining bits of the second data D2. The carry signal mentioned here refers to the carry signal at the most significant bit A of the first data D1. X-1 and bit B of the second data D2 X-1 The carry signal generated during the addition is held in the fourth register 48i. The adder 48e adds the most significant bit A of the first data D1 to the X-1 and bit B of the second data D2 X-1 After the addition, 0 is added to the second data D2 at the X+1th bit (Addx) of the adder 48e until the most significant bit B of the second data D2 is reached. Y+X-1 Since in the pixel point circuit 48E, each bit of the first register 48a and the 0th bit to the X-1th bit of the adder 48e are connected in parallel with each other, the pixel point circuit 48E may not include the selector circuit 48f. Similarly, the pixel point circuit 48E may not include the selector circuit 48g of the 0th bit to the X-1th bit, and the selector circuit 48h of the 0th bit to the X-1th bit. In the pixel point circuit 48E that does not include the above-mentioned selector circuit, the processing speed can be further improved than the pixel point circuit 48A of the second embodiment. In the pixel point circuit 48E that does not include the above-mentioned selector circuit, the area of ​​the pixel circuit can be further reduced than the pixel point circuit 48 of the first embodiment.

[0135] In the first embodiment, the second embodiment, and the above-described modified examples, the timing at which the first data D1 is held in the first register 48 a may be simultaneous in all the pixel circuits 40 constituting the plurality of pixel circuits 40 . Fig.32 2 is a diagram showing an example of the conversion unit 2, the power supply 6 and the control unit 5. Fig.32 , M×N pixel circuits 40 are shown. A power supply 6 supplies a power supply voltage PV to each pixel circuit 40 via a power transmission line 61. Fig.32 In the example of , the power transmission line 61 branches into M rows along the column direction (the first direction A1 or the second direction A2). The power transmission line 61 branched into M rows is connected to each pixel circuit 40 along the row direction.

[0136] The control unit 5 sends the first hold signal S1, the counter operation signal C_act, and the counter reset signal C_rst to each pixel circuit 40 via the signal line 51. Fig.32 In the example of , the signal line 51 branches into N columns along the row direction (a direction perpendicular to the first direction A1 and the second direction A2, i.e., the third direction A3 or the fourth direction A4). The signal line 51 branched into N columns is connected to each pixel circuit 40 along the column direction. The direction in which the transmission line 61 branches is the column direction, whereas the direction in which the signal line 51 branches is the row direction. That is, the direction in which the transmission line 61 branches crosses the direction in which the signal line 51 branches.

[0137] Fig.33 It is a diagram for explaining the first hold signal S1 , the counter action signal C_act, and the counter reset signal C_rst. Fig.33 The vertical axis of the graphs (a) to (c) represents the voltage value, and the horizontal axis represents the time. Fig.33 The counter action signal C_act shown in (a) is at a high (H: High) level. Fig.33As shown in (b), the counter action signal C_act drops from a high level to a low level, and after the adjustment time TC, the first holding signal S1 rises from a low level to a high level. During the period when the counter action signal C_act is at a low (L: Low) level, the counter 47 stops. In synchronization with the rise of the first holding signal S1, the first data D1 is simultaneously held in the first register 48a in all pixel circuits 40. Subsequently, the first holding signal S1 drops from a high level to a low level, and after the adjustment time TC, the counter reset signal C_rst rises from a low level to a high level, resetting the counter 47. Furthermore, the counter reset signal C_rst drops, and after the adjustment time TC, the counter action signal C_act rises from a low level to a high level, and the counter 47 operates again. Here, the reason for setting the adjustment time TC is explained. There are parasitic resistance and parasitic capacitance in the signal line 51, and these may cause a delay in signal transmission. In particular, the farther the pixel circuit 40 is from the control unit 5, the greater the delay in signal transmission. When a delay in signal transmission occurs, for example, there will be a period during which both the counter action signal C_act and the first hold signal S1 are high. During this period, the first data D1 is held in the first register 48a during the operation of the counter 47. The adjustment time TC is adjusted so that the high level periods of each signal do not overlap. Fig.33 In the example, the adjustment time TC from the falling of the counter action signal C_act to the rising of the first holding signal S1, the adjustment time TC from the falling of the first holding signal S1 to the rising of the counter reset signal C_rst, and the adjustment time TC from the falling of the counter reset signal C_rst to the rising of the counter action signal C_act are all the same time, but their respective adjustment times can also be different times.

[0138] The first hold signal S1 is a pulse signal that outputs one pulse in a period T. Here, one pulse refers to a waveform in which the voltage value changes from a low level to a high level, and after the high level continues for a predetermined period, it drops from a high level to a low level. The length of one period T corresponds to one frame operation. One frame operation refers to, for example, from the time when the plurality of pixel circuits 40 hold the first data D1 to the time when the pixels 2c-M corresponding to the last row (see Figure 2 ) the operation until the corresponding pixel circuit 40 outputs the third data D3.

[0139] In the first embodiment, the second embodiment and the above-mentioned modified example, the plurality of pixel circuits 40 may be divided into a first pixel circuit region and a second pixel circuit region. Furthermore, the timing of holding the first data D1 in the first register 48a may be different in the first pixel circuit region and the second pixel circuit region. Fig.344 is a diagram showing an example of a plurality of pixel circuits 40 divided into a first pixel circuit region 401 and a second pixel circuit region 402. Fig.34 As shown, the first pixel circuit area 401 and the second pixel circuit area 402 can be set in units of one column. The first pixel circuit area 401 and the second pixel circuit area 402 can be set alternately along the third direction A3 (row direction). The signal lines outputting signals from the control unit 5 can be plural. Fig.34 In the example of , the signal lines that output signals from the control unit 5 are signal lines 51 and signal lines 52. The control unit 5 sends the first hold signal S1, the counter action signal C_act, and the counter reset signal C_rst to the first pixel circuit region 401 in each pixel circuit 40 via the signal line 51. The control unit 5 sends the second hold signal S2, the counter action signal C_act, and the counter reset signal C_rst to the second pixel circuit region 402 in each pixel circuit 40 via the signal line 52. The signal line that outputs signals from the control unit 5 may also be one. In this case, for example, one signal line that outputs signals from the control unit 5 may also be branched into a line that sends signals to the first pixel circuit region 401 and a line that sends signals to the second pixel circuit region 402. The control unit 5 may also switch to a line that sends signals to the first pixel circuit region 401 and a line that sends signals to the second pixel circuit region 402 by a switch circuit disposed between the control unit 5 and the first pixel circuit region 401 and the second pixel circuit region 402. For example, the control unit 5 may switch the switch of the switch circuit according to the timing of transmitting the first holding signal S1 to the first pixel circuit region 401 and the timing of transmitting the second holding signal S2 to the second pixel circuit region 402 .

[0140] Fig.35 The first hold signal S1 and the second hold signal S2 are used to explain the operation of the counter action signal C_act and the counter reset signal C_rst. Fig.33 The control unit 5 sends the first hold signal S1 to the first pixel circuit area 401 and sends the second hold signal S2 to the second pixel circuit area 402. The first hold signal S1 and the second hold signal S2 are both pulse signals that output one pulse in a period T1. However, the phases of the first hold signal S1 and the second hold signal S2 are different. Specifically, Fig.35 As shown in (b), when the first hold signal S1 rises from a low level to a high level, and as Fig.35 As shown in (c), there is a time difference T2 until the second hold signal S2 rises from a low level to a high level. Therefore, after a time difference T2 has passed from the timing when the first data D1 is held in the first register 48a in the first pixel circuit region 401, the first data D1 is held in the first register 48a in the second pixel circuit region 402.

[0141] Figure 36 to Figure 38 This is a diagram for explaining another example of the first pixel circuit region 401 and the second pixel circuit region 402 . Figure 36 to Figure 38 M×N pixel circuits 40 are displayed. Fig.36 As shown in FIG. 4 , each of the first pixel circuit region 401 and the second pixel circuit region 402 can be set in units of a plurality of columns. Fig.36 As shown in (a), the first pixel circuit area 401 and the second pixel circuit area 402 may be alternately set every several rows along the third direction A3. Fig.36 As shown in (b) of FIG. 8 , the first pixel circuit region 401 and the second pixel circuit region 402 may be set so as to divide the plurality of pixel circuits 40 into two along the third direction A3.

[0142] exist Fig.34 and Fig.36 In the example, the direction in which the power line 61 branches is the column direction, whereas the direction in which the first pixel circuit region 401 and the second pixel circuit region 402 are divided is the row direction. That is, the direction in which the power line 61 branches crosses the direction in which the first pixel circuit region 401 and the second pixel circuit region 402 are divided.

[0143] like Fig.33 As shown, when the first data D1 is simultaneously maintained in the first register 48a in all pixel circuits 40, the power supply voltage PV temporarily changes due to the operation of a large number of digital circuits, so there is a possibility of crosstalk between the pixel circuits 40. By dividing the plurality of pixel circuits 40 into the first pixel circuit area 401 and the second pixel circuit area 402, and making the timing of maintaining the first data D1 in the first register 48a different in the first pixel circuit area 401 and the second pixel circuit area 402, the variation of the power supply voltage PV can be reduced, and the risk of crosstalk can be reduced. Furthermore, by crossing the branching direction of the power transmission line 61 with the division direction of the first pixel circuit area 401 and the second pixel circuit area 402, since the first pixel circuit area 401 and the second pixel circuit area 402 are mixed on the branched power transmission line 61, the risk of crosstalk can be further reduced.

[0144] like Fig.37 As shown in (a), the first pixel circuit region 401 and the second pixel circuit region 402 may be alternately set for each pixel along the third direction A3 (row direction) and the first direction A1 (column direction). In other words, the first pixel circuit region 401 and the second pixel circuit region 402 may be set for each pixel in a checkered pattern.

[0145] like Fig.37As shown in (b), the first pixel circuit region 401 and the second pixel circuit region 402 may be set in units of one row. The first pixel circuit region 401 and the second pixel circuit region 402 may also be set alternately along the first direction A1 (column direction). Fig.38 As shown in FIG. 4 , the first pixel circuit region 401 and the second pixel circuit region 402 may also be set in units of multiple rows. Fig.38 As shown in (a), the first pixel circuit area 401 and the second pixel circuit area 402 may be alternately set every multiple columns along the first direction A1. Fig.38 As shown in (b) of FIG. 8 , a first pixel circuit region 401 and a second pixel circuit region 402 may be set in a manner that divides the plurality of pixel circuits 40 into two along the first direction A1.

[0146] In the first embodiment, the second embodiment and the above-mentioned modified example, the plurality of pixel circuits 40 may be divided into a first pixel circuit region, a second pixel circuit region and a third pixel circuit region. In the first pixel circuit region, the second pixel circuit region and the third pixel circuit region, the timings of holding the first data D1 in the first register 48a may be different from each other. Fig.39 The diagram is used to explain the first hold signal S1, the second hold signal S2, and the third hold signal S3. Fig.33 The control unit 5 sends the first hold signal S1 to the first pixel circuit area, sends the second hold signal S2 to the second pixel circuit area, and sends the third hold signal S3 to the third pixel circuit area. The third hold signal S3 is a pulse signal that outputs one pulse in period T, similar to the first hold signal S1 and the second hold signal S2. However, the phases of the first hold signal S1, the second hold signal S2, and the third hold signal S3 are different from each other. Specifically, from Fig.39 As shown in (b), when the first hold signal S1 rises from a low level to a high level, Fig.39 As shown in (c), there is a time difference T2 until the second hold signal S2 rises from a low level to a high level. Fig.39 As shown in (d), there is a time difference T2 from when the third hold signal S3 rises from a low level to a high level. Thus, after a time difference T2 has passed from when the first data D1 is held in the first register 48a in the first pixel circuit region, the first data D1 is held in the first register 48a in the second pixel circuit region. Furthermore, after a time difference T2 has passed from when the first data D1 is held in the first register 48a in the second pixel circuit region, the first data D1 is held in the first register 48a in the third pixel circuit region.

[0147] like Fig.40 As shown, a column composed of the first pixel circuit region 401 and the second pixel circuit region 402 and a column composed of the second pixel circuit region 402 and the third pixel circuit region 403 may be alternately arranged along the third direction A3 (row direction). In a column composed of the first pixel circuit region 401 and the second pixel circuit region 402, the first pixel circuit region 401 and the second pixel circuit region 402 may be alternately arranged for each pixel along the first direction A1 (column direction). In a column composed of the second pixel circuit region 402 and the third pixel circuit region 403, the second pixel circuit region 402 and the third pixel circuit region 403 may also be alternately arranged for each pixel along the column direction.

[0148] In the above example, the form of dividing the plurality of pixel circuits 40 into two pixel circuit regions, namely the first pixel circuit region 401 and the second pixel circuit region 402, and the form of dividing the plurality of pixel circuits 40 into three pixel circuit regions, namely the first pixel circuit region 401, the second pixel circuit region 402, and the third pixel circuit region 403 are described. The form of dividing the plurality of pixel circuits 40 is not limited to this, and the plurality of pixel circuits 40 may also be divided into four or more pixel circuit regions. In this case, the timing of holding the first data D1 in the first register 48a is different in the four or more pixel circuit regions, thereby further reducing the risk of crosstalk.

[0149] [Note]

[0150] The radiation detector 1 described above includes the first register 48a for holding the count value obtained by the counter 47, that is, the first data D1, but the first register 48a may be omitted. That is, the radiation detector includes:

[0151] The conversion unit 2 includes a plurality of pixels 2c that generate carriers in response to incident radiation R, wherein the plurality of pixels 2c are arranged in a predetermined direction; and

[0152] a plurality of pixel circuits 40, each of which is provided corresponding to each of the plurality of pixels 2c and each of which has at least one detection system 49 for reading out carriers from the corresponding pixel 2c,

[0153] At least one detection system 49 includes: a comparator 46 that compares a first pulse signal PS1 based on the amount of carriers with a threshold value Th, and outputs a second pulse signal PS2 when the first pulse signal PS1 exceeds the threshold value Th;

[0154] a counter 47 for counting the number of second pulse signals PS2;

[0155] A second register 48b, which holds second data D2;

[0156] adders 48c and 48e for adding the count value of the counter 47, that is, the first data D1 and the second data D2 to generate third data D3; and

[0157] The third register 48d holds the third data D3.

[0158] The second data D2 is the third data D3 transferred from the third register 48 d of the pixel circuit 40 provided corresponding to the pixel 2 c adjacent to the corresponding pixel 2 c among each of the plurality of pixel circuits 40 .

[0159] For a radiation detector in which the first register 48a is omitted as described above, all of the above embodiments and variations can be applied. For example, the radiation detector may have the pixel point circuit 48 of the first embodiment, and the number of bits of the adder 48c may be X+Y bits, which is the same number as the number of bits of the second register 48b and the third register 48d. Alternatively, the radiation detector has the pixel point circuit 48A of the second embodiment, and the number of bits of the adder 48e may be 1 bit. The radiation detector can switch between the first TDI action and the second TDI action. The first TDI action is a TDI action that transfers the carriers generated in each pixel 2c to the adjacent pixel 2c column by column along the first direction A1. The second TDI action is a TDI action that transfers the carriers generated in each pixel 2c to the adjacent pixel 2c in the second direction A2, which is the opposite direction of the first direction A1. In addition to the TDI action, the radiation detector can also function as a rolling shutter. In the radiation detector, the detection system 49 of each of the plurality of pixel circuits 40 includes: a second register 48b that holds the third data D3 transferred from the third register 48d in the pixel circuit 40 corresponding to the pixel 2c adjacent to the corresponding pixel 2c as the second data D2; an adder 48c that generates the third data D3 by adding the count value of the counter 47, i.e., the first data D1, to the second data D2; and a third register 48d that holds the generated third data D3. With such a configuration, it is not necessary to write (load) the count value in the pixel circuit 40 of the previous stage into the counter 47 of each pixel circuit 40. Therefore, the non-operation period of the counter 47 can be shortened. Therefore, the ratio of the operation period of the counter 47 in each pixel circuit 40, i.e., the period for detecting radiation R, to the entire operation period of the pixel circuit 40 can be increased.

Claims

1. A radiation detector, wherein: Include: a conversion unit including a plurality of pixels that generate carriers in response to incident radiation, the plurality of pixels being arranged in a predetermined direction; and a plurality of pixel circuits, each of which is provided corresponding to each of the plurality of pixels and each of which has at least one detection system for reading out carriers from the corresponding pixel, The at least one detection system has: a comparator that compares a first signal based on the amount of the carriers with a threshold value and outputs a second signal when the first signal exceeds the threshold value; a counter for counting the number of the second signals; a first register for holding a count value obtained by the counter, i.e., first data; a second register for holding second data; an adder that generates third data by adding the first data and the second data; and a third register, which holds the third data, The second data is the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel among each of the plurality of pixel circuits.

2. The radiation detector according to claim 1, wherein: The adder comprises: at least one of the first register, the second register and the third register, and The at least one detection system has, in addition to the adder, other registers other than the at least one register among the first register, the second register, and the third register.

3. The radiation detector according to claim 1 or 2, wherein: In each of the multiple pixel circuits, the area of ​​the first region occupied by the analog circuit is larger than the area of ​​the second region occupied by the digital circuit, wherein the analog circuit includes the comparator; and the digital circuit includes the counter, the first register, the second register, the adder and the third register.

4. The radiation detector according to claim 3, wherein: The area of ​​the first region occupies more than half of the entire area of ​​each of the plurality of pixel circuits.

5. The radiation detector according to any one of claims 1 to 4, wherein: Each of the plurality of pixel circuits has a plurality of detection systems as the at least one detection system, The thresholds of the comparators of the plurality of detection systems are values ​​that differ for each of the detection systems.

6. The radiation detector according to claim 5, wherein: The adders of the plurality of detection systems are individually provided for each of the detection systems.

7. The radiation detector according to claim 5, wherein: The adders of each of the plurality of detection systems are shared by the plurality of detection systems.

8. The radiation detector according to any one of claims 1 to 7, wherein: The number of bits of the second register is equal to or larger than the sum of the number of bits of the first register and the number of bits obtained by expressing the number of the plurality of pixel circuits in binary. The number of bits of the adder is the same as the number of bits of the second register.

9. The radiation detector according to any one of claims 1 to 8, wherein: The number of bits of the second register is equal to or larger than the sum of the number of bits of the first register and the number of bits obtained by expressing the number of the plurality of pixel circuits in binary. The number of bits of the adder is less than the number of bits of the second register, The adder repeatedly adds and outputs a portion of bits of the first data in the first register and a portion of bits of the second data in the second register corresponding to the portion of bits until all bits of the first data are added.

10. The radiation detector according to claim 9, wherein: The number of bits of the adder is 1 bit, The adder has a fourth register for holding a carry signal.

11. The radiation detector according to any one of claims 1 to 10, wherein: Each of the plurality of pixel circuits further comprises: A charge sharing countermeasure circuit, which, when dispersing the carriers generated by the incidence of the radiation to two or more pixel circuits and reading them out, determines the pixel corresponding to the position where the radiation is incident, thereby correcting the amount of carriers in the pixel and evaluating it, or ignoring the incidence of the radiation.

12. The radiation detector according to any one of claims 1 to 11, wherein: The plurality of pixel circuits further include a switching unit configured to switch between an operation of transferring the third data in the predetermined direction and an operation of transferring the third data in a direction opposite to the predetermined direction.

13. The radiation detector according to any one of claims 1 to 12, wherein: Each of the plurality of pixel circuits further includes a shaping circuit provided at a preceding stage of the comparator. The shaping circuit reduces a time constant of the first signal.

14. The radiation detector according to any one of claims 1 to 13, wherein: The plurality of pixel circuits include a first pixel circuit region and a second pixel circuit region. The first pixel circuit region and the second pixel circuit region have different timings for holding the first data in the first register.

15. The radiation detector according to claim 14, wherein: further comprising: a power supply that supplies a power supply voltage to each of the plurality of pixel circuits via a power transmission line; and a control unit that sends a holding signal to each of the plurality of pixel circuits via a signal line, The second pixel circuit region and the first pixel circuit region are arranged along a predetermined direction, The direction in which the transmission line branches intersects with the direction in which the signal line branches and the prescribed direction.

16. An integrated circuit, wherein: The device comprises: a plurality of pixel circuits, each of which is provided corresponding to a plurality of pixels that generate carriers in response to incident radiation, and each of which has at least one detection system for reading out the carriers from the corresponding pixel, wherein the plurality of pixels are arranged in a predetermined direction, The at least one detection system has: a comparator that compares a first signal based on the amount of the carriers with a threshold value and outputs a second signal when the first signal exceeds the threshold value; a counter for counting the number of the second signals; a first register for holding a count value obtained by the counter, i.e., first data; a second register for holding second data; an adder that generates third data by adding the first data and the second data; and a third register, which holds the third data, The second data is the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel among each of the plurality of pixel circuits.

17. A radiation detection method, wherein: have: A step of generating carriers in response to incident radiation in a plurality of pixels arranged in a predetermined direction; In a plurality of pixel circuits provided corresponding to the plurality of pixels, respectively, a step of reading out carriers from the corresponding pixels; a step of comparing a first signal based on the amount of the carriers with a threshold value, and outputting a second signal when the first signal exceeds the threshold value; a step of counting the number of said second signals; a step of storing the count value obtained in the counting step, that is, the first data, in a first register; The step of holding the second data in the second register; a step of generating third data by adding the first data to the second data; and The step of maintaining the third data in the third register, The second data is the third data transferred from the third register of the pixel circuit provided corresponding to the pixel adjacent to the corresponding pixel among each of the plurality of pixel circuits.

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