Wafer defect detection method, device and equipment and computer readable storage medium

Abstract

The invention discloses a wafer defect detection method, a wafer defect detection device, wafer defect detection equipment and a computer readable storage medium. The wafer defect detection method comprises the following steps: manufacturing different chip matching templates under different objective lens amplification factors; wherein the chip matching template is a chip image without defects; shooting chip images of the wafer under different objective lens magnification factors, and comparing the chip images with the chip matching templates of the corresponding objective lens magnification factors to identify different chip defects on the wafer; and inputting the identified chip defects into a first deep learning model for defect classification. According to the method and the device, the chip images of the wafer are shot under different objective lens magnification factors and are compared with the chip matching templates of the corresponding objective lens magnification factors, so that different chip defects under different objective lens magnification factors can be automatically identified, and compared with manual visual inspection, the wafer detection efficiency can be greatly improved; and the problem caused by insufficient number of some defect samples when a deep learning algorithm is adopted for detection can be solved.

Description

Technical Field

[0001] The present application relates to the field of wafer inspection technology, and in particular to a wafer defect inspection method, device, equipment and computer-readable storage medium. Background Art

[0002] At present, wafers, as a basic material for semiconductor devices, are prone to various surface or internal defects during their manufacturing process, which can seriously affect the performance and yield of integrated circuits. In order to ensure that the produced wafers meet quality requirements, manufacturers usually perform defect detection on the surface of the wafers.

[0003] In the related art, defects of silicon photonics wafers are generally detected by manual visual inspection, which involves visually distinguishing defects through wafer images or manually inspecting wafer quality under a microscope. This detection method is inefficient and has large errors. For large enterprises and production lines with large production volumes, the efficiency of this defect detection method cannot meet the production requirements of the enterprise. At the same time, the mental state of the inspectors also greatly affects the accuracy of manual inspection, which is prone to false inspections and missed inspections. In addition, different inspectors have different understandings of quality inspection standards. Therefore, traditional manual visual inspection methods can no longer meet the growing detection needs in the industry. Moreover, due to the large number of defect samples on the wafer and the small number of some defect types, it is easy to overfit directly using deep learning algorithms for training, and the detection effect does not meet the requirements.

[0004] Therefore, it is necessary to design a new wafer defect detection method to overcome the above problems. Summary of the invention

[0005] The present application provides a wafer defect detection method, device, equipment and computer-readable storage medium, which can solve the technical problems existing in the related art that the traditional manual visual inspection method cannot meet the growing detection needs in the industry and the detection effect directly using the deep learning algorithm cannot meet the requirements.

[0006] In a first aspect, an embodiment of the present application provides a wafer defect detection method, the wafer defect detection method comprising:

[0007] Making different chip matching templates under different objective lens magnifications; wherein the chip matching template is an image of a chip without defects;

[0008] Capture chip images of the wafer at different objective lens magnifications, and compare them with chip matching templates of corresponding objective lens magnifications to identify different chip defects on the wafer;

[0009] The identified chip defects are input into the first deep learning model for defect classification.

[0010] In combination with the first aspect, in one embodiment, making different chip matching templates under different objective lens magnifications includes:

[0011] Under the same objective lens magnification, select a certain number of chips of the same type;

[0012] Photograph the selected chips of the same type;

[0013] Perform pixel averaging on the captured image and generate a chip matching template based on the averaged pixels;

[0014] Switch to another objective lens magnification and repeat the above steps of shooting and pixel averaging to prepare a chip matching template under another objective lens magnification.

[0015] In combination with the first aspect, in one implementation, before performing pixel averaging on the captured images, the following steps are further included:

[0016] Marking points are selected on the selected chips of the same type, and pixels of the captured multiple images are stacked based on the selected marking points.

[0017] In combination with the first aspect, in one implementation, the chip images of the wafer are photographed at different objective lens magnifications, and compared with chip matching templates of corresponding objective lens magnifications to identify different chip defects on the wafer, including:

[0018] Under the magnification of the first objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a first image;

[0019] Compare the first image with a chip matching template produced under the magnification of the first objective lens to identify dirt and edge collapse defects of the chip on the wafer surface;

[0020] Under the magnification of the second objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a second image;

[0021] The second image is compared with a chip matching template made under a second objective lens magnification to identify scratches and metal line color defects on the chip on the wafer surface; wherein the second objective lens magnification is greater than the first objective lens magnification.

[0022] In combination with the first aspect, in one implementation, the chip images of the wafer are photographed at different objective lens magnifications, and compared with chip matching templates of corresponding objective lens magnifications to identify different chip defects on the wafer, further comprising:

[0023] Under the magnification of the third objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a third image;

[0024] The third image is compared with a chip matching template made under a third objective lens magnification to identify pitting and bulging defects of the chip on the wafer surface; wherein the third objective lens magnification is greater than the second objective lens magnification.

[0025] In combination with the first aspect, in one implementation, the wafer defect detection method further includes:

[0026] Under a fourth objective lens magnification, capturing a chip image at a specific area of ​​the wafer to obtain a fourth image;

[0027] The fourth image is input into the trained second deep learning model for detection to identify exposed copper on the pad of the chip on the wafer and dirty optical port; wherein the magnification of the fourth objective lens is greater than the magnification of the third objective lens.

[0028] In combination with the first aspect, in one implementation, after inputting the identified chip defects into the first deep learning model for defect classification, the method further includes:

[0029] Mark the entire wafer map according to the defect classification results and the location information of the chip where the defect is located; different defects are marked with different colors, and the colors corresponding to the defects with high priority are displayed on the wafer map first according to the preset priority;

[0030] Output wafer map with defect information marked.

[0031] In a second aspect, an embodiment of the present application provides a wafer defect detection device, the wafer defect detection device comprising:

[0032] A template making module, which is used to make different chip matching templates under different objective lens magnifications; wherein the chip matching template is a chip image without defects;

[0033] A chip image acquisition module, which is used to acquire chip images of the wafer under different objective lens magnifications;

[0034] A defect recognition module is used to compare the chip image of the wafer with the chip matching template of the corresponding objective lens magnification to identify different chip defects on the wafer;

[0035] A classification module is used to input the identified chip defects into the first deep learning model to classify the defects.

[0036] In the third aspect, an embodiment of the present application provides a wafer defect detection device, which includes a processor, a memory, and a wafer defect detection program stored in the memory and executable by the processor, wherein when the wafer defect detection program is executed by the processor, the steps of the above-mentioned wafer defect detection method are implemented.

[0037] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a wafer defect detection program is stored, wherein when the wafer defect detection program is executed by a processor, the steps of the above-mentioned wafer defect detection method are implemented.

[0038] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:

[0039] By taking chip images of the wafer at different objective lens magnifications and comparing them with chip matching templates of corresponding objective lens magnifications, different chip defects at different objective lens magnifications can be automatically identified. Compared with manual visual inspection, the efficiency of wafer inspection can be greatly improved, and the problem of insufficient number of certain defect samples when using deep learning algorithms for detection can be compensated, thereby realizing the detection of multiple defects on the wafer. This solves the technical problems in related technologies that traditional manual visual inspection methods cannot meet the growing detection needs in the industry and that the detection effect directly using deep learning algorithms cannot meet the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a process flow of an embodiment of a wafer defect detection method of the present application;

[0041] Figure 2 A schematic diagram of a process flow of another embodiment of the wafer defect detection method of the present application;

[0042] Figure 3 This is a schematic diagram of the hardware structure of the wafer defect detection equipment involved in the embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] Since silicon-based optoelectronic wafers have very high requirements for surface defects, and the manual visual inspection method is inefficient and has large errors, it cannot meet the production requirements of enterprises. Not only that, due to the large number of defect samples on the wafer and the small number of some defect types, it is easy to overfit directly with deep learning algorithms for training, and the detection effect does not meet the requirements. And some defects are not particularly obvious even when observed at high magnification and the difference between images without defects. Such defects are not detected well using traditional image algorithms. In addition, in actual production, some defects such as dirt can be removed through post-processing. Marking all defects in the same form is not conducive to subsequent chip selection. Therefore, in order to meet the needs of defect detection of silicon photonic wafers, this application has developed a wafer defect detection method based on template matching and deep learning.

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0046] In a first aspect, an embodiment of the present application provides a wafer defect detection method.

[0047] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the wafer defect detection method of the present application. Figure 1 As shown, the wafer defect detection method includes:

[0048] S1: different chip matching templates are produced under different objective lens magnifications; wherein the chip matching template is an image of a chip without defects.

[0049] S2: Capture chip images of the wafer at different objective lens magnifications, and compare them with chip matching templates of corresponding objective lens magnifications to identify different chip defects on the wafer.

[0050] S3: Input the identified chip defects into the first deep learning model to classify the defects.

[0051] In the present embodiment, the wafer is generally composed of a lot of repetitive structures, each repetitive structure is composed of a certain number of chips, and each repetitive structure generally has a variety of chips, and different types of chip structures are different, so it is necessary to use different chip matching templates, and different defects on the chip also require different magnifications to detect, and different chip matching templates are also required. When making chip matching templates, not only can corresponding chip matching templates be made under different objective lens magnifications, but also corresponding different chip matching templates can be made for different types of chips. Each chip matching template is a complete chip image without defects. In the above step S3, the first deep learning model can be, for example, a residual network model or a DenseNet model.

[0052] This embodiment makes chip matching templates under different objective lens magnifications, and compares the chip images of the wafer taken under different objective lens magnifications with the chip matching templates of the corresponding objective lens magnifications. It can automatically identify different chip defects under different objective lens magnifications. Compared with manual visual inspection, the operation is simple, and the efficiency of wafer inspection can be greatly improved, and the error caused by manual visual inspection can be reduced. It is also highly flexible and specific templates can be made for defects in specific locations for detection.

[0053] At the same time, when making a chip matching template, only multiple chip images at the same position are needed to generate a perfect template. No particularly large sample size is required, which can make up for the problem of insufficient number of certain defect samples when using deep learning algorithms for detection, and realize the detection of multiple defects on the wafer. It solves the technical problems in related technologies that traditional manual visual inspection methods cannot meet the growing detection needs in the industry and the direct use of deep learning algorithms cannot meet the requirements of detection effects, which is conducive to the subsequent screening of chips on wafers.

[0054] Preferably, see Figure 2 As shown, before step S1, the wafer map (i.e., map) can be imported into the wafer defect detection machine, and then the rough calibration of the wafer horizontal position can be performed to facilitate the subsequent movement of the chuck plate (i.e., the carrier plate on which the wafer is placed). The rough calibration can be performed using the two-point coordinates of the wafer. Two points at the same default horizontal position are selected on the wafer, the vertical coordinates of the two points are read, and the angle difference is calculated, and then the chuck plate is rotated until the angle difference is 0. After the rough calibration is completed, the wafer map can be used to position the wafer.

[0055] Further, in one embodiment, the making of different chip matching templates under different objective lens magnifications may include:

[0056] S11: Under the same objective lens magnification, select a certain number of chips of the same type. In this step, the number of the selected chips is preferably greater than or equal to 6.

[0057] S12: Photographing the selected chips of the same type.

[0058] S13: averaging pixels of the captured image, and generating a chip matching template according to the averaged pixels.

[0059] S14: Switch to another objective lens magnification, and repeat the above steps of shooting and pixel averaging to prepare a chip matching template under another objective lens magnification.

[0060] In this embodiment, each chip matching template can be made in the manner of steps S11 to S13. When the chip matching template under a certain objective lens magnification is made, the next objective lens magnification is switched to continue to make the chip matching template under another objective lens magnification in the manner of steps S11 to S13, and the chip matching templates under all different objective lens magnifications are made in this reciprocating cycle. The chip matching template in this embodiment only needs multiple chip images at the same position to generate a perfect template, does not require a particularly large sample size, and will not have a situation where the sample size is insufficient.

[0061] Furthermore, in some optional embodiments, before the pixel averaging of the captured images, the following steps may be included: selecting marking points on the selected chips of the same type, and pixel stacking the captured multiple images based on the selected marking points. In this embodiment, between step S11 and step S12, marking points are selected at the same position on each chip, and then after the chip is photographed in step S12, the images of each chip are pixel stacked based on the previously selected marking points, so that the image positions of each chip are aligned. In this embodiment, it is preferred to select two marking points on each chip to identify the position of the chip; and it is convenient for the marking points to align the images of the chips, so as to facilitate the subsequent accurate calculation of pixels.

[0062] Further, in one embodiment, the capturing of chip images of the wafer at different objective lens magnifications and comparing with chip matching templates at corresponding objective lens magnifications to identify different chip defects on the wafer may include:

[0063] S21: Under the magnification of the first objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a first image.

[0064] In step S21, on the same chip of the wafer, according to a preset rule (eg, from left to right or from top to bottom), the chuck plate (ie, the carrier plate on which the wafer is placed) is moved and the chip image is captured to obtain a first image.

[0065] S22: Compare the first image with a chip matching template produced under the magnification of the first objective lens to identify dirt and edge collapse defects of the chip on the wafer surface.

[0066] In step S22, the magnification of the first objective lens is preferably 2.5X. At 2.5X magnification, the first image is compared with the corresponding chip matching template, and the inconsistent areas are regarded as defects and circled. This pass mainly detects the dirt and edge collapse of the wafer.

[0067] S23: Under the second objective lens magnification, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a second image.

[0068] S24: Compare the second image with a chip matching template made under a second objective lens magnification to identify scratches and metal line color defects on the chip on the wafer surface; wherein the second objective lens magnification is greater than the first objective lens magnification.

[0069] In this embodiment, after inspecting the entire wafer at 2.5X magnification, switch to the second objective lens magnification, which is preferably 10X. At this magnification, move the chuck plate and take an image to obtain a second image. The second image is matched and compared with the chip matching template to identify scratches on the wafer surface and the color of the metal lines.

[0070] Based on the above technical solution, in one embodiment, the chip images of the wafer are photographed at different objective lens magnifications, and compared with the chip matching templates of the corresponding objective lens magnifications to identify different chip defects on the wafer, and may also include:

[0071] S25: Under the magnification of the third objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a third image.

[0072] S26: Compare the third image with a chip matching template made under a third objective lens magnification to identify pitting and bulging defects of the chip on the wafer surface; wherein the third objective lens magnification is greater than the second objective lens magnification.

[0073] In this embodiment, after inspecting the entire wafer at 10X magnification, switch to the third objective lens magnification, preferably 20X, at this magnification, move the chuck plate and take an image to obtain a third image, and match and compare the third image with the chip matching template to identify pitting and bulges on the wafer surface. In the above steps S21 to S26, a different chip matching template is selected each time according to the position of the chip to be detected and the type of defect to be detected; and each time a defect is identified, a template matching algorithm is used for identification, such as the template matching method in penCV, cv2.matchTemplate is a simple and efficient template matching algorithm.

[0074] Of course, in other embodiments, the objective lens magnification may be set to other values ​​according to actual needs, not limited to 2.5X, 10X and 20X.

[0075] Based on the above technical solution, in one embodiment, the wafer defect detection method may further include:

[0076] S27: Under the fourth objective lens magnification, capture a chip image in a specific area of ​​the wafer to obtain a fourth image.

[0077] S28: Input the fourth image into the trained second deep learning model for detection to identify exposed copper on the pad of the chip on the wafer and dirty optical port; wherein the magnification of the fourth objective lens is greater than the magnification of the third objective lens.

[0078] In this embodiment, the magnification of the fourth objective lens is preferably 50X. Under this magnification, a fourth image is obtained by photographing a specific area of ​​the wafer, and the fourth image is input into the second deep learning model (such as Yolo v9 model) for detection. This pass mainly detects subtle defects on the surface of the wafer, such as pad copper leakage (that is, the pad needle is inserted too deep to expose the internal copper layer) and optical port contamination. Figure 2 As shown, in the above embodiment, when the objective lens magnification is 2.5X, 10X and 20X, the template matching algorithm is used to identify defects, and when the objective lens magnification is 50X, the Yolo v9 model is used for defect detection; that is, in this embodiment, small defects on the wafer surface are detected by the Yolo algorithm, and other defects are detected by template matching, so that the detection efficiency is greatly improved.

[0079] Furthermore, in one embodiment, after inputting the identified chip defects into the first deep learning model to classify the defects, the following may also be included:

[0080] S4: marking the entire wafer map (i.e., map) according to the defect classification results and the location information of the chip where the defect is located; wherein different defects are marked with different colors, and the colors corresponding to the defects with high priority are preferentially displayed on the wafer map according to the preset priority;

[0081] S5: Outputting a wafer image marked with defect information.

[0082] In this embodiment, different priorities can be set in advance for different defects, some defects have high priorities, and some defects have low priorities. There may be multiple defects on a chip at the same time. The color of the defect with high priority is displayed first on the map, and the final map result with defect information is output. In the end, this embodiment uses the model to classify defects and output a marked wafer map to facilitate data transmission in subsequent processes.

[0083] In the related art, due to the insufficient number of defect samples, it is difficult to establish a sufficient database using deep learning; and some defects are not very obvious and difficult to detect using traditional image algorithms. The embodiment of the present application provides a wafer defect detection method that is compatible with the detection of these two types of defects. In actual production, the tolerance of different defects is different, and some defects can be removed through later manual processing. Therefore, this application uses different colors to mark different defects, and the production of wafer images with defect marks can facilitate production personnel to select chips. The wafer defect detection method of the present application is not only highly automated and easy to operate, but also can generate wafer images with defect marks.

[0084] In a second aspect, an embodiment of the present application also provides a wafer defect detection device.

[0085] In one embodiment, a wafer defect detection device includes: a template making module, which is used to make different chip matching templates under different objective lens magnifications; wherein the chip matching template is a chip image without defects; a chip image acquisition module, which is used to acquire chip images of the wafer under different objective lens magnifications; a defect recognition module, which is used to compare the chip image of the wafer with the chip matching template of the corresponding objective lens magnification to identify different chip defects on the wafer; and a classification module, which is used to input the identified chip defects into the first deep learning model for defect classification.

[0086] Among them, the functional implementation of each module in the above-mentioned wafer defect detection device corresponds to the various steps in the above-mentioned wafer defect detection method embodiment, and its functions and implementation processes will not be repeated here one by one.

[0087] In a third aspect, an embodiment of the present application provides a wafer defect detection device, which may be a personal computer (PC), a laptop computer, a server, or other device with data processing capabilities.

[0088] Reference Figure 3 , Figure 3 Schematic diagram of the hardware structure of the wafer defect detection device involved in the embodiment of the present application. In the embodiment of the present application, the wafer defect detection device may include a processor, a memory, a communication interface and a communication bus.

[0089] The communication bus may be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0090] The communication interface includes input / output (I / O) interface, physical interface and logical interface, etc., which are used to realize the interconnection of devices inside the wafer defect detection equipment, and the interface used to realize the interconnection between the wafer defect detection equipment and other devices (such as other computing devices or user devices). The physical interface can be an Ethernet interface, a fiber optic interface, an ATM interface, etc.; the user device can be a display, a keyboard, etc.

[0091] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0092] The processor may be a general-purpose processor, and the general-purpose processor may call the wafer defect detection program stored in the memory, and execute the wafer defect detection method provided by the embodiment of the present application. For example, the general-purpose processor may be a central processing unit (central processing unit, CPU). Wherein, the method executed when the wafer defect detection program is called may refer to the various embodiments of the wafer defect detection method of the present application, and will not be repeated here.

[0093] Those skilled in the art will understand that Figure 3 The hardware structure shown in the figure does not constitute a limitation on the present application, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0094] In a fourth aspect, an embodiment of the present application also provides a readable storage medium.

[0095] A wafer defect detection program is stored on a readable storage medium of the present application, wherein when the wafer defect detection program is executed by a processor, the steps of the wafer defect detection method as described above are implemented.

[0096] Among them, the method implemented when the wafer defect detection program is executed can refer to the various embodiments of the wafer defect detection method of the present application, and will not be repeated here.

[0097] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0098] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0099] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0100] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0101] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0102] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0103] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A wafer defect detection method, characterized in that: The wafer defect detection method comprises: Making different chip matching templates under different objective lens magnifications; wherein the chip matching template is an image of a chip without defects; Capture chip images of the wafer at different objective lens magnifications, and compare them with chip matching templates of corresponding objective lens magnifications to identify different chip defects on the wafer; The identified chip defects are input into the first deep learning model for defect classification.

2. The wafer defect detection method according to claim 1, characterized in that: The method of making different chip matching templates under different objective lens magnifications includes: Under the same objective lens magnification, select a certain number of chips of the same type; Photograph the selected chips of the same type; Perform pixel averaging on the captured image and generate a chip matching template based on the averaged pixels; Switch to another objective lens magnification and repeat the above steps of shooting and pixel averaging to prepare a chip matching template under another objective lens magnification.

3. The wafer defect detection method according to claim 2, characterized in that: Before performing pixel averaging on the captured images, the method further includes the following steps: Marking points are selected on the selected chips of the same type, and pixels of the captured multiple images are stacked based on the selected marking points.

4. The wafer defect detection method according to claim 1, characterized in that: The chip images of the wafer are photographed at different objective lens magnifications, and compared with the chip matching templates of the corresponding objective lens magnifications to identify different chip defects on the wafer, including: Under the magnification of the first objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a first image; Compare the first image with a chip matching template produced under the magnification of the first objective lens to identify dirt and edge collapse defects of the chip on the wafer surface; Under the magnification of the second objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a second image; The second image is compared with a chip matching template made under a second objective lens magnification to identify scratches and metal line color defects on the chip on the wafer surface; wherein the second objective lens magnification is greater than the first objective lens magnification.

5. The wafer defect detection method according to claim 4, characterized in that: The method of photographing chip images of the wafer at different objective lens magnifications and comparing them with chip matching templates at corresponding objective lens magnifications to identify different chip defects on the wafer further includes: Under the magnification of the third objective lens, the wafer is moved according to a preset rule and a chip image of the wafer is captured to obtain a third image; The third image is compared with a chip matching template made under a third objective lens magnification to identify pitting and bulging defects of the chip on the wafer surface; wherein the third objective lens magnification is greater than the second objective lens magnification.

6. The wafer defect detection method according to claim 5, characterized in that: The wafer defect detection method further includes: Under a fourth objective lens magnification, capturing a chip image at a specific area of ​​the wafer to obtain a fourth image; The fourth image is input into the trained second deep learning model for detection to identify exposed copper on the pad of the chip on the wafer and dirty optical port; wherein the magnification of the fourth objective lens is greater than the magnification of the third objective lens.

7. The wafer defect detection method according to claim 1, characterized in that: After inputting the identified chip defects into the first deep learning model to classify the defects, the method further includes: Mark the entire wafer map according to the defect classification results and the location information of the chip where the defect is located; different defects are marked with different colors, and the colors corresponding to the defects with high priority are displayed on the wafer map first according to the preset priority; Output wafer map marked with defect information.

8. A wafer defect detection device, characterized in that: The wafer defect detection device comprises: A template making module, which is used to make different chip matching templates under different objective lens magnifications; wherein the chip matching template is a chip image without defects; A chip image acquisition module, which is used to acquire chip images of the wafer under different objective lens magnifications; A defect recognition module is used to compare the chip image of the wafer with the chip matching template of the corresponding objective lens magnification to identify different chip defects on the wafer; A classification module is used to input the identified chip defects into the first deep learning model to classify the defects.

9. A wafer defect detection device, characterized in that: The wafer defect detection device includes a processor, a memory, and a wafer defect detection program stored in the memory and executable by the processor, wherein when the wafer defect detection program is executed by the processor, the steps of the wafer defect detection method as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a wafer defect detection program, wherein when the wafer defect detection program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 7 are implemented.

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