Reference local oscillator circuit system for realizing GPS taming and high-resolution reference input
By designing a reference local oscillator circuit system for multiple phase lock circuits and signal processing units, the reference input problem that is difficult to achieve high phase noise, high resolution and high stability in the prior art is solved, and efficient reference local oscillator signal output is achieved, meeting the high requirements of modern communication systems.
Patent Information
- Application Number
- CN202411459767.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-03-11
AI Technical Summary
The prior art is difficult to achieve GPS taming and high resolution reference input under conditions of high phase noise, high resolution and high stability. Especially in the fields of satellite navigation and electronic communication, the accuracy and stability of reference local oscillator are required, but existing frequency standard sources cannot meet these needs.
A reference local oscillator circuit system is designed, which includes a multi-phase locking circuit, including an integer phase locking loop, a decimal phase locking loop and a GPS second pulse phase locking circuit. Through these phase locking circuits and signal processing units, multiplexing and frequency conversion amplification of the reference clock signal is realized, and high phase noise, high resolution and high stability reference local oscillator signals are output.
It realizes the output of high stability reference local oscillator signals under high phase noise and high resolution conditions, with good flexibility and performance indicators, and meets the high requirements of modern communication systems for reference local oscillator.
Smart Images
Figure CN119602788A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of frequency synthesis, in particular to the field of crystal oscillators, and specifically refers to a reference local oscillator circuit system for realizing GPS taming and high-resolution reference input. Background Art
[0002] With the continuous development of modern communication systems, the system's external reference input frequency for the reference local oscillator is no longer a single frequency, but there are requirements for various frequency points. In order to achieve high-resolution reference input while ensuring low phase noise signal quality, a fractional frequency phase-locked loop is generally used. However, compared with integer frequency division, fractional frequency division still has certain phase noise deterioration and spurious. In addition, in the fields of satellite navigation, electronic communications, etc., there are also higher requirements for the accuracy and stability of the reference local oscillator, but the primary frequency standard source, such as the cesium atomic clock, is expensive, and the secondary frequency standard source, the crystal oscillator, cannot meet today's stability requirements. Taming the crystal oscillator through the GPS second pulse can make the crystal oscillator have good stability. Summary of the invention
[0003] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a reference local oscillator circuit system that meets the requirements of high phase noise, high resolution and high stability for realizing GPS discipline and high-resolution reference input.
[0004] In order to achieve the above object, the reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input of the present invention is as follows:
[0005] The reference local oscillator circuit system for realizing GPS taming and high-resolution reference input has the following main features: the system comprises a first selection switch, a first phase-locked circuit, a second phase-locked circuit, a third phase-locked circuit, a second selection switch, a first voltage-controlled crystal oscillator, a first signal processing unit and a third selection switch.
[0006] The input end of the first selection switch receives a reference clock signal, the output end of the first selection switch is respectively connected to the input ends of the first phase-locked circuit, the second phase-locked circuit and the third phase-locked circuit, and the output ends of the first phase-locked circuit, the second phase-locked circuit and the third phase-locked circuit are all connected to the input end of the second selection switch; the output end of the second selection switch is connected to the input end of the first voltage-controlled crystal oscillator; the output end of the first voltage-controlled crystal oscillator is connected to the input end of the first signal processing unit; the output end of the first signal processing unit outputs the required reference local oscillator signal; the feedback end is output to the input end of the third selection switch according to the corresponding input reference signal, and the output end of the third selection switch is input to the corresponding phase-locked circuit.
[0007] Preferably, the output end of the first selection switch is output to the corresponding phase-locked circuit according to the input frequency, specifically:
[0008] The integer frequency reference clock signal is input into the first phase-locked circuit, the fractional frequency reference clock signal is input into the second phase-locked circuit, and the GPS second pulse signal is input into the third phase-locked circuit.
[0009] Preferably, the first phase-locked circuit includes a first integer phase-locked loop and a first loop filter, the reference clock signal input by the first selection switch enters the reference input terminal of the first integer phase-locked loop, and the feedback signal input by the third selection switch enters the feedback input terminal of the first integer phase-locked loop. After the first integer phase-locked loop compares the phases of the two, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first integer phase-locked loop, and enters the second selection switch after low-pass filtering through the first loop filter.
[0010] Preferably, the second phase-locked circuit includes a first fractional phase-locked loop and a second loop filter, the reference clock signal input by the first selection switch enters the reference input terminal of the first fractional phase-locked loop, and the feedback signal input by the third selection switch enters the feedback input terminal of the first fractional phase-locked loop. After the first fractional phase-locked loop compares the phases of the two, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first fractional phase-locked loop, and enters the second selection switch after low-pass filtering through the second loop filter.
[0011] Preferably, the third phase-locked circuit includes a first FPGA and a first analog-to-digital converter. The reference clock signal input by the first selection switch and the feedback signal input by the third selection switch are respectively input into the first FPGA. After the first FPGA processes the two signals, it outputs the frequency difference in the form of a code value to the first analog-to-digital converter; based on this, the first analog-to-digital converter outputs a corresponding voltage value to the second selection switch.
[0012] Preferably, the output end of the second selection switch selects a corresponding voltage output first voltage-controlled crystal oscillator according to the frequency of the reference clock input, specifically:
[0013] The integer frequency reference clock signal selects the input voltage of the first phase-locked circuit, the fractional frequency reference clock signal selects the input voltage of the second phase-locked circuit, and the GPS second pulse selects the input voltage of the third phase-locked circuit.
[0014] Preferably, after receiving the voltage output by the second selection switch, the first voltage-controlled crystal oscillator outputs a corresponding reference local oscillator frequency to the first signal processing unit.
[0015] Preferably, the first signal processing unit is used to perform the required frequency conversion and amplification processing on the reference local oscillator signal, and then input the reference local oscillator signal as a feedback signal to the third selection switch, and output it as a final reference local oscillator signal.
[0016] Preferably, the output end of the third selection switch is output to the corresponding phase-locked circuit as a feedback signal according to the frequency of the reference clock input, specifically:
[0017] The integer frequency reference clock signal is input into the first phase-locked circuit, the fractional frequency reference clock signal is input into the second phase-locked circuit, and the GPS second pulse is input into the third phase-locked circuit.
[0018] The reference local oscillator circuit system for realizing GPS taming and high-resolution reference input of the present invention can realize output of high phase noise, high resolution and high stability reference clock signals respectively through multi-path phase locking. The present invention can realize high resolution and wide range reference clock input through fractional phase-locked loop, and has good flexibility; through integer phase-locked loop, it can realize good phase noise index and spurious performance, and ensure the performance index of key frequency points; through GPS second pulse taming crystal oscillator, it can output high stability reference local oscillator signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 The present invention is a schematic diagram of the circuit structure of a reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input.
[0020] Figure 2 The present invention is a schematic diagram of the circuit structure of the first phase-locked circuit of the reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input.
[0021] Figure 3 The present invention is a schematic diagram of the circuit structure of the second phase-locked circuit of the reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input.
[0022] Figure 4 The present invention is a schematic diagram of the circuit structure of the third phase-locked circuit of the reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input.
[0023] Figure 5 The present invention is a schematic diagram of the circuit structure of the first signal processing unit of the reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input. DETAILED DESCRIPTION
[0024] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.
[0025] The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input of the present invention comprises a first selection switch, a first phase-locked circuit, a second phase-locked circuit, a third phase-locked circuit, a second selection switch, a first voltage-controlled crystal oscillator, a first signal processing unit and a third selection switch.
[0026] The input end of the first selection switch receives a reference clock signal, the output end of the first selection switch is respectively connected to the input ends of the first phase-locked circuit, the second phase-locked circuit and the third phase-locked circuit, and the output ends of the first phase-locked circuit, the second phase-locked circuit and the third phase-locked circuit are all connected to the input end of the second selection switch; the output end of the second selection switch is connected to the input end of the first voltage-controlled crystal oscillator; the output end of the first voltage-controlled crystal oscillator is connected to the input end of the first signal processing unit; the output end of the first signal processing unit outputs the required reference local oscillator signal; the feedback end is output to the input end of the third selection switch according to the corresponding input reference signal, and the output end of the third selection switch is input to the corresponding phase-locked circuit.
[0027] As a preferred embodiment of the present invention, the output end of the first selection switch is output to the corresponding phase-locked circuit according to the input frequency, specifically:
[0028] The integer frequency reference clock signal is input into the first phase-locked circuit, the fractional frequency reference clock signal is input into the second phase-locked circuit, and the GPS second pulse signal is input into the third phase-locked circuit.
[0029] As a preferred embodiment of the present invention, the first phase-locked circuit includes a first integer phase-locked loop and a first loop filter, the reference clock signal input by the first selection switch enters the reference input terminal of the first integer phase-locked loop, the feedback signal input by the third selection switch enters the feedback input terminal of the first integer phase-locked loop, and after the first integer phase-locked loop compares the phases of the two, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first integer phase-locked loop, and enters the second selection switch after low-pass filtering through the first loop filter.
[0030] As a preferred embodiment of the present invention, the second phase-locked circuit includes a first fractional phase-locked loop and a second loop filter, the reference clock signal input by the first selection switch enters the reference input terminal of the first fractional phase-locked loop, the feedback signal input by the third selection switch enters the feedback input terminal of the first fractional phase-locked loop, and after the first fractional phase-locked loop compares the phases of the two, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first fractional phase-locked loop, and enters the second selection switch after low-pass filtering through the second loop filter.
[0031] As a preferred embodiment of the present invention, the third phase-locked circuit includes a first FPGA and a first analog-to-digital converter. The reference clock signal input by the first selection switch and the feedback signal input by the third selection switch are respectively input into the first FPGA. After the first FPGA processes the two signals, the frequency difference is output to the first analog-to-digital converter in the form of a code value; based on this, the first analog-to-digital converter outputs a corresponding voltage value to the second selection switch.
[0032] As a preferred embodiment of the present invention, the output end of the second selection switch selects the corresponding voltage output of the first voltage-controlled crystal oscillator according to the frequency of the reference clock input, specifically:
[0033] The integer frequency reference clock signal selects the input voltage of the first phase-locked circuit, the fractional frequency reference clock signal selects the input voltage of the second phase-locked circuit, and the GPS second pulse selects the input voltage of the third phase-locked circuit.
[0034] As a preferred embodiment of the present invention, after receiving the voltage output by the second selection switch, the first voltage-controlled crystal oscillator outputs the corresponding reference local oscillator frequency to the first signal processing unit.
[0035] As a preferred embodiment of the present invention, the first signal processing unit is used to perform the required frequency conversion and amplification processing on the reference local oscillator signal, and then input the reference local oscillator signal as a feedback signal to the third selection switch and output it as the final reference local oscillator signal.
[0036] As a preferred embodiment of the present invention, the output end of the third selection switch is output to the corresponding phase-locked circuit as a feedback signal according to the frequency of the reference clock input, specifically:
[0037] The integer frequency reference clock signal is input into the first phase-locked circuit, the fractional frequency reference clock signal is input into the second phase-locked circuit, and the GPS second pulse is input into the third phase-locked circuit.
[0038] In a specific implementation manner of the present invention, in this embodiment, the circuit outputs a 200M reference local oscillator signal, such as Figure 1 shown.
[0039] Taking 10MHz, 2.5MHz, and 1Hz reference clock signals as examples, when a 10MHz reference clock is input, the output of the first selection switch enters the first phase-locked circuit; when a 2.5MHz reference clock signal is input, the output of the first selection switch enters the second phase-locked circuit; when a 1Hz second pulse is input as the reference clock signal, the output of the first selection switch enters the third phase-locked circuit.
[0040] The first phase-locked circuit includes a first integer phase-locked loop and a first loop filter. The 10MHz reference clock signal input by the first selection switch enters the reference input terminal of the first integer phase-locked loop, and the 100MHz feedback signal input by the third selection switch enters the feedback input terminal of the first integer phase-locked loop. After the first integer phase-locked loop compares the phases of the two, the phase difference between the 10MHz reference clock signal and the 100MHz feedback signal is output through the charge pump of the first integer phase-locked loop, and after low-pass filtering by the first loop filter, enters the second selection switch as the tuning voltage of the first voltage-controlled crystal oscillator, such as Figure 2 shown.
[0041] The second phase-locked circuit includes a first fractional phase-locked loop and a second loop filter. The 2.5MHz reference clock signal input by the first selection switch enters the reference input terminal of the first fractional phase-locked loop, and the 100MHz feedback signal input by the third selection switch enters the feedback input terminal of the first fractional phase-locked loop. After the first fractional phase-locked loop compares the phases of the two, the phase difference between the 2.5MHz reference clock signal and the 100MHz feedback signal is output through the charge pump of the second fractional phase-locked loop, and after low-pass filtering through the second loop filter, enters the second selection switch as the tuning voltage of the first voltage-controlled crystal oscillator, such as Figure 3 shown.
[0042] The third phase-locked circuit includes a first FPGA and a first analog-to-digital converter. The 1Hz reference clock signal input by the first selection switch and the 100MHz feedback signal input by the third selection switch are respectively input into the first FPGA. After the first FPGA processes the two signals, it outputs the frequency difference in the form of a code value to the first analog-to-digital converter. Based on this, the first analog-to-digital converter outputs a corresponding voltage value to the second selection switch as a tuning voltage of the first voltage-controlled crystal oscillator, such as Figure 4 shown.
[0043] Furthermore, the output end of the second selection switch selects the corresponding voltage output of the first voltage-controlled crystal oscillator according to the frequency of the reference clock input: the 10MHz integer frequency reference clock signal selects the input voltage of the first phase-locked circuit, the 2.5MHz fractional frequency reference clock signal selects the input voltage of the second phase-locked circuit, and the 1Hz second pulse selects the input voltage of the third phase-locked circuit.
[0044] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.
[0045] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.
[0046] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.
[0047] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0048] The reference local oscillator circuit system for realizing GPS taming and high-resolution reference input of the present invention can realize output of high phase noise, high resolution and high stability reference clock signals respectively through multi-path phase locking. The present invention can realize high resolution and wide range reference clock input through fractional phase-locked loop, and has good flexibility; through integer phase-locked loop, it can realize good phase noise index and spurious performance, and ensure the performance index of key frequency points; through GPS second pulse taming crystal oscillator, it can output high stability reference local oscillator signal.
[0049] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.
Claims
1. A reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input, characterized in that: The system comprises a first selection switch, a first phase-locked circuit, a second phase-locked circuit, a third phase-locked circuit, a second selection switch, a first voltage-controlled crystal oscillator, a first signal processing unit and a third selection switch. The input end of the first selection switch receives a reference clock signal, the output end of the first selection switch is respectively connected to the input ends of the first phase-locked circuit, the second phase-locked circuit and the third phase-locked circuit, and the output ends of the first phase-locked circuit, the second phase-locked circuit and the third phase-locked circuit are all connected to the input end of the second selection switch; the output end of the second selection switch is connected to the input end of the first voltage-controlled crystal oscillator; the output end of the first voltage-controlled crystal oscillator is connected to the input end of the first signal processing unit; the output end of the first signal processing unit outputs the required reference local oscillator signal; the feedback end is output to the input end of the third selection switch according to the corresponding input reference signal, and the output end of the third selection switch is input to the corresponding phase-locked circuit.
2. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The output end of the first selection switch is output to the corresponding phase-locked circuit according to the input frequency, specifically: The integer frequency reference clock signal is input into the first phase-locked circuit, the fractional frequency reference clock signal is input into the second phase-locked circuit, and the GPS second pulse signal is input into the third phase-locked circuit.
3. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The first phase-locked circuit includes a first integer phase-locked loop and a first loop filter. The reference clock signal input by the first selection switch enters the reference input terminal of the first integer phase-locked loop, and the feedback signal input by the third selection switch enters the feedback input terminal of the first integer phase-locked loop. After the first integer phase-locked loop compares the phases of the two, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first integer phase-locked loop, and enters the second selection switch after low-pass filtering through the first loop filter.
4. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The second phase-locked circuit includes a first fractional phase-locked loop and a second loop filter. The reference clock signal input by the first selection switch enters the reference input terminal of the first fractional phase-locked loop, and the feedback signal input by the third selection switch enters the feedback input terminal of the first fractional phase-locked loop. After the first fractional phase-locked loop compares the phases of the two, the phase difference between the reference clock signal and the feedback signal is output through the charge pump of the first fractional phase-locked loop, and enters the second selection switch after low-pass filtering through the second loop filter.
5. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The third phase-locked circuit includes a first FPGA and a first analog-to-digital converter. The reference clock signal input by the first selection switch and the feedback signal input by the third selection switch are respectively input into the first FPGA. After the first FPGA processes the two signals, it outputs the frequency difference in the form of a code value to the first analog-to-digital converter; based on this, the first analog-to-digital converter outputs the corresponding voltage value to the second selection switch.
6. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The output end of the second selection switch selects the corresponding voltage output of the first voltage-controlled crystal oscillator according to the frequency of the reference clock input, specifically: The integer frequency reference clock signal selects the input voltage of the first phase-locked circuit, the fractional frequency reference clock signal selects the input voltage of the second phase-locked circuit, and the GPS second pulse selects the input voltage of the third phase-locked circuit.
7. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: After receiving the voltage output by the second selection switch, the first voltage-controlled crystal oscillator outputs the corresponding reference local oscillator frequency to the first signal processing unit.
8. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The first signal processing unit is used to perform the required frequency conversion and amplification processing on the reference local oscillator signal, and then input the reference local oscillator signal as a feedback signal to the third selection switch, and output it as a final reference local oscillator signal.
9. The reference local oscillator circuit system for realizing GPS discipline and high-resolution reference input according to claim 1, characterized in that: The output end of the third selection switch is output to the corresponding phase-locked circuit as a feedback signal according to the frequency of the reference clock input, specifically: The integer frequency reference clock signal is input into the first phase-locked circuit, the fractional frequency reference clock signal is input into the second phase-locked circuit, and the GPS second pulse is input into the third phase-locked circuit.