Chip and display device

Abstract

The invention discloses a chip and a display device, and the chip comprises an image receiving module which is used for transmitting an input image to a frame buffer under the triggering of a vertical synchronization signal, so as to store the input image in the frame buffer; the image display module is used for reading the input image stored in the frame buffer to obtain an output image, so that a display screen can display the output image; and the frame rate synchronization module is used for determining a tearing position range corresponding to the frame rates of the input image and the output image and determining a first reading position so as to adjust the speed of the image display module for reading the input image stored in the frame buffer according to the first reading position and the tearing position range. Therefore, the speed of reading the input image stored in the frame buffer by the image display module is adjusted through the frame rate synchronization module according to the range of the first reading position and the tearing position, so that each frame of output image is continuous and the input image and the output image are synchronous on the premise of a single frame buffer.

Description

Technical Field

[0001] The present application relates to the technical field of chips, and more specifically, to a chip and a display device. Background Art

[0002] When the Mobile Industry Processor Interface (MIPI) is in video mode, the hardware synchronization method is that the LCDC outputs a frame of output image under the trigger of the vertical synchronization signal. In other words, when the current LCDC output image frame is displayed, if the vertical synchronization signal has not been triggered, it will wait until the vertical synchronization signal is triggered before outputting the next frame of output image. However, this hardware synchronization method has the problem of discontinuous output image, which will cause the transmission channel (TX lane) to be pulled up, resulting in incompatibility of some display screens, resulting in display abnormalities.

[0003] In related technologies, two frame buffers are set up to store input images to achieve conversion of input and output images at any frame rate. This ensures the continuity of the output image and is compatible with input images corresponding to different frame rates and different display screens, but it requires higher hardware costs and increases chip costs. Summary of the invention

[0004] In view of the above problems, the present application proposes a chip and a display device, which can effectively ensure the continuity of the output image and effectively reduce the cost of the chip.

[0005] In a first aspect, an embodiment of the present application provides a chip, which includes: an image receiving module, an image display module, a frame buffer and a frame rate synchronization module, wherein the image receiving module, the frame buffer and the image display module are connected in sequence, and the image receiving module and the image display module are also respectively connected to the frame rate synchronization module, wherein: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal to store the input image in the frame buffer; the vertical synchronization signal is sent by a signal source to the image receiving module; the image display module is used to read the input image stored in the frame buffer to obtain an output image for displaying the output image on a display screen; the frame rate synchronization module is used to determine the tearing position range corresponding to the frame rates of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input moment of the vertical synchronization signal corresponding to the next frame of the input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range to change the frame rate of the output image displayed on the display screen.

[0006] In a second aspect, an embodiment of the present application further provides a display device, which includes: the above-mentioned chip and a display screen, the chip is used to send an output image to the display screen, and the display screen is used to display the output image.

[0007] The technical solution provided by the present application, the chip includes: an image receiving module, an image display module, a frame buffer and a frame rate synchronization module, the image receiving module, the frame buffer and the image display module are connected in sequence, and the image receiving module and the image display module are also respectively connected to the frame rate synchronization module, wherein: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal to store the input image in the frame buffer; the vertical synchronization signal is sent by a signal source to the image receiving module; the image display module is used to read the input image stored in the frame buffer to obtain an output image for displaying the output image on the display screen; the frame rate synchronization module is used to determine the tearing position range corresponding to the frame rates of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input moment of the vertical synchronization signal corresponding to the next frame of the input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range to change the frame rate of the output image displayed on the display screen. Therefore, the frame rate synchronization module adjusts the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range, so as to achieve continuous output of each frame of the image and synchronization of the input image and the output image under the premise of a single frame buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments and drawings obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0009] Figure 1 A schematic diagram of the input and output structure provided in an embodiment of the present application is shown.

[0010] Figure 2 A structural schematic diagram of another input image and output image provided in an embodiment of the present application is shown.

[0011] Figure 3 A schematic diagram of the structure of another input image and output image provided in an embodiment of the present application is shown.

[0012] Figure 4A schematic structural diagram of a chip provided in an embodiment of the present application is shown.

[0013] Figure 5 A structural schematic diagram of another input image and output image provided in an embodiment of the present application is shown.

[0014] Figure 6 A structural schematic diagram of another input image and output image provided in an embodiment of the present application is shown.

[0015] Figure 7 A structural schematic diagram of yet another input image and output image provided in an embodiment of the present application is shown.

[0016] Figure 8 A structural schematic diagram of yet another input image and output image provided in an embodiment of the present application is shown.

[0017] Fig. 9 A schematic diagram of the structure of yet another input image and output image provided in an embodiment of the present application is shown.

[0018] Fig.10 A schematic diagram of the structure of yet another input image and output image provided in an embodiment of the present application is shown.

[0019] Fig.11 A structural schematic diagram of yet another input image and output image provided in an embodiment of the present application is shown.

[0020] Fig.12 A structural schematic diagram of yet another input image and output image provided in an embodiment of the present application is shown.

[0021] Fig.13 A structural schematic diagram of yet another input image and output image provided in an embodiment of the present application is shown.

[0022] Fig.14 A schematic structural diagram of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0024] In the following description, reference is made to "some embodiments", which describes a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, reference is made to the term "multiple" to mean at least two.

[0025] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0027] When the Mobile Industry Processor Interface (MIPI) is in video mode, the hardware synchronization method is that the LCDC outputs a frame of output image under the trigger of the vertical synchronization signal. In other words, when the current LCDC output image frame is displayed, if the vertical synchronization signal has not been triggered, it will wait until the vertical synchronization signal is triggered before outputting the next frame of output image. However, this hardware synchronization method has the problem of discontinuous output image, which will cause the transmission channel (TX lane) to be pulled up, resulting in incompatibility of some display screens, resulting in display abnormalities.

[0028] For example, when the frame rate of the input image is 60 Hz and the frame rate of the output image is 60 Hz, there is a waiting time for the vertical synchronization signal to be triggered between the two output frames. Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of the structure of an input image and an output image provided by an embodiment of the present application. Figure 1 As shown, the blue line represents the input image, the green line represents the output image, and the red line between two frames of output images represents the time waiting for the vertical synchronization signal to be triggered, resulting in the problem of discontinuous output image.

[0029] For another example, when the frame rate of the input image is 90HZ and the frame rate of the output image is 60HZ, inputting three frames of input images will trigger the output of two frames of output images to ensure synchronization between the input image and the output image. Among them, the third frame of output image is triggered by the fourth frame of input image, and there will be a discontinuity between the second frame of output image and the third frame of output image. For details, please refer to Figure 2 , Figure 2 FIG. 2 shows another structural diagram of an input image and an output image provided by an embodiment of the present application. Figure 2 As shown, the red line represents the input image, the blue line represents the output image, and the time t1 is the time when the third frame output image waits for the fourth frame input image to be triggered.

[0030] Based on the above situation, in the related art, two frame buffers are set to store the input image to realize the conversion of any frame rate of the output image. For example, the frame rate of the input image is 120HZ, and the frame rate of the output image is 60HZ. For another example, the frame rate of the input image is 90HZ, and the frame rate of the output image is 60HZ. For another example, the frame rate of the input image is 60HZ, and the frame rate of the output image is 60HZ.

[0031] Specifically, assuming that the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz, please refer to Figure 3 , Figure 3 FIG. 2 shows another structural diagram of an input image and an output image provided by an embodiment of the present application. Figure 3 As shown, when the first frame input image 1 is input, the pointer of the video encoder (VIDC) points to the frame buffer FB2 to store the first frame input image 1 in the frame buffer FB2; when the second frame input image 2 is input, the pointer of the video encoder (VIDC) points to the frame buffer FB1 to store the second frame input image 2 in the frame buffer FB1. So that the frame buffer FB2 and the frame buffer FB1 store the input images alternately. When the second frame output image 2 is output, the pointer of the display controller (LCDC) points to the frame buffer FB1 to output the second frame input image 2 stored in the frame buffer FB1; when the third frame output image 3 is output, the pointer of the display controller points to the frame buffer FB2 to output the third frame input image 3 stored in the frame buffer FB2; when the fourth frame output image 4 is output, the pointer of the display controller points to the frame buffer FB2 to output the fifth frame input image 5 stored in the frame buffer FB2.

[0032] Although the above solution of setting two frame buffers to store input images to achieve arbitrary frame rate conversion of output images can ensure the continuity of output images and is compatible with different frame rates of input images and different display screens, it requires higher hardware costs and increases chip costs.

[0033] In order to improve the above-mentioned problems, the present application provides a chip and a display device, the chip including a receiving module, an image display module, a frame buffer and a frame rate synchronization module, the image receiving module, the frame buffer and the image display module are connected in sequence, and the image receiving module and the image display module are also respectively connected to the frame rate synchronization module, wherein: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal to store the input image in the frame buffer; the vertical synchronization signal is sent by a signal source to the image receiving module; the image display module is used to read the input image stored in the frame buffer to obtain an output image for displaying the output image on the display screen; the frame rate synchronization module is used to determine the tearing position range corresponding to the frame rates of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input moment of the vertical synchronization signal corresponding to the next frame of the input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the tearing position range to change the frame rate of the output image displayed on the display screen.

[0034] Therefore, the frame rate synchronization module adjusts the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range, so as to achieve continuous output of each frame of the image and synchronization of the input image and the output image under the premise of a single frame buffer.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0036] See also Figure 4 , Figure 4 FIG. 1 shows a schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 4 As shown, the chip 100 includes an image receiving module 110, an image display module 120, a frame buffer 130 and a frame rate synchronization module 140. The image receiving module 110, the frame buffer 130 and the image display module 120 are connected in sequence, and the image receiving module 110 and the image display module 120 are also connected to the frame rate synchronization module 140 respectively. Among them: The image receiving module 110 is used to send an input image to the frame buffer 130 under the triggering of a vertical synchronization signal, so as to store the input image in the frame buffer 130; wherein the vertical synchronization signal is sent by a signal source to the image receiving module 110. The image display module 120 is used to read the input image stored in the frame buffer 130 to obtain an output image, so as to display the output image on the display screen. The frame rate synchronization module 140 is used to determine the tearing position range corresponding to the frame rates of the input image and the output image. The frame rate synchronization module 140 is also used to determine the first reading position of the image display module 120 in the frame buffer 130 at the input moment of the vertical synchronization signal corresponding to the next frame of the input image. The frame rate synchronization module 140 is also used to adjust the speed at which the image display module 120 reads the input image stored in the frame buffer 130 according to the first reading position and the tearing position range, so as to change the frame rate of the output image displayed on the display screen.

[0037] The input image is image data sent by the signal source to the image receiving module 110. In some embodiments, the input image includes image information and vertical synchronization signal information. After the signal source sends the input image to the image receiving module 110, the image receiving module 110 reads the vertical synchronization signal information in the input image when parsing the input image, and sends the image information to the frame buffer 130. The image information may be pixels contained in a frame of the input image.

[0038] The image receiving module 110 may include a transmitting module of a Mobile Industry Processor Interface (‌MIPI), for example, a MIPI TX module.

[0039] The image display module 120 may include a MIPI receiving module, for example, a MIPI RX module.

[0040] In some embodiments, the image receiving module 110 also includes a first image processing module, which is used to reduce the received input image data to reduce the storage pressure of the frame buffer, and the image display module 120 also includes a second image processing module, which is used to enlarge the received output image to restore the image quality of the output image.

[0041] The frame buffer 130 (Frame Buffer, FB) can be used to store valid pixel data of an input image.

[0042] See also Figure 5 , Figure 5 FIG. 2 shows another structural diagram of an input image and an output image provided by an embodiment of the present application. Figure 5 As shown, Figure 5The horizontal axis in is time t, Figure 5 The ordinate in is the position d where the image display module reads the input image stored in the frame buffer. The green line is the output image 1, the blue line is the input image 2, and time a is the generation time of the vertical synchronization signal corresponding to the input image 2. Position A is the first reading position of the image display module 120 in the frame buffer 130 at time a.

[0043] See also Figure 5 and 6 , Figure 6 FIG. 2 shows a schematic diagram of the structure of another input image and output image provided by an embodiment of the present application. Figure 6 As shown, Figure 6 The horizontal axis in is time t, Figure 6 The vertical coordinate in is the position d where the image display module reads the input image stored in the frame buffer. The green line is the output image 1, the blue line is the input image 2, and the time a is the time when the vertical synchronization signal corresponding to the input image 2 is generated. Position A is the first reading position of the image display module 120 in the frame buffer 130 at the time a. Figure 5 Middle position A and Figure 6 The middle position A can be obtained to increase the output speed of output image 1. Figure 6 The middle position A is relative to Figure 5 The value of A in the middle position becomes larger.

[0044] See also Figure 6 and 7 , Figure 7 FIG. 2 shows another structural diagram of an input image and an output image provided by an embodiment of the present application. Figure 7 As shown, Figure 7 The horizontal axis in is time t, Figure 7 The vertical coordinate in is the position d where the image display module reads the input image stored in the frame buffer. The green line is the output image 1, the blue line is the input image 2, and the time a is the time when the vertical synchronization signal corresponding to the input image 2 is generated. Position A is the first reading position of the image display module 120 in the frame buffer 130 at the time a. Figure 5 Middle position A and Figure 7 The middle position A can be obtained, reducing the output speed of output image 1, Figure 6 The middle position A is relative to Figure 5 The value of A in the middle position becomes smaller.

[0045] It can be seen that the frame rate synchronization module 140 can ensure the continuity between each frame of output images by increasing or decreasing the output speed of the output image. However, if only the output speed of the output image is adjusted to ensure the continuity between each frame of the output image, the input image and the output image may be out of sync. That is, the speed at which the image display module 120 reads the input image stored in the frame buffer 130 is faster than the speed at which the image receiving module 110 writes the input image into the frame buffer 130, resulting in tearing on the display screen.

[0046] Based on the above situation, under the action of the vertical synchronization signal sent by the signal source, the image receiving module 110 starts to send a frame of input image to the frame buffer 130, and the frame buffer 130 starts to store the frame of input image sent by the image receiving module 110. The read pointer of the image display module 120 moves in the storage space of the frame buffer 130 to read the input image stored in the frame buffer 130, thereby obtaining an output image for displaying the output image on the display screen.

[0047] In this process, the frame rate synchronization module 140 determines whether the first read position is within the tearing position range based on the tearing position range and the first read position. When the frame rate synchronization module 140 determines that the first read position is within the tearing position range, it means that the progress of the image display module 120 reading the input image stored in the frame buffer 130 has caught up with the progress of the image receiving module 110 writing the input image into the frame buffer 130, which will cause the input image and the output image to be out of sync, that is, tearing will occur. At this time, the speed at which the image display module 120 reads the input image stored in the frame buffer 130 is adjusted by the frame rate synchronization module 140 to change the frame rate of the output image displayed on the display screen, so as to achieve the adjustment of the input image and the output image from an out-of-sync relationship to a synchronized relationship through the frame rate synchronization module 140, so that tearing will not occur.

[0048] When the frame rate synchronization module 140 determines that the first reading position is not within the tearing position range, it means that the progress of the image display module 120 reading the input image stored in the frame buffer 130 will not catch up with the progress of the image receiving module 110 writing the input image into the frame buffer 130, and the input image is in a synchronous relationship with the output image, that is, no tearing will occur.

[0049] Therefore, the frame rate synchronization module 140 adjusts the speed at which the image display module 120 reads the input image stored in the frame buffer 130 to ensure that each frame of the output image is continuous and the input image is synchronized with the output image, thereby avoiding tearing on the display screen. Compared with the prior art solution of using a double frame buffer 130, the present application uses a single frame buffer 130 solution to adjust the speed at which the image display module 120 reads the input image stored in the frame buffer 130 through the frame rate synchronization module 140. While ensuring that each frame of the output image is continuous, it also ensures that the input image is synchronized with the output image to avoid tearing on the display screen, which can effectively reduce the cost of the chip 100.

[0050] It is worth noting that in order to synchronize the input image and the output image of the chip 100, part of the input image sent by the signal source to the image receiving module 110 will be discarded under certain circumstances, and the discarded input image cannot be read and output to the display screen by the image display module 120. In other words, the image display module 120 does not read each frame of the input image written into the frame buffer 130 by the image receiving module 110.

[0051] The specific situation includes that the frame rate of the input image is greater than the frame rate of the output image.

[0052] The frame rate of the input image refers to the number of input images received in the image receiving module 1S. For example, if 60 input images are received in the image receiving module 1S, the frame rate is 60 Hz.

[0053] The frame rate of the output image refers to the number of images outputted in the image display module 1S. For example, if 60 input images are outputted in the image display module 1S, the frame rate is 60 Hz.

[0054] For example, when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz, the image receiving module 110 will send three frames of input images to the frame buffer 130 respectively under the triggering of three vertical synchronization signals, and the image display module 120 will only read the two frames of input images written into the frame buffer 130 by the image receiving module 110, thereby obtaining two frames of output images. In other words, when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz, one frame of input image will be discarded among the three frames of input image, thereby obtaining two frames of output image.

[0055] For another example, when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz, the image receiving module 110 will send two frames of input images to the frame buffer 130 respectively under the triggering of two vertical synchronization signals, and the image display module 120 will only read one frame of input image written to the frame buffer 130 by the image receiving module 110, thereby obtaining one frame of output image. In other words, when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz, one frame of input image will be discarded from the two frames of input image, thereby obtaining one frame of output image.

[0056] For another example, when the frame rate of the input image is 60 Hz and the frame rate of the output image is 60 Hz, the image display module 120 reads each frame of the input image written into the frame buffer 130 by the image receiving module 110. In other words, when the frame rate of the input image is 60 Hz and the frame rate of the output image is 60 Hz, each frame of the input image will not be discarded, and each frame of the input image has a corresponding output image.

[0057] Furthermore, in some embodiments, the frame rate synchronization module 140 is further used to determine a target input image to be discarded in multiple input images based on the frame rates of the input image and the output image. The frame rate synchronization module 140 is further used to determine a synchronization area corresponding to an output image corresponding to a previous input image of the first input image based on two input images adjacent to the first input image in the target input image. The frame rate synchronization module 140 is further used to determine a tearing position range based on the synchronization area and the generation time of a vertical synchronization signal corresponding to a next input image of the first input image.

[0058] The synchronization area is an area where the output image corresponding to the previous input image of the first input image can be output, that is, when the output image corresponding to the previous input image of the first input image is located in the synchronization area, there is no asynchronism between the previous input image of the first input image and the output image corresponding to the previous input image of the first input image. And when the output image corresponding to the previous input image of the first input image is located in the synchronization area, it can be ensured that each frame of the output image is in a continuous state.

[0059] In some embodiments, the frame rate synchronization module 140 is used to determine the limit position of the output image corresponding to the previous input image of the first input image in the frame buffer 130 read by the image display module 120 at the generation time of the vertical synchronization signal corresponding to the next input image of the first input image. The frame rate synchronization module 140 then determines the tearing position range according to the limit position. That is, when the first read position of the output image corresponding to the previous input image of the first input image is within the tearing position range, the input image and the output image are not synchronized at this time, and tearing will occur on the display screen.

[0060] In some implementations, the frame rate synchronization module 140 is specifically configured to determine a target input image among multiple frames of input images when the frame rate of the input image is greater than the frame rate of the output image.

[0061] For example, the frame rate synchronization module 140 is further specifically used to determine the second input image of every two input images in the multiple input images as the target input image when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz. For another example, the frame rate synchronization module is further specifically used to determine the second input image of every three input images in the multiple input images as the target input image when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz.

[0062] For example, when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz, one input image frame will be discarded for every three input image frames, thereby obtaining two output image frames. Figure 8 , Figure 8 FIG. 2 shows a schematic diagram of a structure of yet another input image and an output image provided by an embodiment of the present application. Figure 8 As shown, Figure 8 The horizontal axis in is time t, Figure 8 The ordinate in is the position d where the image display module reads the input image stored in the frame buffer. The blue line is the input image, the blue dotted line is the first frame input image 1 in the target input image to be discarded, and input image 2 and input image 3 are two frames of input images adjacent to the first frame input image 1. The frame rate synchronization module 140 determines the synchronization area A of the output image corresponding to input image 2 based on input image 2 and input image 3 (that is, synchronization area A is the green line area). Moment a is the generation moment of the vertical synchronization signal corresponding to the next frame input image 3 of the first frame input image 1. At moment a, the frame rate synchronization module 140 determines the limit position b of the output image corresponding to the previous frame input image 2 of the first frame input image 1 in the frame buffer 130 read by the image display module 120.

[0063] Please continue to refer to Figure 8 , when the position of the output image corresponding to the previous input image 2 of the first input image 1 in the frame buffer 130 read by the image display module 120 at time a is less than the limit position b, the output image corresponding to the previous input image 2 of the first input image 1 in the frame buffer 130 read by the image display module 120 will have an intersection with the next frame image of the first input image 1, and tearing will occur. Therefore, the tearing position range is [0, b].

[0064] For example, when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz, one input image frame will be discarded for every two input image frames, thereby obtaining one output image frame. Fig. 9 , Fig. 9 FIG. 2 shows a schematic diagram of a structure of another input image and an output image provided by an embodiment of the present application. Fig. 9 As shown, Fig. 9 The horizontal axis in is time t, Fig. 9 The ordinate in is the position d where the image display module reads the input image stored in the frame buffer. The blue line is the input image, the blue dotted line is the first frame input image 1 in the target input image to be discarded, and input image 2 and input image 3 are two frames of input images adjacent to the first frame input image 1. The frame rate synchronization module 140 determines the synchronization area A of the output image corresponding to input image 2 based on input image 2 and input image 3 (that is, synchronization area A is the green line area). Moment a is the generation moment of the vertical synchronization signal corresponding to the next frame input image 3 of the first frame input image 1. At moment a, the frame rate synchronization module 140 determines the limit position b of the output image corresponding to the previous frame input image 2 of the first frame input image 1 in the frame buffer 130 read by the image display module 120.

[0065] Please continue to refer to Fig. 9 , when the position of the output image corresponding to the previous input image 2 of the first input image 1 in the frame buffer 130 read by the image display module 120 at time a is less than the limit position b, the output image corresponding to the previous input image 2 of the first input image 1 in the frame buffer 130 read by the image display module 120 will have an intersection with the next frame image of the first input image 1, and tearing will occur. Therefore, the tearing position range is [0, b].

[0066] In a specific embodiment, the frame rate synchronization module 140 is specifically configured to, when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz, the tearing position range is [0, ]. Wherein, VTT is a second reading position after the image display module 120 has finished reading a frame of output image stored in the frame buffer 130 .

[0067] In another specific embodiment, the frame rate synchronization module 140 is specifically configured to, when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz, the tearing position range is [0, VTT].

[0068] After determining the tearing position range, the frame rate synchronization module 140 can adjust the speed at which the image display module 120 reads the input image stored in the frame buffer 130 according to whether the first reading position is within the tearing position range, so as to change the frame rate of the output image displayed on the display screen, thereby synchronizing the input image of the chip with the output image.

[0069] As can be seen from the above description, when the frame rate synchronization module 140 determines that the first reading position is within the tearing position range, the output image can be synchronized with the input image and each frame of the output image can be continuous by increasing or decreasing the speed at which the image display module reads the input image stored in the frame buffer. In order to further accelerate, the speed at which the image display module reads the input image stored in the frame buffer is adjusted so that the output image is quickly synchronized with the input image.

[0070] In some embodiments, the frame rate synchronization module 140 is also used to divide the tear position range into a first tear position sub-range and a second tear position sub-range; the frame rate synchronization module 140 is specifically used to increase the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the first tear position sub-range; the frame rate synchronization module 140 is specifically used to reduce the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the second tear position sub-range.

[0071] The frame rate synchronization module 140 divides the tear position range into a first tear position sub-range and a second tear position sub-range, and determines whether the first reading position is located in the first tear position sub-range or the second tear position sub-range, so as to quickly determine whether to increase the speed at which the image display module reads the input image stored in the frame buffer so as to synchronize the output image with the input image, or to reduce the speed at which the image display module reads the input image stored in the frame buffer so as to synchronize the output image with the input image. Thus, when the frame rate synchronization module 140 determines that the first reading position is located in the tear position range, it quickly adjusts the speed at which the image display module reads the input image stored in the frame buffer so as to achieve rapid synchronization between the output image and the input image, that is, the speed of the input image will not be caught up by the speed of the output image.

[0072] In a specific embodiment, the first tear position sub-range is [ , ], the second tear position sub-range [0, ].

[0073] In another specific embodiment, the first tear position sub-range is [ , ], the second tear position sub-range [0, ].

[0074] As can be seen from the above description, the frame rate synchronization module 140 quickly adjusts the speed at which the image display module reads the input image stored in the frame buffer by determining that the first reading position is located in the first tear position sub-range and the second tear position sub-range, so as to achieve rapid synchronization between the output image and the input image. When the frame rate of the input image is sent to switch, for example, the frame rate of multiple frames of input images is switched from 90HZ to 60Hz. For another example, the frame rate of multiple frames of input images is switched from 60HZ to 90Hz. In this case, it is possible that the output image is not synchronized with the input image, resulting in tearing on the display screen.

[0075] Based on the above situation, in some embodiments, the frame rate synchronization module 140 is also used to determine the target reading position corresponding to the current frame rate switch when the frame rate of the multiple-frame input images is switched from the first frame rate to the second frame rate; the frame rate synchronization module 140 is also used to determine the first frame input image with a frame rate of the second frame rate in the multiple-frame input images as the reference input image; the frame rate synchronization module 140 is also used to adjust the speed at which the image display module reads the output image corresponding to the second frame input image with a frame rate of the second frame rate in the multiple-frame input images when the target reading position is not equal to the reference reading position.

[0076] The reference reading position is the reading position of the output image corresponding to the previous input image in the multiple input images, where the image display module 120 reads the reference input image stored in the frame buffer 130 at the time when the vertical synchronization signal corresponding to the reference input image is generated.

[0077] For example, the frame rate of multiple input images is switched from 90 Hz to 60 Hz. Fig.10 , Fig.10 FIG. 2 shows a schematic diagram of a structure of another input image and an output image provided by an embodiment of the present application. Fig.10 As shown, Fig.10 The horizontal axis of 10a and 10b is time t. Fig.10 The vertical coordinates of 10a and 10b in FIG. 10a and 10b are the positions d where the image display module reads the input image stored in the frame buffer. The blue lines in 10a and 10b are the input images, and the green lines in 10a and 10b are the output images. Fig.10As shown in a, at time a, the frame rate is switched from 90Hz to 60Hz, and the input image is synchronized with the output image, that is, the display screen will not be torn, but after the switch, the target reading position is not equal to the reference reading position. In order to make the target reading position equal to the reference reading position, the speed of the image display module reading the output image corresponding to the second frame input image with a frame rate of the second frame rate in the multiple frames of input images is adjusted to make the target reading position equal to the reference reading position. At time c, the relationship between the output image and the input image is adjusted to make the target reading position equal to the reference reading position.

[0078] like Fig.10 As shown in b, when the frame rate is switched from 90 Hz to 60 Hz, the input image is synchronized with the output image, and the target reading position is equal to the reference reading position after the switching, that is, there is no need to adjust the speed at which the image display module reads the output image corresponding to the second frame input image with a frame rate of the second frame rate among multiple frames of input images.

[0079] For example, the frame rate of multiple input images is switched from 60 Hz to 90 Hz. Fig.11 , Fig.11 FIG. 2 shows another structural diagram of an input image and an output image provided by an embodiment of the present application. Fig.11 As shown, Fig.11 The horizontal coordinates of 11a, 11b and 11c in the figure are time t. Fig.11 The vertical coordinates of 11a, 11b and 11c in FIG. 1 are the positions d where the image display module reads the input image stored in the frame buffer. The blue lines in 11a, 11b and 11c are the input images, and the green lines in 11a, 11b and 11c are the output images. Fig.11 As shown in FIG. 1 , at time a, the frame rate is switched from 60 Hz to 90 Hz, and the input image is synchronized with the output image, that is, the display screen will not be torn. The frame rate synchronization module 140 reduces the speed at which the image display module 120 reads the image data stored in the frame buffer 130, so that at time c, the relationship between the output image and the input image is adjusted to the target reading position being equal to the reference reading position.

[0080] like Fig.11 As shown in FIG. 2 , at time a, the frame rate is switched from 60 Hz to 90 Hz, and tearing occurs during the synchronization between the input image and the output image. The frame rate synchronization module 140 increases the speed at which the image display module 120 reads the image data stored in the frame buffer 130, so that at time c, the relationship between the output image and the input image is adjusted to be equal to the target reading position and the reference reading position. This synchronizes the input image with the output image.

[0081] like Fig.11As shown in FIG. 3 , at time a, the frame rate is switched from 60 Hz to 90 Hz. After the frame rate is switched, the relationship between the output image and the input image is that the target reading position is equal to the reference reading position. Therefore, there is no need to adjust the relationship between the output image and the input image.

[0082] For example, the frame rate of multiple input images is switched from 60 Hz to 90 Hz. Fig.12 , Fig.12 FIG. 2 shows a schematic diagram of a structure of yet another input image and an output image provided by an embodiment of the present application. Fig.12 As shown, Fig.12 The horizontal axis of 12a and 12b is time t. Fig.12 The vertical coordinates of 12a and 12b in 12a are the position d where the image display module reads the input image stored in the frame buffer. The blue lines in 12a and 12b are the input images, and the green lines in 12a and 12b are the output images. At time a, the frame rate is switched from 120Hz to 60Hz, and the input image is synchronized with the output image, that is, the display screen will not be torn. By reducing the speed at which the image display module 120 reads the image data stored in the frame buffer 130, at time c, the relationship between the output image and the input image is adjusted to be equal to the target reading position and the reference reading position. So that the input image is synchronized with the output image.

[0083] like Fig.12 As shown in b, at time a, the frame rate is switched from 120 Hz to 60 Hz, and the relationship between the input image and the output image has been adjusted to the target reading position being equal to the reference reading position, so there is no need to adjust the relationship between the output image and the input image.

[0084] For example, the frame rate of multiple input images is switched from 60 Hz to 120 Hz. Fig.13 , Fig.13 FIG. 2 shows a schematic diagram of a structure of another input image and an output image provided by an embodiment of the present application. Fig.13 As shown, Fig.13 The horizontal axis of 13a and 13b is time t. Fig.13 The vertical coordinates of 13a and 13b in 13a and 13b are the position d where the image display module reads the input image stored in the frame buffer. The blue lines in 13a and 13b are the input images, and the green lines in 13a and 13b are the output images. At time a, the frame rate is switched from 60Hz to 120Hz, and the input image is synchronized with the output image, that is, there is no tearing on the display screen. By reducing the speed at which the image display module 120 reads the image data stored in the frame buffer 130, at time c, the relationship between the output image and the input image is adjusted to be equal to the target reading position and the reference reading position. So that the input image is synchronized with the output image.

[0085] like Fig.13 As shown in b, at time a, the frame rate is switched from 60 Hz to 120 Hz, and the relationship between the input image and the output image has been adjusted to the target reading position being equal to the reference reading position, so there is no need to adjust the relationship between the output image and the input image.

[0086] In a specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 90 Hz to 60 Hz. VTT; wherein VTT is the second position where the image display module reads a frame of output image.

[0087] In another specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 60 Hz to 90 Hz. VTT; wherein VTT is the second position where the image display module reads a frame of output image.

[0088] In another specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 120 Hz to 60 Hz. VTT; wherein VTT is the second position where the image display module reads a frame of output image.

[0089] In another specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 60 Hz to 120 Hz. VTT; wherein VTT is the second position where the image display module reads a frame of output image.

[0090] See also Fig.14 , Fig.14 The structure diagram of a display device provided by an embodiment of the present application is shown. The display device 200 includes: the above chip 100 and a display screen 210. Specifically: The chip 100 is used to send an output image to the display screen 210, and the display screen 210 is used to display the output image.

[0091] In some embodiments, a signal source 220 is further included, and the signal source 220 is used to send an input image to the chip 100 .

[0092] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the chip 100, the display screen 210 and the signal source 220 described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0093] The technical solution provided by the present application, the chip includes: an image receiving module, an image display module, a frame buffer and a frame rate synchronization module, the image receiving module, the frame buffer and the image display module are connected in sequence, and the image receiving module and the image display module are also respectively connected to the frame rate synchronization module, wherein: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal to store the input image in the frame buffer; the vertical synchronization signal is sent by a signal source to the image receiving module; the image display module is used to read the input image stored in the frame buffer to obtain an output image for displaying the output image on the display screen; the frame rate synchronization module is used to determine the tearing position range corresponding to the frame rates of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input moment of the vertical synchronization signal corresponding to the next frame of the input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range to change the frame rate of the output image displayed on the display screen. Therefore, the frame rate synchronization module adjusts the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range, so as to achieve continuous output of each frame of the image and synchronization of the input image and the output image under the premise of a single frame buffer.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized in that: It includes an image receiving module, an image display module, a frame buffer and a frame rate synchronization module, wherein the image receiving module, the frame buffer and the image display module are connected in sequence, and the image receiving module and the image display module are also connected to the frame rate synchronization module respectively, wherein: The image receiving module is used to send the input image to the frame buffer under the triggering of the vertical synchronization signal, so as to store the input image in the frame buffer; the vertical synchronization signal is sent by the signal source to the image receiving module; The image display module is used to read the input image stored in the frame buffer to obtain an output image, so that the display screen can display the output image; The frame rate synchronization module is used to determine the tearing position range corresponding to the frame rates of the input image and the output image; The frame rate synchronization module is further used to determine the first reading position of the image display module in the frame buffer at the input time of the vertical synchronization signal corresponding to the next frame input image; The frame rate synchronization module is further used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tearing position range, so as to change the frame rate at which the display screen displays the output image.

2. The chip according to claim 1, characterized in that: The frame rate synchronization module is further used to determine a target input image to be discarded among multiple frames of input images according to the frame rates of the input image and the output image; The frame rate synchronization module is further used to determine a synchronization area corresponding to an output image corresponding to a previous input image of the first input image based on two input images adjacent to the first input image in the target input image; The frame rate synchronization module is further used to determine the tearing position range according to the synchronization area and the generation time of the vertical synchronization signal corresponding to the next frame input image of the first frame input image.

3. The chip according to claim 2, characterized in that: The frame rate synchronization module is specifically used to determine the target input image in the multiple frames of input images when the frame rate of the input image is greater than the frame rate of the output image.

4. The chip according to claim 3, characterized in that: The frame rate synchronization module is further specifically configured to determine the second input image of every two input images in the multiple input images as the target input image when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz; Alternatively, the frame rate synchronization module is further specifically used to determine the second input image of every three input images in the multiple input images as the target input image when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz.

5. The chip according to claim 1, characterized in that: The frame rate synchronization module is further used to divide the tearing position range into a first tearing position sub-range and a second tearing position sub-range; The frame rate synchronization module is specifically configured to increase the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the first tearing position sub-range; The frame rate synchronization module is specifically configured to reduce the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the second tearing position sub-range.

6. The chip according to claim 5, characterized in that: The frame rate synchronization module is specifically used for when the frame rate of the input image is 120 Hz and the frame rate of the output image is 60 Hz, the tearing position range is [0, ]; Alternatively, the frame rate synchronization module is specifically configured to, when the frame rate of the input image is 90 Hz and the frame rate of the output image is 60 Hz, the tearing position range is [0, VTT], wherein VTT is a second reading position after the image display module has finished reading a frame of the output image stored in the frame buffer.

7. The chip according to claim 6, characterized in that: The first tear position sub-range is [ , ], the second tear position sub-range [0, ]; Alternatively, the first tear position sub-range is [ , ], the second tear position sub-range [0, ].

8. The chip according to claim 1, characterized in that: The frame rate synchronization module is further used to determine a target reading position corresponding to the current frame rate switching when the frame rate of the multiple frames of input images is switched from the first frame rate to the second frame rate; The frame rate synchronization module is further used to determine a first frame of input image with a frame rate of the second frame rate among the multiple frames of input images as a reference input image; The frame rate synchronization module is further configured to adjust, when the target reading position is not equal to the reference reading position, a speed at which the image display module reads an output image corresponding to a second input image with a frame rate of the second frame rate among the multiple input image frames; Among them, the reference reading position is the reading position of the output image corresponding to the previous input frame of the reference input image in the multiple input images stored in the frame buffer when the vertical synchronization signal corresponding to the reference input image is generated.

9. The chip according to claim 8, characterized in that: The frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 90 Hz to 60 Hz. VTT; Alternatively, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 60 Hz to 90 Hz. VTT; Alternatively, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 120 Hz to 60 Hz. VTT; Alternatively, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multiple frames of input images is switched from 60 Hz to 120 Hz. VTT; Wherein, VTT is the second position where the image display module finishes reading a frame of the output image.

10. A display device, characterized in that: It comprises the chip and display screen as described in any one of claims 1 to 9, wherein the chip is used to send an output image to the display screen, and the display screen is used to display the output image.

11. The chip according to claim 10, characterized in that: Also included is a signal source, which is used to send an input image to the chip.

Images