Semiconductor device including charge holding node

Abstract

The invention relates to a semiconductor device including a charge holding node. The semiconductor device may include a first transistor and a second transistor on a substrate. The first transistor may include: a first source / drain region and a second source / drain region; a first channel region between the first source / drain region and the second source / drain region; the first gate electrode is located on the first channel region; and a charge holding node between the first channel region and the first gate electrode. The second transistor may include a third source / drain region and a fourth source / drain region, a portion of the third source / drain region being connected to the charge holding node; a second channel region between the third source / drain region and the fourth source / drain region; and a second gate electrode on the second channel region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0118766 filed in the Korean Intellectual Property Office on September 7, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor device including a charge retaining node and a method of forming the same. Background Art

[0004] As electronic systems tend toward high performance, memory devices that operate at high speeds must be developed. Memory devices using floating gates or charge trap layers show limitations in increasing the operating speed. Research is underway to improve the operating speed of memory devices by combining multiple transistors. The technology of realizing highly integrated memory devices by combining multiple transistors faces various problems, such as crosstalk. Summary of the invention

[0005] Various embodiments are directed to providing a semiconductor device and a method of forming the same which improves operation speed and facilitates high integration.

[0006] In an embodiment, a semiconductor device may include a first transistor and a second transistor disposed on a substrate. The first transistor may include: a first source / drain region and a second source / drain region; a first channel region located between the first source / drain region and the second source / drain region; a first gate electrode located above the first channel region; and a charge holding node located between the first channel region and the first gate electrode. The second transistor may include: a third source / drain region and a fourth source / drain region, a portion of the third source / drain region being connected to the charge holding node; a second channel region located between the third source / drain region and the fourth source / drain region; and a second gate electrode located above the second channel region.

[0007] In an embodiment, a semiconductor device may include a read word line extending in a row direction. A write word line is spaced apart from the read word line in a column direction. A plurality of write bit lines intersecting the read word line and the write word line and spaced apart from each other may be provided. A plurality of read bit lines intersecting the read word line and the write word line and spaced apart from each other may be provided. A plurality of memory cells adjacent to the plurality of write bit lines and the intersection points of the plurality of read bit lines with the read word line and the write word line may be provided. Each of the plurality of memory cells may include a read transistor and a write transistor. The read transistor may include: a first gate electrode above a channel region; and a charge retention node located between the channel region and the first gate electrode. The write transistor may include: a source / drain region connected to the charge retention node; and a second gate electrode connected to the first gate electrode.

[0008] In an embodiment, a semiconductor device may include a first read word line and a second read word line spaced apart from each other in a column direction. Each of the first read word line and the second read word line may extend in a row direction. A first write word line and a second write word line may be spaced apart from each other in a column direction. Each of the first write word line and the second write word line may extend in a row direction. A first write bit line intersecting the first read word line and the second read word line and the first write word line and the second write word line may be provided. A first read bit line intersecting the first read word line and the second read word line and the first write word line and the second write word line may be provided. A first storage unit adjacent to the first write bit line and an intersection point where the first read bit line intersects the first read word line and the first write word line may be provided. A fourth storage unit adjacent to the first write bit line and an intersection point where the first read bit line intersects the second read word line and the second write word line may be provided. The first storage unit may include a first read transistor and a first write transistor. The fourth storage unit may include a fourth read transistor and a fourth write transistor. The first read transistor may include: a first source / drain region and a second source / drain region; a first channel region located between the first source / drain region and the second source / drain region; a first gate electrode located above the first channel region; and a charge holding node located between the first channel region and the first gate electrode. The first source / drain region of the first read transistor may contact the third channel region of the fourth read transistor. The first write transistor may include: a third source / drain region and a fourth source / drain region, the third source / drain region being connected to the charge holding node; a second channel region located between the third source / drain region and the fourth source / drain region; and a second gate electrode located above the second channel region.

[0009] According to an embodiment of the disclosed technology, a memory cell including a read transistor and a write transistor may be provided. The read transistor may include a charge retention node between a channel region and a first gate electrode. The source / drain region of the write transistor may be connected to the charge retention node. The second gate electrode of the write transistor may be connected to the first gate electrode of the read transistor. The first gate electrode and the second gate electrode may be connected to a write word line. The disclosed embodiments minimize crosstalk and increase operating speed, so that a semiconductor device that is conducive to high integration can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4 It is shown Figure 3 Layout diagram of some of the components shown in .

[0014] Figures 5 to 11 It is shown Figure 1 A partial view of a part.

[0015] Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 and Fig. 22 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0016] Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figures 24 to 31 is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure, Figure 2 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present disclosure, Figure 3 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure, Figure 4 It is shown Figure 3 The layout of some components shown in Figures 5 to 11 It is shown Figure 1 A partial view of a part. Figure 1 You can refer to Figure 3 In an embodiment, a semiconductor device according to an embodiment of the present disclosure may include a 2-transistor 0-capacitor (2T0C) memory.

[0019] Reference Figure 1The semiconductor device may include a substrate 21, a first well 23, a first active region 25, a second active region 26, an isolation layer 27, a channel dielectric layer 31, a charge holding node 33, a first gate dielectric layer 35, a first gate electrode 37, a first capping pattern 38, a first gate spacer 39, a second gate dielectric layer 42, a second gate electrode 44, a second capping pattern 45, a second gate spacer 48, a first source / drain region 51, a second source / drain region 5 ... A channel region 55, a third source / drain region 61, a fourth source / drain region 63, a second channel region 66, a first interlayer insulating layer 72, an interconnect 73, a contact covering pattern 79, a second interlayer insulating layer 82, a first contact plug 83, a second contact plug 84, a third contact plug 85, a fourth contact plug 86, a fifth contact plug 87, a first read word line RWL1, a first read bit line RBL1, a first write word line WWL1 and a first write bit line WBL1.

[0020] The channel dielectric layer 31, the charge holding node 33, the first gate dielectric layer 35, the first gate electrode 37, the first source / drain region 51, the second source / drain region 53, and the first channel region 55 may configure a first read transistor RTr1. The second gate dielectric layer 42, the second gate electrode 44, the third source / drain region 61, the fourth source / drain region 63, and the second channel region 66 may configure a first write transistor WTTr1. In an embodiment, the first read transistor RTr1 may correspond to a first transistor disposed on the substrate 21, and the first write transistor WTTr1 may correspond to a second transistor disposed on the substrate 21.

[0021] The first well 23 may include impurities of a conductivity type different from that of the impurities in the substrate 21. In an embodiment, the substrate 21 may include P-type impurities, and the first well 23 may include N-type impurities. The first active region 25 may be defined by the isolation layer 27 in the substrate 21. The second active region 26 may be defined by the isolation layer 27 in the first well 23.

[0022] The first source / drain region 51 and the second source / drain region 53 may be disposed in the first active region 25. The first channel region 55 may be defined between the first source / drain region 51 and the second source / drain region 53 in the first active region 25. In an embodiment, the first channel region 55 may include P-type impurities, and the first source / drain region 51 and the second source / drain region 53 may include N-type impurities.

[0023] The third source / drain region 61 and the fourth source / drain region 63 may be disposed in the second active region 26. A second channel region 66 may be defined between the third source / drain region 61 and the fourth source / drain region 63 in the second active region 26. The second channel region 66 may include impurities having a conductivity type different from that of the impurities in the first channel region 55. In an embodiment, the second channel region 66 may include N-type impurities, and the third source / drain region 61 and the fourth source / drain region 63 may include P-type impurities.

[0024] The channel dielectric layer 31, the charge holding node 33, the first gate dielectric layer 35, the first gate electrode 37, and the first capping pattern 38 may be sequentially stacked on the first channel region 55. The charge holding node 33 may span the first active region 25 and may extend onto the isolation layer 27. The channel dielectric layer 31 may be interposed between the first channel region 55 and the charge holding node 33 and between the isolation layer 27 and the charge holding node 33. The first gate spacer 39 may be disposed on the side surfaces of the first capping pattern 38, the first gate electrode 37, the first gate dielectric layer 35, the charge holding node 33, and the channel dielectric layer 31.

[0025] The second gate dielectric layer 42, the second gate electrode 44, and the second capping pattern 45 may be sequentially stacked on the second channel region 66. The second gate spacer 48 may be disposed on side surfaces of the second capping pattern 45, the second gate electrode 44, and the second gate dielectric layer 42.

[0026] A first interlayer insulating layer 72 covering the first read transistor RTrl and the first write transistor WTrl may be disposed on the substrate 21. An interconnect 73 contacting the upper surface and the side surface of the charge holding node 33 and contacting the third source / drain region 61 may be disposed in the first interlayer insulating layer 72. A contact covering pattern 79 covering the interconnect 73 may be disposed in the first interlayer insulating layer 72. A portion of the third source / drain region 61 may be connected to the charge holding node 33 through the interconnect 73.

[0027] The first contact plug 83 may be disposed to contact the first source / drain region 51 by passing through the first interlayer insulating layer 72, and the second contact plug 84 may be disposed to contact the fourth source / drain region 63 by passing through the first interlayer insulating layer 72. The first read bit line RBL1 and the first write bit line WBL1 may be formed on the first interlayer insulating layer 72. The first read bit line RBL1 may contact the first contact plug 83. The first read bit line RBL1 may be connected to the first source / drain region 51 through the first contact plug 83. The first write bit line WBL1 may contact the second contact plug 84. The first write bit line WBL1 may be connected to the fourth source / drain region 63 through the second contact plug 84.

[0028] A second interlayer insulating layer 82 covering the first read bit line RBL1 and the first write bit line WBL1 may be disposed on the first interlayer insulating layer 72. A third contact plug 85 may be disposed to contact the second source / drain region 53 by passing through the second interlayer insulating layer 82 and the first interlayer insulating layer 72. A fourth contact plug 86 may be disposed to contact the first gate electrode 37 by passing through the second interlayer insulating layer 82, the first interlayer insulating layer 72, and the first capping pattern 38. A fifth contact plug 87 may be disposed to contact the second gate electrode 44 by passing through the second interlayer insulating layer 82, the first interlayer insulating layer 72, and the second capping pattern 45. A first read word line RWL1 may be disposed on the second interlayer insulating layer 82 to contact the third contact plug 85. The first read word line RWL1 may be connected to the second source / drain region 53 through the third contact plug 85.

[0029] The first write word line WWL1 may be disposed on the second interlayer insulating layer 82 to contact the fourth and fifth contact plugs 86 and 87. The first write word line WWL1 may be connected to the first and second gate electrodes 37 and 44 through the fourth and fifth contact plugs 86 and 87, respectively.

[0030] In an embodiment, each of the first read transistor RTrl and the first write transistor WTrl may include a planar transistor, a recessed channel transistor, a vertical transistor, a fin field effect transistor (finFET), a gate-all-around (GAA) transistor, a multi-bridge channel transistor, or a combination thereof.

[0031] Reference Figure 2 , a first read word line RWL1 and a first write word line WWL1 spaced apart from each other may be provided. Each of the first read word line RWL1 and the first write word line WWL1 may extend in a row direction. The first write word line WWL1 may be arranged in a column direction from the first read word line RWL1. The first write word line WWL1 may be aligned parallel to the first read word line RWL1. The first write bit line WBL1 and the first read bit line RBL1 may be spaced apart from each other. Each of the first write bit line WBL1 and the first read bit line RBL1 may extend in a column direction. The first read bit line RBL1 may be arranged in a row direction from the first write bit line WBL1. The first read bit line RBL1 may be aligned parallel to the first write bit line WBL1. Each of the first write bit line WBL1 and the first read bit line RBL1 may intersect the first read word line RWL1 and the first write word line WWL1.

[0032] The first memory cell MC1 may be disposed adjacent to an intersection of the first write bit line WBL1 and the first read bit line RBL1 and the first read word line RWL1 and the first write word line WWL1. The first memory cell MC1 may include a first read transistor RTr1 and a first write transistor WTTr1. In an embodiment, the first read transistor RTr1 may be an NMOS transistor, and the first write transistor WTTr1 may be a PMOS transistor.

[0033] Gate electrodes of the first read transistor RTr1 and the first write transistor WTr1 may be connected to the first write word line WWL1. One of the source and the drain of the first read transistor RTr1 may be connected to the first read word line RWL1, and the other of the source and the drain of the first read transistor RTr1 may be connected to the first read bit line RBL1.

[0034] The first read transistor RTr1 may include a charge holding node 33 disposed between a gate electrode and a channel region. One of a source and a drain of the first write transistor WTr1 may be connected to the charge holding node 33, and the other of the source and the drain of the first write transistor WTr1 may be connected to the first write bit line WBL1.

[0035] In an embodiment, the first read transistor RTr1 may be a PMOS transistor, and the first write transistor WTr1 may be an NMOS transistor.

[0036] Reference Figure 3 , the first write word line WWL1 may be arranged in parallel in the column direction of the first read word line RWL1. The first read bit line RBL1 may be arranged in parallel in the row direction of the first write bit line WBL1. Each of the first write bit line WBL1 and the first read bit line RBL1 may intersect the first read word line RWL1 and the first write word line WWL1.

[0037] The first channel region 55 may be disposed between the first source / drain region 51 and the second source / drain region 53. The charge holding node 33 may be disposed on the first channel region 55. The first gate electrode 37 may be disposed on the charge holding node 33, and the charge holding node 33 is disposed on the first channel region 55. The first source / drain region 51 may be connected to the first read bit line RBL1. The second source / drain region 53 may be connected to the first read word line RWL1.

[0038] The second channel region 66 may be disposed between the third source / drain region 61 and the fourth source / drain region 63. The second gate electrode 44 may be disposed on the second channel region 66. The fourth source / drain region 63 may be connected to the first write bit line WBL1. The first gate electrode 37 and the second gate electrode 44 may be connected to the first write word line WWL1. The charge holding node 33 may be connected to the third source / drain region 61 through an interconnect 73.

[0039] Figure 4 Shows Figure 3 The charge holding node 33, the first gate electrode 37, the first source / drain region 51, the second source / drain region 53, the first channel region 55, the second gate electrode 44, the third source / drain region 61, the fourth source / drain region 63, the second channel region 66, and the interconnect 73 cited in the figure. The charge holding node 33 can be connected to the third source / drain region 61 through the interconnect 73.

[0040] Reference Figures 1 to 3 , the writing or programming operation of the first memory cell MC1 may include: applying 1V or 0V to the first write bit line WBL1 and applying -2V to the first write word line WWL1 to charge the charge holding node 33 to 1V or 0V; and applying 0V to the first write word line WWL1.

[0041] The read operation of the first memory cell MC1 may include applying 0V to the first read word line RWL1, applying 0.5V to the first read bit line RBL1, applying 0V to the first write bit line WBL1, and applying 1V to the first write word line WWL1. In the read operation of the first memory cell MC1, the turning on or off of the first read transistor RTr1 may be determined according to whether the charge state of the charge holding node 33 is 1V or 0V.

[0042] The standby operation of the first memory cell MC1 may include applying 0V to the first write word line WWL1 to maintain both the first read transistor RTr1 and the first write transistor WTr1 in a turned-off state.

[0043] Reference Figure 5 , the interconnect 73 may include a barrier layer 73B and a conductive layer 73C. The conductive layer 73C may be formed on the barrier layer 73B. The barrier layer 73B may contact the third source / drain region 61. In an embodiment, the barrier layer 73B may include Ti, TiN, Ta, TaN, or a combination thereof. The conductive layer 73C may include W, WN, Al, Cu, Co, Ru, Pt, Ag, Au, Zr, Mn, Sn, Ni, Ti, TiN, Ta, TaN, or a combination thereof.

[0044] Reference Figure 6 , a metal silicide layer 75 may be formed between the interconnection 73 and the third source / drain region 61. In an embodiment, the metal silicide layer 75 may include TiSi, TaSi, CoSi, NiSi, or a combination thereof.

[0045] Reference Figure 7, a Schottky barrier layer 77 may be formed between the interconnect 73 and the third source / drain region 61. In an embodiment, the third source / drain region 61 may include a semiconductor layer such as single crystal silicon having a first concentration of P-type impurities. The Schottky barrier layer 77 may include a semiconductor layer such as single crystal silicon having a second concentration of P-type impurities, the second concentration being lower than the concentration of the P-type impurities in the third source / drain region 61. The interconnect 73 may include a metal that forms a Schottky bond with the Schottky barrier layer 77. The interconnect 73 may include TiN, W, Al, or a combination thereof.

[0046] Reference Figure 8 , both the metal silicide layer 75 and the Schottky barrier layer 77 may be formed between the interconnection 73 and the third source / drain region 61. The barrier layer 73B may contact the upper surface and the side surface of the charge holding node 33.

[0047] Reference Fig. 9 , the equivalent oxide thickness (EOT) of the channel dielectric layer 31 may be substantially the same as the equivalent oxide thickness (EOT) of the first gate dielectric layer 35. The equivalent oxide thickness (EOT) of each of the channel dielectric layer 31 and the first gate dielectric layer 35 may be minimized within the limit of thickness capable of preventing leakage current.

[0048] Reference Fig.10 , the equivalent oxide thickness (EOT) of the first gate dielectric layer 35 may be greater than the equivalent oxide thickness (EOT) of the channel dielectric layer 31. For example, the equivalent oxide thickness (EOT) of the first gate dielectric layer 35 may be 1 to 2 times the equivalent oxide thickness (EOT) of the channel dielectric layer 31.

[0049] Reference Fig.11 , the equivalent oxide thickness (EOT) of the channel dielectric layer 31 may be greater than the equivalent oxide thickness (EOT) of the first gate dielectric layer 35. For example, the equivalent oxide thickness (EOT) of the channel dielectric layer 31 may be 1 to 2 times the equivalent oxide thickness (EOT) of the first gate dielectric layer 35.

[0050] Reference Figures 9 to 11 In an embodiment, the equivalent oxide thickness (EOT) of the first gate dielectric layer 35 may be 0.5 to 2 times the equivalent oxide thickness (EOT) of the channel dielectric layer 31 .

[0051] Fig.12 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure, Fig.13 is corresponding to Fig.12 Layout diagram of the .

[0052] Reference Fig.12 and Fig.13 , the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2 may be disposed to be spaced apart from each other. Each of the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2 may extend in the row direction. In an embodiment, the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2 may be aligned in parallel with each other and arranged sequentially in the column direction.

[0053] The first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 may be disposed to be spaced apart from each other. Each of the first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 may extend in the column direction. In an embodiment, the first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 may be aligned in parallel with each other and arranged to be spaced apart from each other in the row direction.

[0054] Each of the first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 may intersect the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2. The first to sixth memory cells MC1 to MC6 may be disposed adjacent to intersections of the first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 with the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2.

[0055] The first to sixth memory cells MC1 to MC6 may include first to sixth read transistors RTr1 to RTr6 and first to sixth write transistors WTTr1 to WTTr6, respectively. Figures 1 to 11 For example, the first memory cell MC1 may include a first read transistor RTr1 and a first write transistor WTTr1. Each of the second to sixth memory cells MC2 to MC6 may include the same configuration as described above with reference to FIG. Figures 1 to 11 The first memory cell MC1 is similarly configured as described.

[0056] Fig.14is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure, Fig.15 is with Fig.14 The corresponding layout diagram.

[0057] Reference Fig.14 and Fig.15 In an embodiment, the first write bit line WBL1, the first read bit line RBL1, the second read bit line RBL2, the second write bit line WBL2, the third write bit line WBL3, and the third read bit line RBL3 may be sequentially arranged and aligned in parallel with each other in a row direction. Each of the first write bit line WBL1, the first read bit line RBL1, the second read bit line RBL2, the second write bit line WBL2, the third write bit line WBL3, and the third read bit line RBL3 may intersect the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2.

[0058] The first to sixth memory cells MC1 to MC6 may be disposed adjacent to intersections of the first write bit line WBL1, the first read bit line RBL1, the second read bit line RBL2, the second write bit line WBL2, the third write bit line WBL3, and the third read bit line RBL3 with the first read word line RWL1, the first write word line WWL1, the second read word line RWL2, and the second write word line WWL2. The first to sixth memory cells MC1 to MC6 may include first to sixth read transistors RTr1 to RTr6 and first to sixth write transistors WTTr1 to WTTr6, respectively. The first memory cell MC1 may include the same as the above reference Figures 1 to 11 The configuration described above is similar to the configuration described above. The first storage cell MC1 to the third storage cell MC3 can be arranged sequentially in the row direction and aligned in the column direction. The fourth storage cell MC4 to the sixth storage cell MC6 can be respectively arranged in the column direction of the first storage cell MC1 to the third storage cell MC3. The fourth storage cell MC4 to the sixth storage cell MC6 can be arranged sequentially in the row direction and aligned in the column direction.

[0059] The second read transistor RTr2 of the second memory cell MC2 may be disposed adjacent to the first read transistor RTr1 of the first memory cell MC1. The second write transistor WTTr2 of the second memory cell MC2 may be disposed adjacent to the third write transistor WTTr3 of the third memory cell MC3. The fifth read transistor RTr5 of the fifth memory cell MC5 may be disposed adjacent to the fourth read transistor RTr4 of the fourth memory cell MC4. The fifth write transistor WTTr5 of the fifth memory cell MC5 may be disposed adjacent to the sixth write transistor WTTr6 of the sixth memory cell MC6.

[0060] Fourth and fifth read transistors RTr4 and RTr5 may be disposed in the column direction of first and second read transistors RTr1 and RTr2, respectively. Fifth and sixth write transistors WTTr5 and WTtr6 may be disposed in the column direction of second and third write transistors WTtr2 and WTtr3, respectively.

[0061] The first read transistor RTrl, the second read transistor RTr2, the fourth read transistor RTr4, and the fifth read transistor RTr5 can be arranged in the first conductive type region 125. The second write transistor WTTr2, the third write transistor WTTr3, the fifth write transistor WTTr5, and the sixth write transistor WTTr6 can be arranged in the second conductive type region 126. The second conductive type region 126 can be arranged adjacent to the first conductive type region 125 in the row direction. A plurality of first conductive type regions 125 and a plurality of second conductive type regions 126 can be arranged alternately and repeatedly in the row direction. In an embodiment, the first conductive type region 125 may include an NMOS transistor, and the second conductive type region 126 may include a PMOS transistor.

[0062] Fig.16 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure, Fig.17 is corresponding to Fig.16 Layout diagram of the .

[0063] Reference Fig.16 and Fig.17 In an embodiment, the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, and the second read word line RWL2 may be sequentially arranged in the column direction and aligned in parallel with each other while extending in the row direction. The first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 may be sequentially arranged in the row direction and aligned in parallel with each other while extending in the column direction.

[0064] The first to sixth memory cells MC1 to MC6 may be disposed adjacent to intersections of the first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 with the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, and the second read word line RWL2.

[0065] One of the source region and the drain region of the first read transistor RTrl may be shared with the fourth read transistor RTr4 and may be connected to the first read bit line RBL1. One of the source region and the drain region of the second read transistor RTr2 may be shared with the fifth read transistor RTr5 and may be connected to the second read bit line RBL2. One of the source region and the drain region of the third read transistor RTr3 may be shared with the sixth read transistor RTr6 and may be connected to the third read bit line RBL3.

[0066] For example, the first channel region 55 may be disposed between the first source / drain region 51 and the second source / drain region 53 of the first read transistor RTrl. The first source / drain region 51 may contact the third channel region 155 of the fourth read transistor RTr4. The fourth read transistor RTr4 may include the third channel region 155 between the first source / drain region 51 and the fifth source / drain region 153. The first source / drain region 51 may be disposed between the first channel region 55 and the third channel region 155. The first source / drain region 51 may contact the first channel region 55 and the third channel region 155. The first source / drain region 51 may be connected to the first read bit line RBL1.

[0067] Fig.18 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure, Fig.19 is corresponding to Fig.18 Layout diagram of the .

[0068] Reference Fig.18 and Fig.19 In an embodiment, the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, and the second read word line RWL2 may be sequentially arranged in the column direction and aligned in parallel with each other while extending in the row direction. The first write bit line WBL1, the first read bit line RBL1, the second read bit line RBL2, the second write bit line WBL2, the third write bit line WBL3, and the third read bit line RBL3 may be sequentially arranged in the row direction and aligned in parallel with each other while extending in the column direction.

[0069] One of the source region and the drain region of the first read transistor RTrl may be shared with the fourth read transistor RTr4 and may be connected to the first read bit line RBL1. One of the source region and the drain region of the second read transistor RTr2 may be shared with the fifth read transistor RTr5 and may be connected to the second read bit line RBL2. The first read transistor RTr1 may be disposed adjacent to the second read transistor RTr2, and the fourth read transistor RTr4 may be disposed adjacent to the fifth read transistor RTr5. The first read transistor RTr1, the second read transistor RTr2, the fourth read transistor RTr4, and the fifth read transistor RTr5 may be disposed in the first conductive type region 125.

[0070] The second write transistor WTr2 may be disposed adjacent to the third write transistor WTr3, and the fifth write transistor WTr5 may be disposed adjacent to the sixth write transistor WTr6. The second, third, fifth, and sixth write transistors WTr2, WTr3, WTr5, and WTr6 may be disposed in the second conductive type region 126.

[0071] Fig. 20 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure, Fig.21 is with Fig. 20 The corresponding layout diagram.

[0072] Reference Fig. 20 and Fig.21 In an embodiment, the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, the second read word line RWL2, the third write word line WWL3, the fourth write word line WWL4, and the third read word line RWL3 may be sequentially arranged in the column direction and aligned in parallel with each other while extending in the row direction. The first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3, and the third read bit line RBL3 may be sequentially arranged in the row direction and aligned in parallel with each other while extending in the column direction.

[0073] The first to twelfth memory cells MC1 to MC12 may be arranged adjacent to intersections of the first write bit line WBL1, the first read bit line RBL1, the second write bit line WBL2, the second read bit line RBL2, the third write bit line WBL3 and the third read bit line RBL3 and the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, the second read word line RWL2, the third write word line WWL3, the fourth write word line WWL4 and the third read word line RWL3.

[0074] One of the source and drain regions of the fourth read transistor RTr4 and one of the source and drain regions of the seventh read transistor RTr7 may be connected to the second read word line RWL2. One of the source and drain regions of the fifth read transistor RTr5 and one of the source and drain regions of the eighth read transistor RTr8 may be connected to the second read word line RWL2. One of the source and drain regions of the sixth read transistor RTr6 and one of the source and drain regions of the ninth read transistor RTr9 may be connected to the second read word line RWL2.

[0075] Fig. 22 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present disclosure, Fig.23 is with Fig. 22 The corresponding layout diagram.

[0076] Reference Fig. 22 and Fig.23 In an embodiment, the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, the second read word line RWL2, the third write word line WWL3, the fourth write word line WWL4, and the third read word line RWL3 may be sequentially arranged in a column direction and aligned in parallel with each other while extending in a row direction. The first write bit line WBL1, the first read bit line RBL1, the second read bit line RBL2, the second write bit line WBL2, the third write bit line WBL3, and the third read bit line RBL3 may be sequentially aligned in parallel with each other in a row direction.

[0077] The first to twelfth memory cells MC1 to MC12 may be arranged adjacent to intersections of the first write bit line WBL1, the first read bit line RBL1, the second read bit line RBL2, the second write bit line WBL2, the third write bit line WBL3 and the third read bit line RBL3 and the first read word line RWL1, the first write word line WWL1, the second write word line WWL2, the second read word line RWL2, the third write word line WWL3, the fourth write word line WWL4 and the third read word line RWL3.

[0078] The first read transistor RTr1 may be disposed adjacent to the second read transistor RTr2, the fourth read transistor RTr4 may be disposed adjacent to the fifth read transistor RTr5, the seventh read transistor RTr7 may be disposed adjacent to the eighth read transistor RTr8, and the tenth read transistor RTr10 may be disposed adjacent to the eleventh read transistor RTr11. The first read transistor RTr1, the second read transistor RTr2, the fourth read transistor RTr4, the fifth read transistor RTr5, the seventh read transistor RTr7, the eighth read transistor RTr8, the tenth read transistor RTr10, and the eleventh read transistor RTr11 may be disposed in the first conductive type region 125.

[0079] The second write transistor WTr2 may be disposed adjacent to the third write transistor WTr3, the fifth write transistor WTr5 may be disposed adjacent to the sixth write transistor WTr6, the eighth write transistor WTr8 may be disposed adjacent to the ninth write transistor WTr9, and the eleventh write transistor WTr11 may be disposed adjacent to the twelfth write transistor WTr12. The second write transistor WTr2, the third write transistor WTr3, the fifth write transistor WTr5, the sixth write transistor WTr6, the eighth write transistor WTr8, the ninth write transistor WTr9, the eleventh write transistor WTr11, and the twelfth write transistor WTr12 may be disposed in the second conductive type region 126.

[0080] One of the source and drain regions of the fourth read transistor RTr4 and one of the source and drain regions of the seventh read transistor RTr7 may be connected to the second read word line RWL2. One of the source and drain regions of the fifth read transistor RTr5 and one of the source and drain regions of the eighth read transistor RTr8 may be connected to the second read word line RWL2. One of the source and drain regions of the sixth read transistor RTr6 and one of the source and drain regions of the ninth read transistor RTr9 may be connected to the second read word line RWL2.

[0081] Figures 24 to 31 is a cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure. Figures 24 to 31 Can be along Figure 3 Cross-sectional views taken along lines II' and II-II'.

[0082] Reference Figure 3 and Fig.24 , a first well 23 may be formed in the substrate 21 . An isolation layer 27 defining the first active region 25 and the second active region 26 may be formed in the substrate 21 .

[0083] The substrate 21 may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The substrate 21 may include a III-V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 21 may include single crystal silicon, polycrystalline silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0084] The substrate 21 may include a first conductive type impurity, and the first well 23 may include a second conductive type impurity. Each of the first conductive type impurity and the second conductive type impurity may include a P-type impurity or an N-type impurity. The P-type impurity may include B, BF, BF 2 or a combination thereof, and the N-type impurities may include P, As, or a combination thereof. The second conductive type impurities may include conductive type impurities different from the first conductive type impurities.

[0085] In an embodiment, the first conductive type impurity may include a P-type impurity, and the second conductive type impurity may include an N-type impurity. The substrate 21 may include a semiconductor layer such as a single crystal silicon layer having a P-type impurity, and the first well 23 may include a semiconductor layer such as a single crystal silicon layer having an N-type impurity. For example, the first well 23 may correspond to an N-well.

[0086] The first active region 25, the second active region 26 and the isolation layer 27 may be formed using a trench isolation technique such as shallow trench isolation (STI). The second active region 26 may be spaced apart from the first active region 25. The first active region 25 may be defined in the substrate 21 by the isolation layer 27. The second active region 26 may be defined in the first well 23 by the isolation layer 27. In an embodiment, the first active region 25 may include a semiconductor layer such as single crystal silicon having a P-type impurity. The second active region 26 may include a semiconductor layer such as single crystal silicon having an N-type impurity.

[0087] Isolation layer 27 may include a single layer or multiple layers. Isolation layer 27 may include at least two selected from the group consisting of Si, O, N, C, and H. Isolation layer 27 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0088] In an embodiment, the isolation layer 27 may include a first insulating layer 28 and a second insulating layer 29. The first insulating layer 28 may contact side surfaces of the first active region 25 and the second active region 26. The first insulating layer 28 may include an oxide liner, a nitride liner, or a combination thereof. The second insulating layer 29 may be formed on the first insulating layer 28. The second insulating layer 29 may include silicon oxide.

[0089] Reference Figure 3 and Fig.25 By using multiple thin film formation processes and multiple patterning processes, a channel dielectric layer 31, a charge holding node 33, a first gate dielectric layer 35, a first gate electrode 37, a first covering pattern 38, a first gate spacer 39, a second gate dielectric layer 42, a second gate electrode 44, a second covering pattern 45 and a second gate spacer 48 can be formed on a substrate 21 including a first active area 25, a second active area 26 and an isolation layer 27.

[0090] Charge holding node 33 may be formed on first active region 25 and may extend onto isolation layer 27 adjacent to second active region 26. Channel dielectric layer 31 may be formed between first active region 25 and charge holding node 33 and may extend between isolation layer 27 and charge holding node 33.

[0091] The first gate electrode 37 may be formed on the charge holding node 33, which is formed on the first active region 25. The first gate dielectric layer 35 may be formed between the charge holding node 33 and the first gate electrode 37. The first capping pattern 38 may be formed on the first gate electrode 37. At least one side surface of each of the first capping pattern 38, the first gate electrode 37, the first gate dielectric layer 35, and the charge holding node 33 may be aligned on substantially the same plane. At least one side surface of each of the first capping pattern 38, the first gate electrode 37, the first gate dielectric layer 35, and the charge holding node 33 may be vertically aligned. The first gate spacer 39 may be formed on the side surfaces of the first capping pattern 38, the first gate electrode 37, the first gate dielectric layer 35, the charge holding node 33, and the channel dielectric layer 31.

[0092] A second gate electrode 44 may be formed over the second active region 26. A second gate dielectric layer 42 may be formed between the second active region 26 and the second gate electrode 44. A second capping pattern 45 may be formed on the second gate electrode 44. A second gate spacer 48 may be formed on side surfaces of the second capping pattern 45, the second gate electrode 44, and the second gate dielectric layer 42.

[0093] Each of the charge holding node 33, the first gate electrode 37, and the second gate electrode 44 may include a single layer or multiple layers. Each of the charge holding node 33, the first gate electrode 37, and the second gate electrode 44 may include a conductive material such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. The charge holding node 33, the first gate electrode 37, and the second gate electrode 44 may include different materials.

[0094] Each of the channel dielectric layer 31, the first gate dielectric layer 35, and the second gate dielectric layer 42 may include a single layer or multiple layers. Each of the channel dielectric layer 31, the first gate dielectric layer 35, and the second gate dielectric layer 42 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. The channel dielectric layer 31, the first gate dielectric layer 35, and the second gate dielectric layer 42 may include different materials.

[0095] Each of the first capping pattern 38, the first gate spacer 39, the second capping pattern 45, and the second gate spacer 48 may include a single layer or multiple layers. Each of the first capping pattern 38, the first gate spacer 39, the second capping pattern 45, and the second gate spacer 48 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0096] Reference Figure 3 and Fig.26, a first mask pattern 50 covering the second active region 26 and exposing the first active region 25 may be formed on the substrate 21. By using the first mask pattern 50, the first capping pattern 38, the first gate spacer 39, and the first gate electrode 37 as an ion implantation mask, a first source / drain region 51 and a second source / drain region 53 may be formed in the first active region 25. The first source / drain region 51 and the second source / drain region 53 may be formed adjacent to the first capping pattern 38, the first gate spacer 39, and the outer portion of the first gate electrode 37. A first channel region 55 may be defined between the first source / drain region 51 and the second source / drain region 53 in the first active region 25. The first channel region 55 may be aligned below the first gate electrode 37. The first source / drain region 51 and the second source / drain region 53 may include impurities of a different conductivity type from that of the first channel region 55.

[0097] In an embodiment, the first channel region 55 may include a semiconductor layer such as single crystalline silicon having P-type impurities. The first source / drain region 51 and the second source / drain region 53 may include a semiconductor layer such as single crystalline silicon having N-type impurities.

[0098] Reference Figure 3 and Fig. 27 , the first mask pattern 50 may be removed. A second mask pattern 60 covering the first active region 25 and exposing the second active region 26 may be formed on the substrate 21 .

[0099] By using the second mask pattern 60, the second capping pattern 45, the second gate spacer 48, and the second gate electrode 44 as an ion implantation mask, a third source / drain region 61 and a fourth source / drain region 63 may be formed in the second active region 26. The third source / drain region 61 and the fourth source / drain region 63 may be formed adjacent to the second capping pattern 45, the second gate spacer 48, and the outer portion of the second gate electrode 44. A second channel region 66 may be defined between the third source / drain region 61 and the fourth source / drain region 63 in the second active region 26. The second channel region 66 may be aligned under the second gate electrode 44. The third source / drain region 61 and the fourth source / drain region 63 may include impurities of a different conductivity type from the second channel region 66.

[0100] In an embodiment, the second channel region 66 may include a semiconductor layer such as single crystalline silicon having N-type impurities. The third source / drain region 61 and the fourth source / drain region 63 may include a semiconductor layer such as single crystalline silicon having P-type impurities.

[0101] Reference Figure 3 and Fig.28, the second mask pattern 60 may be removed, and a first interlayer insulating layer 72 may be formed on the substrate 21. The first interlayer insulating layer 72 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0102] Reference Figure 3 and Fig.29 By patterning the first interlayer insulating layer 72, an opening 72H exposing the third source / drain region 61 and the charge holding node 33 may be formed. The upper surface and the side surface of the charge holding node 33 may be partially exposed in the opening 72H. In an embodiment, in the opening 72H, a portion or all of the first gate spacer 39 may be removed. In the opening 72H, the first gate spacer 39 may be partially retained on the side surface of the charge holding node 33. In the opening 72H, the first gate spacer 39 may be removed to expose a portion of the side surface of the charge holding node 33.

[0103] Reference Figure 3 and Fig.30 , the interconnection 73 and the contact capping pattern 79 may be sequentially formed in the opening 72H. The interconnection 73 may contact the upper surface and the side surface of the charge holding node 33, and may contact the third source / drain region 61. The interconnection 73 may be formed in a variety of ways, including the same as in the above reference. Figures 5 to 8 The interconnect 73 may include a single layer or multiple layers. The interconnect 73 may include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. A contact capping pattern 79 may be formed in the opening 72H to cover the interconnect 73. The contact capping pattern 79 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0104] Reference Figure 3 and Fig.31 A first contact plug 83 contacting the first source / drain region 51 by passing through the first interlayer insulating layer 72 and a second contact plug 84 contacting the fourth source / drain region 63 by passing through the first interlayer insulating layer 72 may be formed. A first read bit line RBL1 and a first write bit line WBL1 may be formed on the first interlayer insulating layer 72.

[0105] The first read bit line RBL1 may contact the first contact plug 83. The first write bit line WBL1 may contact the second contact plug 84. A second interlayer insulating layer 82 covering the first read bit line RBL1 and the first write bit line WBL1 may be formed on the first interlayer insulating layer 72. The second interlayer insulating layer 82 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0106] Refer again Figure 1 and Figure 3 , a third contact plug 85 may be formed, the third contact plug 85 contacting the second source / drain region 53 by passing through the second interlayer insulating layer 82 and the first interlayer insulating layer 72. A fourth contact plug 86 may be formed, the fourth contact plug 86 contacting the first gate electrode 37 by passing through the second interlayer insulating layer 82, the first interlayer insulating layer 72, and the first capping pattern 38. A fifth contact plug 87 may be formed, the fifth contact plug 87 contacting the second gate electrode 44 by passing through the second interlayer insulating layer 82, the first interlayer insulating layer 72, and the second capping pattern 45. A first read word line RWL1 contacting the third contact plug 85 may be formed on the second interlayer insulating layer 82. A first write word line WWL1 contacting the fourth contact plug 86 and the fifth contact plug 87 may be formed on the second interlayer insulating layer 82.

[0107] Each of the first contact plug 83, the second contact plug 84, the third contact plug 85, the fourth contact plug 86, the fifth contact plug 87, the first read word line RWL1, the first read bit line RBL1, the first write word line WWL1, and the first write bit line WBL1 may include a single layer or multiple layers. Each of the first contact plug 83, the second contact plug 84, the third contact plug 85, the fourth contact plug 86, the fifth contact plug 87, the first read word line RWL1, the first read bit line RBL1, the first write word line WWL1, and the first write bit line WBL1 may include a conductive material such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0108] Although exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only as illustrative and not intended to limit the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted in conjunction with the appended claims and encompass all equivalents that fall within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: A first transistor and a second transistor are provided on a substrate, Wherein, the first transistor comprises: a first source / drain region and a second source / drain region; a first channel region located between the first source / drain region and the second source / drain region; a first gate electrode located on the first channel region; and a charge holding node located between the first channel region and the first gate electrode, and Wherein, the second transistor comprises: a third source / drain region and a fourth source / drain region, a portion of the third source / drain region being connected to the charge holding node; a second channel region located between the third source / drain region and the fourth source / drain region; and A second gate electrode is located on the second channel region.

2. The semiconductor device according to claim 1, wherein The second gate electrode is connected to the first gate electrode.

3. The semiconductor device according to claim 2, further comprising: a write word line connected to the first gate electrode and the second gate electrode; a read bit line connected to the first source / drain region; a read word line connected to the second source / drain region; as well as A write bit line is connected to the fourth source / drain region.

4. The semiconductor device according to claim 1, wherein: The charge holding node includes a conductive material, and the conductive material includes a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

5. The semiconductor device according to claim 1, further comprising: An interconnect is located between the third source / drain region and the charge holding node.

6. The semiconductor device according to claim 5, wherein: The interconnect contacts an upper surface and a side surface of the charge holding node.

7. The semiconductor device according to claim 5, further comprising: A Schottky barrier layer is located between the interconnect and the third source / drain region.

8. The semiconductor device according to claim 7, wherein: The third source / drain region includes a first concentration of P-type impurities, and The Schottky barrier layer includes a second concentration of P-type impurities, the second concentration being lower than the first concentration.

9. The semiconductor device according to claim 7, wherein: The interconnect includes TiN, W, Al or a combination thereof.

10. The semiconductor device according to claim 1, wherein The second channel region includes impurities having a conductivity type different from that of impurities of the first channel region.

11. The semiconductor device according to claim 10, wherein: The first channel region includes a semiconductor layer having P-type impurities, and The second channel region includes a semiconductor layer having N-type impurities.

12. The semiconductor device according to claim 1, further comprising: a channel dielectric layer located between the first channel region and the charge holding node; as well as a gate dielectric layer located between the charge holding node and the first gate electrode, The EOT of the gate dielectric layer is 0.5 to 2 times the EOT of the channel dielectric layer, and the EOT is an equivalent oxide thickness.

13. The semiconductor device according to claim 12, wherein: The EOT of the gate dielectric layer is substantially the same as the EOT of the channel dielectric layer.

14. A semiconductor device comprising: a read word line extending in the row direction; a write word line spaced apart from the read word line in a column direction; a plurality of write bit lines spaced apart from each other and intersecting the read word lines and the write word lines; a plurality of read bit lines spaced apart from each other and intersecting the read word lines and the write word lines; a plurality of memory cells adjacent to intersections of the plurality of write bit lines and the plurality of read bit lines with the read word lines and the write word lines, Each of the plurality of memory cells comprises a read transistor and a write transistor, The read transistor comprises: a first gate electrode located on the channel region; and a charge holding node located between the channel region and the first gate electrode, and The write transistor comprises: a source / drain region connected to the charge holding node; and A second gate electrode is connected to the first gate electrode.

15. The semiconductor device according to claim 14, wherein: The plurality of memory cells include first to third memory cells arranged in the row direction, The first to third memory cells include first to third read transistors and first to third write transistors, respectively. The first read transistor of the first memory cell is disposed adjacent to the second read transistor of the second memory cell, and The second write transistor of the second memory cell is disposed adjacent to the third write transistor of the third memory cell.

16. The semiconductor device according to claim 14, wherein The first gate electrode and the second gate electrode are connected to the write word line.

17. The semiconductor device according to claim 16, wherein: The read transistor is an NMOS transistor, and the write transistor is a PMOS transistor.

18. A semiconductor device comprising: a first read word line and a second read word line which are spaced apart from each other in a column direction, each of the first read word line and the second read word line extending in a row direction; a first write word line and a second write word line spaced apart from each other in the column direction, each of the first write word line and the second write word line extending in the row direction; a first write bit line intersecting the first read word line and the second read word line and the first write word line and the second write word line; a first read bit line intersecting the first read word line and the second read word line and the first write word line and the second write word line; a first storage cell adjacent to an intersection where the first write bit line and the first read bit line intersect the first read word line and the first write word line; as well as a fourth storage unit adjacent to an intersection point where the first write bit line and the first read bit line intersect with the second read word line and the second write word line, Wherein, the first storage unit includes a first read transistor and a first write transistor; Wherein, the fourth storage unit includes a fourth read transistor and a fourth write transistor; Wherein, the first read transistor comprises: a first source / drain region and a second source / drain region, a first channel region located between the first source / drain region and the second source / drain region, a first gate electrode located on the first channel region, and a charge holding node located between the first channel region and the first gate electrode; wherein the first source / drain region of the first read transistor contacts the third channel region of the fourth read transistor; and Wherein, the first write transistor comprises: a third source / drain region and a fourth source / drain region, the third source / drain region being connected to the charge holding node, a second channel region located between the third source / drain region and the fourth source / drain region, and A second gate electrode is located on the second channel region.

19. The semiconductor device according to claim 18, further comprising: A third write word line is arranged in the column direction of the second write word line, and the second write word line is arranged between the first write word line and the third write word line; as well as a seventh storage unit adjacent to an intersection point where the first write bit line and the first read bit line intersect with the second read word line and the third write word line, The seventh storage unit includes a seventh read transistor and a seventh write transistor, and One of the source and the drain of the fourth read transistor and one of the source and the drain of the seventh read transistor are connected to the second read word line.

20. The semiconductor device according to claim 18, wherein The second gate electrode is connected to the first gate electrode, and the first gate electrode and the second gate electrode are connected to the first write word line.

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