Memory structure and forming method thereof
By forming a gap between the word line gate structure and the floating gate structure of the split gate flash memory, the problems of poor memory performance and over-erase in the prior art are solved, and higher memory performance is achieved.
Patent Information
- Application Number
- CN202311148864.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-06
- Publication Date
- 2025-03-11
AI Technical Summary
The existing sub-gate flash memory has poor performance and has problems with over-erase.
A memory structure is designed, including a substrate, an erase region, a floating gate region and a word line gate region. By forming a gap between the word line gate structure and a floating gate structure, leakage is avoided and the influence of parasitic capacitance is reduced.
The leakage phenomenon between the word line gate structure and the floating gate structure is effectively avoided, the impact caused by parasitic capacitance is reduced, and the performance of the memory is improved.
Smart Images
Figure CN119603965A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art
[0002] In the current semiconductor industry, integrated circuit products can be divided into three main types: analog circuits, digital circuits, and mixed analog / digital circuits. Among them, memory is an important type of digital circuit. Among memories, the development of flash memory (Flash Memory, referred to as flash memory) has been particularly rapid in recent years. The main feature of flash memory is that it can store information for a long time without power, and it has the advantages of high integration, fast storage speed, easy erasure and rewriting. Therefore, it has been widely used in many fields such as microcomputers and automation control.
[0003] Flash memory is divided into two types: stack gate flash memory and split gate flash memory. Stack gate flash memory has a floating gate and a control gate located above the floating gate. Stack gate flash memory has the problem of over-erasure. Unlike stack gate flash memory, split gate flash memory forms a word line as an erase gate on one side of the floating gate. Split gate flash memory can effectively avoid the over-erasure effect.
[0004] However, the performance of existing split-gate flash memories is relatively poor. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a memory structure and a forming method thereof, so as to improve the performance of the memory.
[0006] In order to solve the above problems, the present invention provides a memory structure, including: a substrate, the substrate including a floating gate region, an erase region and a word line gate region distributed on both sides of the floating gate region; an erase gate structure located on the erase region; a floating gate structure located on the floating gate region, and a control gate structure located on the floating gate structure; a word line gate structure located on the word line gate region, the floating gate structure being located between the erase gate structure and the word line gate structure; and a gap between the word line gate structure and the floating gate structure.
[0007] Optionally, the top of the gap is flush with the top of the floating gate structure or the top of the gap is lower than the top of the floating gate structure.
[0008] Optionally, it also includes a source line doping region located in the erase area, and the erase gate structures on the erase area between adjacent floating gate regions share the source line doping region.
[0009] Optionally, it also includes a bit line doping region located in the substrate, and the bit line doping region is located on one side of the word line gate structure.
[0010] Optionally, it also includes a first oxide layer located on the substrate, and the first oxide layer covers the erase gate structure and the control gate structure.
[0011] Optionally, it further includes partitions respectively located on part of the word line gate structure sidewall and part of the control gate structure sidewall, the gap is located between the partition and the substrate, and the partition exposes the gap.
[0012] Optionally, a second oxide layer is also included, the second oxide layer covers the word line gate structure, and the second oxide layer seals the top of the gap.
[0013] Optionally, the material of the partition portion includes one or a combination of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
[0014] Correspondingly, the present invention also provides a method for forming a memory structure, comprising: providing a substrate, the substrate comprising a floating gate region, an erase region and a word line gate region located on both sides of the floating gate region; forming an erase gate structure on the erase region; forming a floating gate structure on the floating gate region, and forming a control gate structure on the floating gate structure; forming a word line gate structure in the word line gate region, the floating gate structure being located between the erase gate structure and the word line gate structure; and forming a gap between the word line gate structure and the floating gate structure.
[0015] Optionally, the top of the gap is flush with the top of the floating gate structure or the top of the gap is lower than the top of the floating gate structure.
[0016] Optionally, before forming the gap, the method further includes forming an initial oxide layer on the substrate, wherein the initial oxide layer covers the erase gate structure, the control gate structure and the word line gate structure.
[0017] Optionally, the step of forming a gap includes: forming a mask layer on the surface of the initial oxide layer corresponding to the erase gate structure and the control gate structure; using the mask layer as a mask, etching and removing the top surface of the word line gate structure and the initial oxide layer between the word line gate structure and the control gate structure to form a first oxide layer, and the top of the first oxide layer between the word line gate structure and the floating gate structure is flush with the top of the floating gate structure.
[0018] Optionally, the step of forming the gap further includes: forming a sacrificial layer on the surface of the first oxide layer, wherein the sacrificial layer covers the word line gate structure and fills between the word line gate structure and the control gate structure.
[0019] Optionally, the step of forming the gap further includes: etching back to remove the sacrificial layer, forming a partition on a portion of the word line gate structure sidewall and a portion of the control gate structure sidewall, the partition being located on the top of the first oxide layer between the word line gate structure and the floating gate structure.
[0020] Optionally, the step of forming a gap further includes: removing the first oxide layer at the bottom of the partition portion to expose the surface of the substrate, and forming a gap between the word line gate structure and the floating gate structure.
[0021] Optionally, after forming the gap, a second oxide layer is formed on the surface of the word line gate structure and the surface of the partition portion, and the second oxide layer seals the top of the gap, and the top surface of the second oxide layer is flush with the top surface of the first oxide layer.
[0022] Optionally, the material of the partition portion includes one or a combination of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
[0023] Optionally, it also includes forming a source line doping region in the erase region, and the erase gate structures on the erase region between adjacent floating gate regions share the source line doping region.
[0024] Optionally, the method further includes forming a bit line doping region in the substrate, wherein the bit line doping region is located on one side of the word line gate structure.
[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0026] In the memory structure of the technical solution of the present invention, the erase gate structure is located on the erase area; the floating gate structure is located on the floating gate area, and the control gate structure is located on the floating gate structure; the word line gate structure is located on the word line gate area, and the floating gate structure is located between the erase gate structure and the word line gate structure; the gap is located between the word line gate structure and the floating gate structure; the existence of the gap is utilized to avoid leakage between the word line gate structure and the floating gate structure, and the influence caused by parasitic capacitance is reduced, and the memory has a wider range of applications.
[0027] In the method for forming a memory structure of the technical solution of the present invention, an erase gate structure is formed on the erase area; a floating gate structure is formed on the floating gate area, and a control gate structure is formed on the floating gate structure; a word line gate structure is formed in the word line gate area, and the floating gate structure is located between the erase gate structure and the word line gate structure; a gap is formed between the word line gate structure and the floating gate structure; the existence of the gap is utilized to avoid leakage between the word line gate structure and the floating gate structure, and the influence caused by parasitic capacitance is reduced, and the method has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a cross-sectional schematic diagram of a flash memory;
[0029] Figures 2 to 9 It is a schematic diagram of the memory structure and each step of the formation method thereof in an embodiment of the present invention. DETAILED DESCRIPTION
[0030] As the background technology, the performance of the existing split-gate flash memory is relatively poor.
[0031] Figure 1 A cross-sectional schematic diagram of a flash memory.
[0032] Please refer to Figure 1 A flash memory comprises: a substrate 100, the substrate 100 comprises an erase region A and a floating gate region B, the floating gate region B is adjacent to the erase region A and is located on both sides of the erase region A; an oxide layer 160 located on the substrate 100; an erase gate structure 130 located on the erase region A; floating gate structures 120 respectively located on the floating gate regions B; a control gate structure 121 located on the floating gate structure 120, the control gate structure 121 is vertically separated from the floating gate structure 120; a word line gate structure 140 located on one side of the floating gate structure 120, the floating gate structure 120 is located between the erase gate structure 130 and the word line gate structure 140; a source region 110 located in the erase region A; a bit line structure 150 located in the substrate 100, and the bit line structure 150 is located on one side of the word line gate structure 140.
[0033] However, in the structure of the above-mentioned flash memory, the word line gate structure 140 and the floating gate structure 120 are isolated by the oxide layer 160, so there is a parasitic capacitance between the word line gate structure 140 and the floating gate structure 120, which will cause the threshold voltage of the floating gate structure 120 to mutate. At the same time, as the oxide layer 160 becomes thinner, the leakage between the word line gate structure 140 and the floating gate structure 120 will become more and more obvious.
[0034] On this basis, the present invention provides a memory structure and a method for forming the same, forming a gap between the word line gate structure and the floating gate structure to avoid leakage between the word line gate structure and the floating gate structure, and reducing the impact caused by parasitic capacitance, having a wider range of applications.
[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0036] Figures 2 to 9 It is a schematic diagram of the memory structure and each step of the formation method thereof in an embodiment of the present invention.
[0037] Please refer to Figure 2 , providing a substrate 200, the substrate 200 includes a floating gate region I, an erase region II located on both sides of the floating gate region I, and a word line gate region III.
[0038] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate 200 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate 200 may also be a silicon substrate on an insulator or a germanium substrate on an insulator.
[0039] In this embodiment, there are two floating gate regions I, and the erase regions II between adjacent floating gate regions I share a common source design.
[0040] Please continue to refer to Figure 2 , an erase gate structure 201 is formed on the erase area II; a floating gate structure 202 is formed on the floating gate area I, and a control gate structure 203 is formed on the floating gate structure 202; a word line gate structure 204 is formed in the word line gate area III, and the floating gate structure 202 is located between the erase gate structure 201 and the word line gate structure 204.
[0041] In this embodiment, a source line doping region 205 is further formed in the erase region II, and the erase gate structures 201 on the erase region II between adjacent floating gate regions I share the source line doping region 205 .
[0042] In this embodiment, a bit line doping region 206 is further formed in the substrate 200 . The bit line doping region 206 is located on one side of the word line gate structure 204 .
[0043] Please continue to refer to Figure 2 In the process of forming the floating gate structure 202, the control gate structure 203, the erase gate structure 201 and the word line gate structure 204 respectively, a multi-layer starting oxide layer is simultaneously formed as the dielectric layer 207. After the floating gate structure 202, the control gate structure 203, the erase gate structure 201 and the word line gate structure 204 are formed respectively, the substrate 200 has a starting oxide layer covering the control gate structure 203 and the erase gate structure 201, and the starting oxide layer fills the space between the word line gate structure 204 and the floating gate structure 202.
[0044] Please refer to Figure 3 , an initial oxide layer 208 is formed on the substrate 200, and the initial oxide layer covers the erase gate structure 201, the control gate structure 203 and the word line gate structure 204. Specifically, a re-oxidation layer is formed on the surface of the initial oxide layer and the surface of the word line gate structure 204, and the re-oxidation layer and the initial oxide layer constitute the initial oxide layer on the substrate 200.
[0045] In this embodiment, the material of the initial oxide layer 208 is silicon oxide.
[0046] In this embodiment, the initial oxide layer 208 is formed by a chemical vapor deposition process.
[0047] In other embodiments, the initial oxide layer 208 may be formed by a physical vapor deposition process or an atomic layer deposition process.
[0048] Please refer to Figure 4 A mask layer 209 is formed on the surface of the initial oxide layer 208 corresponding to the erase gate structure 201 and the control gate structure 203 .
[0049] In this embodiment, the material of the mask layer 209 is photoresist.
[0050] In this embodiment, the step of forming a mask layer 209 includes: forming an initial mask layer on the surface of the initial oxide layer 208 corresponding to the erase gate structure 201 and the control gate structure 203, patterning the initial mask layer, and forming a mask layer 209 on the surface of the initial oxide layer 208 corresponding to the erase gate structure 201 and the control gate structure 203.
[0051] Please refer to Figure 5 Using the mask layer 209 as a mask, the top surface of the word line gate structure 204 and the initial oxide layer 208 between the word line gate structure 204 and the control gate structure 203 are etched away to form a first oxide layer 210. The top of the first oxide layer 210 between the word line gate structure 204 and the floating gate structure 202 is flush with the top of the floating gate structure 202.
[0052] In this embodiment, the top of the first oxide layer 210 is flush with the top of the floating gate structure 202 .
[0053] In other embodiments, the top of the first oxide layer 210 may be lower than the top of the floating gate structure 202 .
[0054] In this embodiment, a dry etching process is used to etch away the top surface of the word line gate structure 204 and the initial oxide layer 208 between the word line gate structure 204 and the control gate structure 203 .
[0055] In other embodiments, a wet etching process may be used to etch away the top surface of the word line gate structure 204 and the initial oxide layer 208 between the word line gate structure 204 and the control gate structure 203 .
[0056] In this embodiment, after the first oxide layer 210 is formed, the mask layer 209 is removed.
[0057] In this embodiment, an ashing process is used to remove the mask layer 209 .
[0058] In other embodiments, the mask layer 209 is removed by etching.
[0059] Please refer to Figure 6 A sacrificial layer 211 is formed on the surface of the first oxide layer 210 . The sacrificial layer 211 covers the word line gate structure 204 and fills the space between the word line gate structure 204 and the control gate structure 203 .
[0060] In this embodiment, the material of the sacrificial layer 211 is silicon nitride.
[0061] In other embodiments, the material of the sacrificial layer 211 may also be silicon carbide or the like.
[0062] In this embodiment, the sacrificial layer 211 is formed by a chemical vapor deposition process.
[0063] In this embodiment, during the process of forming the sacrificial layer 211 , the gap between the word line gate structure 204 and the control gate structure 203 is particularly filled.
[0064] Please refer to Figure 7 , the sacrificial layer 211 is removed by etching back, and a partition portion 212 is formed on a portion of the sidewall of the word line gate structure 204 and a portion of the sidewall of the control gate structure 203 . The partition portion 212 is located on the top of the first oxide layer 210 between the word line gate structure 204 and the floating gate structure 202 .
[0065] In this embodiment, the partition portion 212, on the one hand, isolates the first oxide layer 210 between the word line gate structure 204 and the floating gate structure 202; on the other hand, during the subsequent formation of the second oxide layer, the partition portion 212 can separate the second oxide layer from the gap to ensure the formation of the gap.
[0066] Please refer to Figure 8 , the first oxide layer 210 at the bottom of the partition portion 212 is removed to expose the surface of the substrate 200 , and a gap 213 is formed between the word line gate structure 204 and the floating gate structure 202 .
[0067] In this embodiment, a wet etching process is used to remove the first oxide layer 210 at the bottom of the partition portion 212 .
[0068] In this embodiment, a gap 213 is formed between the word line gate structure 204 and the floating gate structure 202, thereby reducing the influence of the parasitic capacitance generated between the word line gate structure 204 and the floating gate structure 202 on the memory; at the same time, the risk of leakage due to dielectric loss between the word line gate structure 204 and the floating gate structure 202 is avoided, and the application range is relatively wide.
[0069] Please refer to Fig. 9 A second oxide layer 214 is formed on the surface of the word line gate structure 204 and the surface of the partition portion 212 , and the second oxide layer 214 seals the top of the gap 213 . The top surface of the second oxide layer 214 is flush with the top surface of the first oxide layer 210 .
[0070] In this embodiment, the material of the second oxide layer 214 is silicon oxide.
[0071] In this embodiment, the process of forming the second oxide layer 214 is a chemical vapor deposition process.
[0072] In other embodiments, the process of forming the second oxide layer 214 may also be a physical vapor deposition process, etc.
[0073] Accordingly, the present invention also provides a memory structure, please refer to Fig. 9, including a substrate 200, the substrate 200 including a floating gate region I, an erase region II and a word line gate region III distributed on both sides of the floating gate region I; an erase gate structure 201 located on the erase region II; a floating gate structure 202 located on the floating gate region I, and a control gate structure 203 located on the floating gate structure 202; a word line gate structure 204 located on the word line gate region III, the floating gate structure 202 being located between the erase gate structure 201 and the word line gate structure 204; and a gap 213 located between the word line gate structure 204 and the floating gate structure 202.
[0074] In this embodiment, the gap 213 is located between the word line gate structure 204 and the floating gate structure 202. The existence of the gap 213 avoids leakage between the word line gate structure 204 and the floating gate structure 202, and reduces the influence caused by parasitic capacitance, thus having a wider range of applications.
[0075] In this embodiment, a parasitic capacitor exists between the word line gate structure 204 and the floating gate structure 202. The gap 213 is used to replace the medium between the word line gate structure 204 and the floating gate structure 202, thereby reducing the impact caused by the parasitic capacitor. In addition, during the operation of the memory, the risk of the medium between the word line gate structure 204 and the floating gate structure 202 becoming thinner is eliminated, thereby avoiding leakage between the word line gate structure 204 and the floating gate structure 202.
[0076] In this embodiment, the top of the gap 213 is flush with the top of the floating gate structure 202 .
[0077] In other embodiments, the top of the gap 213 may also be lower than the top of the floating gate structure 202 .
[0078] In this embodiment, a source line doping region 205 located in the erase region II is further included. The erase gate structures 201 on the erase region II between adjacent floating gate regions I share the source line doping region 205 .
[0079] In this embodiment, a bit line doping region 206 located in the substrate 200 is further included. The bit line doping region 206 is located on one side of the word line gate structure 204 .
[0080] In this embodiment, a first oxide layer 210 is further included on the substrate 200 , and the first oxide layer 210 covers the erase gate structure 201 and the control gate structure 203 .
[0081] In this embodiment, a partition portion 212 is further included which is located on a part of the sidewall of the word line gate structure 204 and a part of the sidewall of the control gate structure 203 . A gap 213 is located between the partition portion 212 and the substrate 200 , and the partition portion 212 exposes the gap 213 .
[0082] In this embodiment, the material of the partition portion 212 includes one or a combination of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
[0083] In this embodiment, a second oxide layer 214 is further included. The second oxide layer 214 covers the word line gate structure 204 , and the second oxide layer 214 seals the top of the gap 213 .
[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A memory structure, characterized in that: include: A substrate, the substrate comprising a floating gate region, an erase region and a word line gate region distributed on both sides of the floating gate region; an erase gate structure located on the erase area; a floating gate structure located on the floating gate region, and a control gate structure located on the floating gate structure; A word line gate structure located on the word line gate region, wherein the floating gate structure is located between the erase gate structure and the word line gate structure; A gap is located between the word line gate structure and the floating gate structure.
2. The memory structure according to claim 1, characterized in that: The top of the gap is flush with the top of the floating gate structure or the top of the gap is lower than the top of the floating gate structure.
3. The memory structure according to claim 1, wherein: It also includes a source line doping region located in the erase region, and the erase gate structure on the erase region between adjacent floating gate regions shares the source line doping region.
4. The memory structure according to claim 1, characterized in that: It also includes a bit line doping region located in the substrate, and the bit line doping region is located on one side of the word line gate structure.
5. The memory structure according to claim 1, wherein: It also includes a first oxide layer located on the substrate, wherein the first oxide layer covers the erase gate structure and the control gate structure.
6. The memory structure according to claim 1, wherein: It also includes partition parts respectively located on part of the sidewall of the word line gate structure and part of the sidewall of the control gate structure, the gap is located between the partition part and the substrate, and the partition part exposes the gap.
7. The memory structure according to claim 6, characterized in that: The invention also includes a second oxide layer, wherein the second oxide layer covers the word line gate structure and seals the top of the gap.
8. The memory structure according to claim 6, characterized in that: The material of the partition portion includes one or a combination of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
9. A method for forming a memory structure, characterized in that: include: Providing a substrate, the substrate comprising a floating gate region, an erase region and a word line gate region located on both sides of the floating gate region; forming an erase gate structure on the erase area; forming a floating gate structure on the floating gate region, and forming a control gate structure on the floating gate structure; forming a word line gate structure in the word line gate region, wherein the floating gate structure is located between the erase gate structure and the word line gate structure; A gap is formed between the word line gate structure and the floating gate structure.
10. The method for forming a memory structure according to claim 9, wherein: The top of the gap is flush with the top of the floating gate structure or the top of the gap is lower than the top of the floating gate structure.
11. The method for forming a memory structure according to claim 9, wherein: Before forming the gap, the method further includes forming an initial oxide layer on the substrate, wherein the initial oxide layer covers the erase gate structure, the control gate structure and the word line gate structure.
12. The method for forming a memory structure according to claim 11, wherein: The step of forming the gap includes: forming a mask layer on the surface of the initial oxide layer corresponding to the erase gate structure and the control gate structure; using the mask layer as a mask, etching and removing the top surface of the word line gate structure and the initial oxide layer between the word line gate structure and the control gate structure to form a first oxide layer, and the top of the first oxide layer between the word line gate structure and the floating gate structure is flush with the top of the floating gate structure.
13. The method for forming a memory structure according to claim 12, wherein: The step of forming the gap further includes: forming a sacrificial layer on the surface of the first oxide layer, wherein the sacrificial layer covers the word line gate structure and fills a space between the word line gate structure and the control gate structure.
14. The method for forming a memory structure according to claim 13, wherein: The step of forming the gap also includes: etching back to remove the sacrificial layer, forming a partition on part of the word line gate structure sidewall and part of the control gate structure sidewall, the partition is located on the top of the first oxide layer between the word line gate structure and the floating gate structure.
15. The method for forming a memory structure according to claim 14, wherein: The step of forming the gap further includes: removing the first oxide layer at the bottom of the partition portion to expose the surface of the substrate, and forming the gap between the word line gate structure and the floating gate structure.
16. The method for forming a memory structure according to claim 15, wherein: After forming the gap, the method further includes forming a second oxide layer on the surface of the word line gate structure and the surface of the partition portion, wherein the second oxide layer seals the top of the gap, and the top surface of the second oxide layer is flush with the top surface of the first oxide layer.
17. The method for forming a memory structure according to claim 14, wherein: The material of the partition portion includes one or a combination of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.
18. The method for forming a memory structure according to claim 9, wherein: The method further includes forming a source line doping region in the erase region, wherein the erase gate structures on the erase region between adjacent floating gate regions share the source line doping region.
19. The method for forming a memory structure according to claim 9, wherein: The method also includes forming a bit line doping region in the substrate, wherein the bit line doping region is located on one side of the word line gate structure.