Preparation method of selective electrode contact heterojunction battery and heterojunction battery

Abstract

The invention relates to the technical field of heterojunction solar cells, and particularly discloses a selective electrode contact heterojunction cell preparation method and a heterojunction cell, and the method comprises the steps: carrying out the first texturing of a silicon wafer substrate, carrying out the mask layer preparation of the textured silicon wafer, and carrying out the first patterning processing of the silicon wafer. Performing slotting treatment on two sides of the silicon wafer based on picosecond laser, performing secondary texturing on the silicon wafer, placing the cleaned silicon wafer in a second texturing mixed solution so as to generate a large textured pyramid structure on the inner bottom surface of a groove in the two sides of the silicon wafer, and removing the first mask layer from the silicon wafer after secondary texturing to obtain a second textured pyramid structure; sequentially depositing a plurality of layers including an intrinsic amorphous silicon layer and the like on the two surfaces of the silicon wafer, printing a second mask layer in a counterpoint manner in other areas of the silicon wafer which is provided with the groove in the first time of patterning based on exposure and development, electroplating a copper grid line on the silicon wafer, and sequentially removing the second mask layer and a copper seed layer on the silicon wafer after electroplating the grid line; the selective electrode contact copper grid line heterojunction solar cell is obtained, the problem of grid separation of the copper grid lines is solved, and the cell efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of heterojunction solar cells, and in particular to a method for preparing a selective electrode contact heterojunction cell and a heterojunction cell. Background Art

[0002] In recent years, heterojunction solar cells have attracted widespread attention in the industry due to their excellent performance such as high efficiency and low attenuation.

[0003] In the related art, for the grid lines of heterojunction solar cells, the most cutting-edge technology is to use copper electroplating technology instead of screen printing, and to use metallic copper to completely replace silver paste as the grid line electrode. This method fundamentally solves the problem of high silver paste cost. At the same time, copper and the transparent conductive film TCO are tightly attached, the contact resistance is smaller, the power loss is also smaller, and the conversion efficiency of the battery cell is higher. In addition, the copper grid lines made by copper electroplating are thinner and have better morphology than the silver grid lines made by screen printing, further improving the photoelectric conversion efficiency.

[0004] However, in actual applications, it is found that both copper and silver grid lines have the problem of grid detachment. Moreover, in the existing copper electroplating process technology, the copper grid lines formed by electroplating are more prone to grid detachment than the silver grid lines, which affects the production yield of the battery cells and directly increases the difficulty of mass production. At the same time, the high series resistance leads to large current loss, thereby reducing the overall photoelectric conversion efficiency of the battery. Summary of the invention

[0005] The present application aims to at least solve the problem of gate debonding in heterojunction cells in the prior art, especially the problem that copper grid lines plated in the copper electroplating process are prone to gate debonding and high string resistance, which increases the difficulty of mass production and reduces the overall conversion efficiency of the cell. Therefore, the present application proposes a method for preparing a selective electrode contact heterojunction cell and a heterojunction cell.

[0006] In order to achieve the above objectives, in a first aspect, the present application provides a method for preparing a selective electrode contact heterojunction battery, comprising: Step S10: the first texturing of the silicon wafer substrate, placing the silicon wafer substrate in a first texturing mixed solution, so that small textured pyramid structures are generated on both sides of the silicon wafer substrate, wherein the size of the pyramid structures is between 0.5um and 4um; Step S20: preparing a mask layer of a silicon wafer, depositing a first mask layer for a second texturing on both sides of the silicon wafer after the first texturing, wherein the first mask layer has a thickness of 50nm-250nm and a refractive index between 1.5-2.6; Step S30: the first patterning process of the silicon wafer, using picosecond laser to perform groove processing on both sides of the silicon wafer according to the positions of the electrode gate lines, wherein the depth of the groove is completely ablated to expose the surface of the silicon wafer substrate; Step S40: Second texturing of the silicon wafer, pre-cleaning the grooved silicon wafer, placing the cleaned silicon wafer in a second texturing mixture, so that a large textured pyramid structure is formed on the bottom surface of the double-sided groove of the silicon wafer, wherein the size of the pyramid structure is between 4um and 10um; Step S50: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, a TCO layer and an electroplating seed layer on both sides of the silicon wafer; Step S60: performing a second patterning process on the silicon wafer, and printing a second mask layer on other regions of the silicon wafer where the grooves are opened in the first patterning process based on exposure and development, wherein the second mask layer is an ink mask layer; Step S70: electroplating copper gate lines on the silicon wafer, and removing the second mask layer and the copper seed layer from the silicon wafer after the gate line electroplating in sequence to obtain a selective electrode contact copper gate line heterojunction solar cell.

[0007] According to some embodiments of the present application, in step S10, the first texturing mixture is composed of at least an alkaline solution, a special additive for small suede surfaces and ultrapure water, and the alkaline solution includes a combination of one or more of potassium hydroxide or sodium hydroxide solutions.

[0008] According to some embodiments of the present application, in step S20, the first mask layer includes a combination of one or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.

[0009] According to some embodiments of the present application, in the step S30, the mask layers on the front and back sides of the silicon wafer are grooved according to the positions of preset electrode gate lines based on a picosecond laser, wherein the wavelength range of the picosecond laser is 325nm-532nm, the front main gate groove width range is 50 um-80um, the front auxiliary gate groove width range is 10um-40um, the back main gate groove width range is 50um-250um, and the back auxiliary gate groove width range is 20-80um.

[0010] According to some embodiments of the present application, in step S40, a potassium hydroxide solution is used to clean the laser damaged layer at the grooved positions on the front and back sides of the silicon wafer, and the cleaned silicon wafer is placed in a second texturing mixture for texturing, wherein the second texturing mixture is composed of at least an alkaline solution, a special additive for large texturing surfaces and ultrapure water, and the alkaline solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions.

[0011] According to some embodiments of the present application, in step S50, it includes: Step S51: depositing intrinsic amorphous silicon layers on both sides of the silicon wafer after secondary texturing, wherein the thickness of the intrinsic amorphous silicon layer is in the range of 4nm-10nm; Step S52: Depositing emitter layers on the surfaces of the intrinsic amorphous silicon layer on both sides of the silicon wafer, wherein the emitter layer is one of a doped amorphous silicon layer and a nanocrystalline silicon layer; Step S53: sputtering a high-transmittance TCO layer on the emitter layer surface on both sides of the silicon wafer; Step S54: depositing a seed layer on the surface of the TCO layer on both sides of the silicon wafer, wherein the thickness of the seed layer is in the range of 10 nm to 150 nm.

[0012] According to some embodiments of the present application, in step S52, it includes: Depositing a phosphorus-doped amorphous silicon or a phosphorus-doped nanocrystalline silicon layer on the surface of the intrinsic amorphous silicon layer on the light-receiving surface of the silicon wafer to form a front emitter, wherein the phosphorus-doped amorphous silicon or phosphorus-doped nanocrystalline silicon layer has a thickness ranging from 5nm to 40nm; A boron-doped amorphous silicon or boron-doped nanocrystalline silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the backlight side of the silicon wafer to form a back emitter, wherein the boron-doped amorphous silicon or boron-doped nanocrystalline silicon layer has a thickness of 5nm-60nm.

[0013] According to some embodiments of the present application, in the step S70, it further includes: The electroplated silicon wafer is immersed in an alkaline mixed solution to remove the second mask layer, wherein the alkaline mixed solution includes a combination of one or more potassium hydroxide solutions or sodium hydroxide solutions. The immersion time ranges from 30s to 200s; The silicon wafer with the mask removed is immersed in an acidic mixed solution to remove the copper seed layer other than the copper grid line, wherein the acidic mixed solution includes a combination of one or more of dilute sulfuric acid solution or dilute nitric acid solution.

[0014] According to some embodiments of the present application, when the battery electrode is a silver grid line, the step S40 includes: Step S51: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer and a TCO layer on both sides of the silicon wafer; Step S61: printing electrodes. According to the position of the first patterned groove, a corresponding screen is selected, and silver grid lines are printed on the front and back sides of the silicon wafer by screen printing. After curing, a selective electrode contact silver grid heterojunction solar cell is obtained.

[0015] Compared with the prior art, the technical solution provided in the first aspect of the present application at least includes the following beneficial effects: 1) By performing small velvet on the silicon wafer, a small velvet pyramid structure is formed on both sides of the silicon wafer, and the size of the pyramid structure is controlled at 0.5um -4um, thus increasing the light absorption of heterojunction cells and improving the efficiency of cells. Different from the existing heterojunction cell production process, after the first texturing, a mask layer is deposited on both sides of the silicon wafer, and the mask layer is one of a silicon nitride film, a silicon oxide film and a silicon oxynitride film layer. Then, a gate line groove is opened based on a picosecond laser with a wavelength of 325nm-532nm to complete a graphic processing. Through the laser of a specific wavelength and frequency, the copper gate line width is flexibly adjustable and more refined during the slotting process. After cleaning the laser damaged layer at the slotting position, a second texturing is performed. Due to the existence of the mask layer, the second texturing produces a large velvet pyramid structure in the groove, and the size of the pyramid is controlled between 4um-10um. In this way, after depositing multiple layers and electroplating copper gate lines or printing silver gate lines, the contact specific surface area of ​​the copper electroplating process copper gate lines or silver gate lines and the transparent conductive oxide TCO layer is increased to reduce the series resistance and increase the pulling force, thereby improving the cell efficiency and improving the gate line debonding problem.

[0016] 2) The heterojunction solar cell prepared by the method of the present application effectively increases the specific surface area of ​​the contact between the grid line and the heterojunction solar cell body without increasing the grid line width, thereby reducing the series resistance and improving the fill factor efficiency gain. In addition, the cell structure can effectively increase the bonding force between the copper grid line or the silver grid line and the TCO layer, thereby effectively improving the grid detachment problem and improving the yield rate of the heterojunction solar cell. At the same time, for the copper-gate silicon heterojunction solar cell, two different processes are used when preparing the mask layer before and after twice. Under the premise of ensuring the improvement of grid detachment and the improvement of yield rate, the preparation process of the selective electrode contact silicon heterojunction solar cell is further simplified, thereby improving the production efficiency of the heterojunction solar cell.

[0017] In a second aspect, the present application further provides a copper electroplating back-contact heterojunction battery, which is prepared by the preparation method of a selective electrode contact heterojunction battery provided in any one of the embodiments of the first aspect above.

[0018] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flow chart of a method for preparing a selective electrode contact copper grid heterojunction battery according to an embodiment of the present application; Figure 2 It is a schematic diagram of the first cell structure in the preparation process of the copper grid heterojunction solar cell according to the embodiment of the present application; Figure 3 is a schematic diagram of the second cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Figure 4 It is a schematic diagram of the third cell structure in the preparation process of the copper grid heterojunction solar cell according to the embodiment of the present application; Figure 5 is a schematic diagram of the fourth cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Figure 6 It is a schematic diagram of the fifth cell structure in the preparation process of the copper grid heterojunction solar cell according to the embodiment of the present application; Figure 7 It is a schematic diagram of the sixth cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Figure 8 It is a schematic diagram of the seventh cell structure in the preparation process of the copper grid heterojunction solar cell according to the embodiment of the present application; Fig. 9 It is a schematic diagram of the eighth cell structure in the preparation process of the copper grid heterojunction solar cell according to the embodiment of the present application; Fig.10 It is a schematic diagram of the ninth cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Fig.11 is a schematic diagram of the tenth cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Fig.12 is a schematic diagram of the eleventh cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Fig.13 is a schematic diagram of the twelfth cell structure in the preparation process of the copper grid heterojunction solar cell according to an embodiment of the present application; Reference numerals: 100, silicon wafer substrate; 101, first velvet surface; 102, second velvet surface; 110, first mask layer; 111, first wire groove; 112, second velvet surface; 120, intrinsic amorphous silicon layer, 130a, phosphorus-doped silicon layer; 130b, boron-doped silicon layer; 140, TCO layer; 150, electroplating seed layer; 160, second mask layer; 161, second wire groove; 170, copper gate electrode. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0025] See also Figures 1 to 13 This embodiment provides a method for preparing a selective electrode contact heterojunction battery, comprising: Step S10: the first texturing of the silicon wafer substrate, placing the silicon wafer substrate in a first texturing mixed solution, so that small textured pyramid structures are generated on both sides of the silicon wafer substrate, wherein the size of the pyramid structures is between 0.5um and 4um; In this step, the pre-cleaned silicon wafer substrate is textured for the first time using a texturing process, and the silicon wafer is placed in a special first texturing mixture, wherein the first texturing mixture is composed of at least an alkaline solution, a special additive for small texture surfaces and ultrapure water, the alkaline solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions, the special additive for small texture surfaces mainly contains potassium sorbate, and the solution accounts for 1% to 5%; the first texturing is to form a pyramid light-trapping structure on the surface of the single crystal silicon to increase light absorption, and the reaction time can be controlled at 200s-1800s, so that a pre-set pyramid structure is formed on the front and back (light-receiving and backlighting) surfaces of the silicon wafer substrate, and the size of the pyramid structure is controlled to be between 0.5um-4um.

[0026] In some examples, such as Figure 2As shown, a first velvet surface 101 structure is formed on both sides of the silicon wafer substrate 100. By setting the first velvet surface 101, the effective area of ​​the battery surface can be increased, so that more light can be absorbed, thereby improving the photoelectric conversion efficiency. At the same time, by forming a micron-level texture on the battery surface, the reflection of light can be effectively reduced, and the absorption of light can be further enhanced. The velvet structure can optimize the movement path of carriers, reduce the recombination of carriers, and improve the current output of the battery.

[0027] It can be understood that the thickness and specific material of the silicon wafer substrate 100, as well as other parameters in the texturing process and the required equipment can be selected according to actual needs and are not limited here. For example, optionally, the silicon wafer substrate 100 is an N-type doped single crystal or polycrystalline silicon wafer with a thickness of 80um-160um. The pre-cleaning of the silicon wafer substrate is a conventional process and will not be elaborated here.

[0028] Step S20: preparing a mask layer of a silicon wafer, depositing a first mask layer for a second texturing on both sides of the silicon wafer after the first texturing, wherein the first mask layer has a thickness of 50nm-250nm and a refractive index between 1.5-2.6; In this step, after the first texturing of the silicon wafer substrate, PECVD is used to deposit 50nm-250nm silicon nitride film, silicon oxide film or silicon oxynitride film on the front and back sides of the silicon wafer substrate as the first mask layer for the secondary texturing. At the same time, the refractive index is between 1.5-2.6. The deposition material of the first mask layer can be selected according to actual needs and is not limited here. The specific value of the thickness of the first mask layer and the specific value of the refractive index are within the above range. For example, the thickness is 100nm and the refractive index is 2. The selection is based on actual needs. It can be understood that the restriction of the refractive index can help achieve good optical matching between different materials, reduce light reflection loss, ensure that more light can enter the battery, reduce light reflection between different layers, increase light penetration and absorption, and thus improve photoelectric conversion efficiency.

[0029] In some examples, such as Figure 3 As shown, the first mask layer 110 deposited on both sides of the silicon wafer substrate 100 completely covers its surface. Due to the small thickness of the mask layer, its surface will still maintain a pyramid-shaped velvet surface after deposition. Of course, it should be noted that the PECVD technology and the corresponding equipment are existing technologies, and the deposition principle and related parameter settings can be selected according to actual needs, which will not be elaborated here.

[0030] Step S30: the first patterning process of the silicon wafer, using picosecond laser to perform groove processing on both sides of the silicon wafer according to the positions of the electrode gate lines, wherein the depth of the groove is completely ablated to expose the surface of the silicon wafer substrate; In this step, a picosecond laser with a wavelength of 325nm-532nm is used to groove the mask layers on the front and back sides according to the positions of the electrode gate lines. The width of the front main gate groove is 50-80um, the width of the front auxiliary gate groove is 10um-40um, the width of the back main gate groove is 50um-250um, and the width of the back auxiliary gate groove is 20-80um; the first mask layer at the groove position is completely etched away, that is, the depth of the groove is completely ablated to expose the surface of the silicon wafer substrate.

[0031] It should be noted that in order to increase the specific surface area of ​​contact between the grid line and the heterojunction solar cell, in this method, The setting of the first mask layer can effectively limit the reaction of the mixed texturing solution to the silicon wafer surface area outside the set line groove area during the second texturing, so as to reduce the reflection of light between different layers, increase the penetration and absorption of light, and improve the photoelectric conversion efficiency. In this step, the use of picosecond laser can cooperate well with the first mask layer, so that the copper grid line width can be flexibly adjusted and more refined during the grooving process through the laser of specific wavelength and frequency. At the same time, in this step, a picosecond laser with a wavelength of 325nm-532nm is used for patterning, which can perform precise cutting and engraving at the micron or even submicron level. Combined with the setting of the first mask layer, the groove size can be more accurate.

[0032] In some examples, such as Figure 4 As shown, first linear grooves 111 are opened at intervals on the surface of the first mask layer 110 deposited on both sides of the silicon wafer substrate 100. It should be noted that the number and position of the first linear grooves 111 are selected according to actual needs and are not limited here. The bottom of the first linear groove 111 opened by the picosecond laser extends to the surface of the silicon wafer substrate 100, and the small velvet surface on the surface of the silicon wafer substrate 100 in the first linear groove 111 is completely etched away, that is, the silicon nitride at the groove position is completely etched away. In this way, it is ensured that a pyramid structure with a large velvet surface is formed at the bottom of the first linear groove 111 during the second velvet making.

[0033] Step S40: Second texturing of the silicon wafer, pre-cleaning the grooved silicon wafer, placing the cleaned silicon wafer in a second texturing mixture, so that a large textured pyramid structure is formed on the bottom surface of the double-sided groove of the silicon wafer, wherein the size of the pyramid structure is between 4um and 10um; In this step, the silicon wafer after the groove is pre-cleaned. The pre-cleaning can be performed by using a KOH solution to clean the laser damaged layer at the groove position on the front and back sides of the silicon wafer. The pre-cleaned silicon wafer is subjected to a second texturing process. Specifically, the silicon wafer is placed in a special second texturing mixture, wherein the second texturing mixture is at least composed of an alkaline solution, a special additive for large velvet and ultrapure water, the alkaline solution includes a combination of one or more of potassium hydroxide or sodium hydroxide solutions, and the main component of the special additive for large velvet is 1% to 5% potassium sorbate solution; other components are selected according to actual needs; the role of the second texturing is to form a larger pyramid structure at the gate line position, the purpose is to increase the contact area with the copper gate line, reduce the contact resistance, and thus improve the FF and battery efficiency, the reaction time can be controlled at 200s-1800s, and due to the setting of the first mask layer, a large velvet pyramid structure is formed on the bottom surface of the line groove on the front and back sides (light receiving and backlighting) of the silicon wafer substrate, and the size of the pyramid structure is controlled to be between 3um-10um.

[0034] Step S50: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, a TCO layer and an electroplating seed layer on both sides of the silicon wafer; In this step, after the front and back sides of the silicon wafer are patterned, the second texturing is performed, and then the silicon wafer is placed in an HF aqueous solution to etch away the silicon nitride mask layer on the front and back sides. In this way, a large velvet pyramid structure is formed at the position corresponding to the line groove of the silicon wafer substrate, and a small velvet pyramid structure is retained in other areas corresponding to the position of the line groove of the silicon wafer substrate. Then, an intrinsic amorphous silicon layer, an emitter layer, a TCO layer and an electroplating seed layer are sequentially deposited on both sides of the silicon wafer. Specifically, the following steps are included: Step S51: depositing intrinsic amorphous silicon layers on both sides of the silicon wafer after secondary texturing, wherein the thickness of the intrinsic amorphous silicon layer is in the range of 4nm-10nm; In this step, PECVD is used to deposit an intrinsic amorphous silicon layer with a thickness of 4 nm-10 nm on the front and back sides of the silicon wafer to passivate the crystalline silicon interface. Optionally, the process gas for the intrinsic amorphous silicon layer is a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2) with a refractive index of 3.2-4.8. The intrinsic amorphous silicon layer can passivate the dangling bonds on the surface of the silicon wafer and reduce the surface defect state density.

[0035] Step S52: Depositing emitter layers on the surfaces of the intrinsic amorphous silicon layer on both sides of the silicon wafer, wherein the emitter layer is one of a doped amorphous silicon layer and a nanocrystalline silicon layer; In this step, PECVD is used to deposit emitter layers on the front and back of the silicon wafer. Specifically, doped amorphous silicon / nanocrystalline silicon layers are deposited on the front and back of the silicon wafer, respectively. Phosphorus-doped amorphous silicon / nanocrystalline silicon is deposited on the front with a thickness of 5nm-40nm to form a nn+ high-low heterostructure with crystalline silicon, and boron-doped amorphous silicon / nanocrystalline silicon is deposited on the back with a thickness of 5nm-60nm to form an np heterostructure with crystalline silicon as the back emitter of the battery.

[0036] Step S53: sputtering a high-transmittance TCO layer on the emitter layer surface on both sides of the silicon wafer; In this step, PVD or RPD is used to sputter a layer of highly transmittance conductive film on the front and back sides of the battery to form a TCO layer for collecting carriers. It can be understood that the thickness of the TCO layer is 80 to 120 nm. The TCO layer is a conventional setting for heterojunction solar cells. Its specific implementation conditions and principles can be achieved by existing technologies and will not be elaborated here.

[0037] Step S54: depositing a seed layer on the surface of the TCO layer on both sides of the silicon wafer, wherein the thickness of the seed layer is in the range of 10 nm to 150 nm.

[0038] In this step, electroplating seed layers are prepared on both surfaces of the silicon wafer, and PVD is used to deposit a 10nm-150nm seed layer on the front and back sides of the battery respectively. The seed layer can be roughly divided into three types: copper, nickel and copper-nickel alloy by using different target materials in the PVD sputtering process. The main function of the seed layer is to enhance the bonding force between the copper grid line and the TCO, which helps the heterojunction battery to achieve double-sided electroplating. If the copper grid line is directly grown on the silicon surface, the sintering link is reduced, which is easy to cause the grid detachment problem.

[0039] In some examples, such as Figures 5 to 9 As shown, after the first mask layer 110 of the silicon wafer substrate 100 is removed, a second velvet surface 112 is formed at the bottom of the double-surface surface grooves, and a first velvet surface 101 is formed in other areas of the grooves. At the same time, an intrinsic amorphous silicon layer 120, a phosphorus-doped silicon layer 130a, a TCO layer 140 and an electroplating seed layer 150 are sequentially deposited on the front side, and an intrinsic amorphous silicon layer 120, a boron-doped silicon layer 130b, a TCO layer 140 and an electroplating seed layer 150 are sequentially deposited on the back side.

[0040] Step S60: performing a second patterning process on the silicon wafer, and printing a second mask layer on other regions of the silicon wafer where the grooves are opened in the first patterning process based on exposure and development, wherein the second mask layer is an ink mask layer; In this step, the deposited multi-layer structure silicon wafer is patterned for the second time, and the exposure and development methods are used to perform masking on other areas outside the patterned grooves in the third step; first, ink is printed on the front and back sides of the battery with the electroplating seed layer, then exposed, and finally developed, leaving the ink in the mask area to form a gate line groove. It should be noted that the exposure and development process is a prior art, and its principles and related parameter settings will not be elaborated here.

[0041] It should be noted that this step uses exposure and development for patterning, taking into full consideration that the battery's passivation film, PN junction, and TCO film layers have all been prepared before this step. These film layers are all nanoscale, and laser grooving will cause damage to these film layers, resulting in reduced efficiency.

[0042] Step S70: electroplating copper gate lines on the silicon wafer, and removing the second mask layer and the copper seed layer from the silicon wafer after the gate line electroplating in sequence to obtain a selective electrode contact copper gate line heterojunction solar cell.

[0043] In the step, during the copper electroplating process of the battery, a vertical continuous electroplating method is used to electroplate copper grid lines at the double-sided grid line grooves of the silicon wafer, wherein the front main grid width range is 50 um-80 um, the front sub-grid width range is 10 um-40 um, and the height range is 5 um-20 um; the back main grid width range is 50 um-250 um, the back sub-grid width range is 20 um-80 um; the height range is 5 um-20 um.

[0044] After the copper grid lines are electroplated, the electroplated silicon wafer is immersed in an alkaline mixed solution to remove the second mask layer, wherein the alkaline mixed solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions, and the immersion time ranges from 30s to 200s; the silicon wafer with the mask removed is immersed in an acidic mixed solution to remove the copper seed layer other than the copper grid lines, wherein the acidic mixed solution includes a combination of one or more dilute sulfuric acid or dilute nitric acid solutions, and then cleaned with ultrapure water and dried to obtain a selective electrode contact copper grid line silicon-based heterojunction solar cell, wherein the concentration of potassium hydroxide or sodium hydroxide solution is about 4% to 15%, and the concentration of dilute sulfuric acid or dilute nitric acid solution is about 0.5% to 1.5%;.

[0045] In some examples, such as Figures 10 to 13A second mask layer 160 made of ink is formed on the surface of the electroplating seed layer 150 by exposure and development, and a second line groove 161 is formed on the surface of the second mask layer 160 at a position corresponding to the first line groove 111. After electroplating, a copper grid electrode 170 is formed in the second line groove 161. Finally, the electroplating seed layer 150 and the second mask layer 160 are removed, wherein a portion of the electroplating seed layer 150 is still retained at the bottom of the copper grid electrode 170, to obtain a selective electrode contact copper grid silicon-based heterojunction solar cell.

[0046] In some embodiments, a method for preparing a selective electrode contact silver grid line silicon-based heterojunction solar cell is also provided. It should be noted that the method steps are different from the steps of the copper grid line silicon-based heterojunction solar cell preparation method in that after the secondary texturing in step S40, the following steps are included: Step S51: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer and a TCO layer on both sides of the silicon wafer; In this step, the deposition of the intrinsic amorphous silicon layer, the emitter layer and the TCO layer may refer to the description in the above embodiments, and will not be described in detail here.

[0047] Step S61: printing electrodes. According to the position of the first patterned groove, a corresponding screen is selected, and silver grid lines are printed on the front and back sides of the silicon wafer by screen printing. After curing, a selective electrode contact silver grid heterojunction solar cell is obtained.

[0048] In the above process, a small velvet surface is formed on the silicon wafer to form a small velvet surface pyramid structure on both sides of the silicon wafer, and the size of the pyramid structure is controlled to be 0.5um. -4um, thus increasing the light absorption of heterojunction cells and improving the efficiency of cells. Different from the existing heterojunction cell production process, after the first texturing, a mask layer is deposited on both sides of the silicon wafer, and the mask layer is one of a silicon nitride film, a silicon oxide film and a silicon oxynitride film layer. Then, a gate line groove is opened based on a picosecond laser with a wavelength of 325nm-532nm to complete a graphic processing. Through the laser of a specific wavelength and frequency, the copper gate line width is flexibly adjustable and more refined during the slotting process. After cleaning the laser damaged layer at the slotting position, a second texturing is performed. Due to the existence of the mask layer, the second texturing produces a large velvet pyramid structure in the groove, and the size of the pyramid is controlled between 4um-10um. In this way, after depositing multiple layers and electroplating copper gate lines or printing silver gate lines, the contact specific surface area of ​​the copper electroplating process copper gate lines or silver gate lines and the transparent conductive oxide TCO layer is increased to reduce the series resistance and increase the pulling force, thereby improving the cell efficiency and improving the gate line debonding problem.

[0049] At the same time, without increasing the width of the grid line, the specific surface area of ​​the contact between the grid line and the heterojunction solar cell body is effectively increased, thereby reducing the series resistance and improving the fill factor efficiency gain. In addition, the cell structure can effectively increase the bonding force between the copper grid line or the silver grid line and the TCO layer, thereby effectively improving the grid detachment problem and improving the yield rate of the heterojunction solar cell. At the same time, for copper-gate silicon heterojunction solar cells, two different processes are used when preparing the mask layer before and after twice. Under the premise of ensuring improved grid detachment and improved yield rate, the preparation process of selective electrode contact silicon heterojunction solar cells is further simplified, thereby improving the production efficiency of heterojunction solar cells.

[0050] In some embodiments, a comparison of experimental data between a copper-gate heterojunction solar cell prepared by the above method and a common copper-gate heterojunction solar cell is provided, as shown in the following table (1), wherein the copper-gate control group is a common copper-gate heterojunction solar cell, and the copper-gate experimental groups 1-3 are copper-gate heterojunction solar cells prepared by the above method. After two texturing processes, the gate line pull-off force of the copper-gate experimental group 2 is significantly greater than that of the common copper-gate heterojunction solar cell. For example, the gate line pull-off force of the copper-gate experimental group 2 is 0.9N greater than that of the copper-gate control group. At the same time, the cell efficiency and FF are effectively improved, and the series resistance is effectively reduced.

[0051] Table (1) is a comparison of the experimental data of the copper-gate heterojunction solar cell prepared by the above method and the ordinary copper-gate heterojunction solar cell In some embodiments, a heterojunction solar cell is also provided. The heterojunction solar cell is prepared by a preparation method of a selective electrode contact heterojunction cell prepared by any one of the above embodiments.

[0052] It can be understood that the beneficial effects of the technical solution of this embodiment can be found in the relevant description of the corresponding beneficial effects of the selective electrode contact silicon heterojunction solar cell mentioned above, and will not be repeated here.

[0053] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the invention.

[0054] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0055] Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Mentioning "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present embodiment application. The appearance of this phrase in various positions in the specification is not necessarily the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It can be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0056] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a selective electrode contact heterojunction battery, characterized in that: include: Step S10: the first texturing of the silicon wafer substrate, placing the silicon wafer substrate in a first texturing mixed solution, so that small textured pyramid structures are generated on both sides of the silicon wafer substrate, wherein the size of the pyramid structures is between 0.5um and 4um; Step S20: preparing a mask layer of a silicon wafer, depositing a first mask layer for a second texturing on both sides of the silicon wafer after the first texturing, wherein the first mask layer has a thickness of 50nm-250nm and a refractive index between 1.5-2.6; Step S30: the first patterning process of the silicon wafer, using picosecond laser to perform groove processing on both sides of the silicon wafer according to the positions of the electrode gate lines, wherein the depth of the groove is completely ablated to expose the surface of the silicon wafer substrate; Step S40: Second texturing of the silicon wafer, pre-cleaning the grooved silicon wafer, placing the cleaned silicon wafer in a second texturing mixture, so that a large textured pyramid structure is formed on the bottom surface of the double-sided groove of the silicon wafer, wherein the size of the pyramid structure is between 4um and 10um; Step S50: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, a TCO layer and an electroplating seed layer on both sides of the silicon wafer; Step S60: performing a second patterning process on the silicon wafer, and printing a second mask layer on other regions of the silicon wafer where the grooves are opened in the first patterning process based on exposure and development, wherein the second mask layer is an ink mask layer; Step S70: electroplating copper gate lines on the silicon wafer, and removing the second mask layer and the copper seed layer from the silicon wafer after the gate line electroplating in sequence to obtain a selective electrode contact copper gate line heterojunction solar cell.

2. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S10, the first texturing mixture is composed of at least an alkaline solution, a small texturing additive and ultrapure water, and the alkaline solution includes a combination of one or more of potassium hydroxide solution and sodium hydroxide solution.

3. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S20, the first mask layer includes a silicon nitride film, a silicon oxide film, and a silicon oxynitride film, or a combination of one or more of the following.

4. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S30, the mask layers on the front and back sides of the silicon wafer are grooved according to the positions of preset electrode grid lines based on a picosecond laser, wherein the wavelength range of the picosecond laser is 325nm-532nm, the front main gate groove width range is 50um-80um, the front auxiliary gate groove width range is 10um-40um, the back main gate groove width range is 50um-250um, and the back auxiliary gate groove width range is 20-80um.

5. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In step S40, a potassium hydroxide solution is used to clean the laser damaged layer at the grooved positions on the front and back sides of the silicon wafer, and the cleaned silicon wafer is placed in a second texturing mixture for texturing, wherein the second texturing mixture is composed of at least an alkaline solution, a special additive for large texturing surfaces and ultrapure water, and the alkaline solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions.

6. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S50, it includes: Step S51: depositing on both sides of the silicon wafer after secondary texturing, the thickness of the intrinsic amorphous silicon layer is in the range of 4nm-10nm; Step S52: Depositing emitter layers on the surfaces of the intrinsic amorphous silicon layer on both sides of the silicon wafer, wherein the emitter layer is one of a doped amorphous silicon layer and a nanocrystalline silicon layer; Step S53: sputtering a high-transmittance TCO layer on the emitter layer surface on both sides of the silicon wafer; Step S54: depositing a seed layer on the surface of the TCO layer on both sides of the silicon wafer, wherein the thickness of the seed layer is in the range of 10 nm to 150 nm.

7. The method for preparing a selective electrode contact heterojunction battery according to claim 6, characterized in that: In the step S52, it specifically includes: Depositing a phosphorus-doped amorphous silicon or a phosphorus-doped nanocrystalline silicon layer on the surface of the intrinsic amorphous silicon layer on the light-receiving surface of the silicon wafer to form a front emitter, wherein the phosphorus-doped amorphous silicon or phosphorus-doped nanocrystalline silicon layer has a thickness ranging from 5nm to 40nm; A boron-doped amorphous silicon or boron-doped nanocrystalline silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the backlight side of the silicon wafer to form a back emitter, wherein the boron-doped amorphous silicon or boron-doped nanocrystalline silicon layer has a thickness of 5nm-60nm.

8. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S70, it also includes: Soaking the electroplated silicon wafer in an alkaline mixed solution to remove the second mask layer, wherein the alkaline mixed solution includes a combination of one or more potassium hydroxide solutions or sodium hydroxide solutions, and the soaking time ranges from 30s to 200s; The silicon wafer with the mask removed is immersed in an acidic mixed solution to remove the copper seed layer other than the copper grid line, wherein the acidic mixed solution includes a combination of one or more of dilute sulfuric acid solution or dilute nitric acid solution.

9. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: When the battery electrode is a silver grid line, the step S40 includes: Step S51: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer and a TCO layer on both sides of the silicon wafer; Step S61: printing electrodes. According to the position of the first patterned groove, a corresponding screen is selected, and silver grid lines are printed on the front and back sides of the silicon wafer by screen printing. After curing, a selective electrode contact silver grid heterojunction solar cell is obtained.

10. A heterojunction solar cell, characterized in that: The heterojunction solar cell is prepared by the method for preparing a selective electrode contact heterojunction cell as claimed in any one of claims 1 to 9.

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