Method for manufacturing porous silicon structure
By designing high resistance value on the epitaxial layer and monitoring the lateral etch width of the protective layer, the problems of wafer warping and cracking in the manufacturing of porous silicon structures are solved, and the stability of etching depth and the productivity improvement are achieved.
Patent Information
- Application Number
- CN202311422756.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-13
- Filing Date
- 2023-10-31
- Publication Date
- 2025-03-14
AI Technical Summary
In the process of manufacturing porous silicon structures, the wafer is prone to warping and porous silicon structures are prone to cracks, and the etching depth is unstable, affecting the yield of production.
By designing the resistance value on the epitaxial layer to at least 10 times the substrate resistance value, and monitoring the side etch width of the protective layer during electrochemical etching, in order to calculate the etching depth of the porous silicon structure, decide whether to stop etching.
It effectively avoids wafer warping and cracks in porous silicon structures, ensures the correctness and stability of the etching depth of the porous silicon structures, and greatly improves the yield of production.
Smart Images
Figure CN119626897A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a porous silicon structure, in particular to a method for manufacturing a porous silicon structure capable of avoiding wafer warping and porous silicon cracks. Background Art
[0002] Porous silicon is a material commonly used in semiconductor manufacturing and microfabrication. It has excellent thermal insulation and lightweight properties, and is therefore widely used in various electronic components and devices. However, there are some technical problems in the process of manufacturing porous silicon structures, such as wafer warping and the formation of porous silicon cracks.
[0003] Electrochemical etching is one of the main steps in manufacturing porous silicon structures. However, etching too deep will cause the wafer to warp, which is caused by the uneven stress on the substrate during the etching process. In addition, insufficient etching depth will lead to poor thermal insulation of the porous silicon structure, which is caused by the inability to fully form the pore structure of the porous silicon.
[0004] In view of this, the present invention provides a method for manufacturing a porous silicon structure, which can ensure the accuracy and stability of the etching depth of the porous silicon structure, so as to greatly improve the production yield. Summary of the invention
[0005] The object of the present invention is to provide a method for manufacturing a porous silicon structure, which designs the resistance value of the epitaxial layer to be at least 10 times greater than the resistance value of the substrate, and monitors the side etching width of the protective layer during the electrochemical etching process to infer the etching depth of the porous silicon structure, and then decides whether to stop the electrochemical etching according to the etching depth of the porous silicon structure. Therefore, the accuracy and stability of the etching depth of the porous silicon structure can be guaranteed, which can not only avoid the wafer from warping and the porous silicon structure from cracking, but also greatly improve the production yield.
[0006] To achieve the above-mentioned purpose, the present invention discloses a method for manufacturing a porous silicon structure, comprising forming an epitaxial layer on a substrate; forming a protective layer on the epitaxial layer, the protective layer having an opening area; performing an electrochemical etching in the opening area to form a porous silicon structure in the epitaxial layer; and removing the protective layer.
[0007] In one embodiment, when performing the electrochemical etching, an etching rate at the epitaxial layer is greater than or equal to 10 times an etching rate at the substrate.
[0008] In one embodiment, a resistance value of the epitaxial layer is greater than or equal to 10 times a resistance value of the substrate.
[0009] In one embodiment, a thickness of the epitaxial layer is between 20 μm and 80 μm.
[0010] In one embodiment, the substrate is a silicon substrate.
[0011] In one embodiment, the epitaxial layer is a P-type doped epitaxial layer.
[0012] In one embodiment, a thickness of the protection layer is between 200 nm and 500 nm.
[0013] In one embodiment, the electrochemical etching is an anodic etching of the epitaxial layer using an etching solution made of hydrofluoric acid (HF) and ethanol (C2H5OH).
[0014] In one embodiment, the epitaxial layer has a porous silicon region and a non-porous silicon region, and a thickness of the porous silicon region is the same as a thickness of the epitaxial layer.
[0015] After referring to the accompanying drawings and the embodiments described below, a person skilled in the art will be able to understand other objects of the present invention, as well as the technical means and embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a cross-sectional view of the wafer of the present invention before etching;
[0017] Figure 2 is a cross-sectional view of the wafer after etching of the present invention; and
[0018] Figure 3 It is a cross-sectional view of the wafer after etching and removing the protective layer of the present invention.
[0019] Description of Reference Numerals
[0020] 100: Substrate
[0021] 200: Epitaxial layer
[0022] 210: Porous silicon region
[0023] 230: Non-porous silicon area
[0024] 300: Protective layer
[0025] 310: Opening area
[0026] 400: Porous silicon structure
[0027] D1: Initial width
[0028] D2: Width after etching
[0029] D3: Side erosion width
[0030] D4: Etching depth
[0031] D5: Width of the porous silicon structure. DETAILED DESCRIPTION
[0032] The present invention will be explained below by way of examples, and the examples of the present invention are not intended to limit the present invention to any specific environment, application or special method as described in the examples. Therefore, the description of the examples is only for the purpose of explaining the present invention, and is not intended to limit the present invention. It should be noted that in the following examples and drawings, elements that are not directly related to the present invention have been omitted and are not shown, and the dimensional relationship between the elements in the drawings is only for easy understanding, and is not intended to limit the actual proportion.
[0033] Please refer to Figures 1 to 3 , which respectively depicts the process of manufacturing a porous silicon (PS) structure at different stages. First, an epitaxial layer 200 is formed on a substrate 100, and a protective layer 300 is formed on the epitaxial layer 200. The substrate 100 is a silicon substrate, and the epitaxial layer 200 is a P-type doped epitaxial layer.
[0034] In the present invention, in order to prevent the wafer from warping and the porous silicon structure from cracking, a resistance value of the epitaxial layer 200 must be greater than or equal to 10 times a resistance value of the substrate 100. In addition, a thickness of the epitaxial layer 200 must be between 20 micrometers (μm) and 80 μm, while a thickness of the substrate 100 is generally greater than or equal to 500 μm.
[0035] In other embodiments, the optimal resistance value of the epitaxial layer 200 is 10 to 15 times the resistance value of the substrate 100. In addition, the optimal thickness of the epitaxial layer 200 is between 40 micrometers and 50 micrometers.
[0036] The thickness of the protective layer 300 is generally between 200 nanometers (nm) and 500 nanometers. The protective layer 300 has an opening area 310. An electrochemical etching is performed in the opening area 310 to form a porous silicon structure 400 on the epitaxial layer 200. An initial width D1 of the opening area 310 is the same as the width D5 of the porous silicon structure 400. The electrochemical etching is an anodic etching of the epitaxial layer 200 using an etching solution made of hydrofluoric acid (HF) and ethanol (C2H5OH).
[0037] Please also refer to Figure 1 and Figure 2The material of the protective layer 300 can be a silicon nitride dielectric layer. During the electrochemical etching process, the protective layer 300 will retreat to both sides, so it is necessary to monitor the retreat distance of the protective layer 300, and infer the etching depth of the porous silicon structure from the side etching width of the protective layer 300. The side etching width D3 of the protective layer 300 is equal to the etching depth D4 of the porous silicon structure. When the side etching width D3 reaches the required etching depth D4, the etching is stopped immediately to ensure the accuracy and stability of the etching depth of the porous silicon structure 400.
[0038] In one embodiment, the etching depth D4 of the porous silicon structure 400 is the same as a thickness of the epitaxial layer 200. Specifically, the epitaxial layer 200 has a porous silicon region 210 and a non-porous silicon region 230. The porous silicon structure 400 is located in the porous silicon region, and the thickness of the porous silicon region is the same as the thickness of the epitaxial layer.
[0039] Since the protective layer 300 retreats during the electrochemical etching process, the post-etching width D2 of the opening area 310 is wider than the initial width D1 of the opening area 310. In addition, when the electrochemical etching is performed, an etching speed at the epitaxial layer 200 is greater than or equal to 10 times an etching speed at the substrate 100. In other words, when the electrochemical etching reaches the position of the substrate 100, the etching speed becomes slow, which has a stopping effect.
[0040] Finally, after the electrochemical etching is completed, the protection layer 300 is removed to obtain a wafer having a porous silicon structure 200 .
[0041] In summary, the porous silicon structure manufacturing method of the present invention is designed to design the resistance value of the P-type doped epitaxial layer to be at least 10 times greater than the resistance value of the P-type silicon substrate, and a silicon nitride dielectric layer is set on the P-type doped epitaxial layer as a protective layer. The protective layer has an open area, which is an area for electrochemical etching. The side etching width of the protective layer is monitored during the electrochemical etching process to infer the etching depth of the porous silicon structure, and then decide whether to stop the electrochemical etching according to the etching depth of the porous silicon structure. Therefore, the accuracy and stability of the etching depth of the porous silicon structure can be guaranteed, which can not only avoid the warping of the wafer and the cracks in the porous silicon structure, but also greatly improve the production yield.
[0042] The above embodiments are only used to illustrate the implementation methods of the present invention and to explain the technical features of the present invention, and are not used to limit the protection scope of the present invention. Any changes or equivalent arrangements that can be easily completed by a person skilled in the art belong to the scope claimed by the present invention, and the scope of protection of the present invention shall be subject to the attached claims.
Claims
1. A method for manufacturing a porous silicon structure, comprising: forming an epitaxial layer on a substrate; forming a protective layer on the epitaxial layer, wherein the protective layer has an opening area; Performing an electrochemical etching in the opening area to form a porous silicon structure in the epitaxial layer; and Remove the protective layer.
2. The method for manufacturing a porous silicon structure according to claim 1, wherein: When the electrochemical etching is performed, an etching rate at the epitaxial layer is greater than or equal to 10 times an etching rate at the substrate.
3. The method for manufacturing a porous silicon structure according to claim 1, wherein: A resistance value of the epitaxial layer is greater than or equal to 10 times a resistance value of the substrate.
4. The method for manufacturing a porous silicon structure according to claim 1, wherein: The epitaxial layer has a thickness ranging from 20 micrometers to 80 micrometers.
5. The method for manufacturing a porous silicon structure according to claim 1, wherein: The substrate is a silicon substrate.
6. The method for manufacturing a porous silicon structure according to claim 1, wherein: The epitaxial layer is a P-type doped epitaxial layer.
7. The method for manufacturing a porous silicon structure according to claim 1, wherein: A thickness of the protective layer is between 200 nanometers and 500 nanometers.
8. The method for manufacturing a porous silicon structure according to claim 1, wherein: The electrochemical etching is to perform an anodic etching on the epitaxial layer using an etching solution made of hydrofluoric acid and ethanol.
9. The method for manufacturing a porous silicon structure according to claim 1, wherein: The epitaxial layer has a porous silicon region and a non-porous silicon region. The thickness of the porous silicon region is the same as that of the epitaxial layer.