High-temperature-resistant successive approximation analog-to-digital converter

Abstract

The invention provides a high-temperature-resistant successive approximation type analog-to-digital converter which can be applied to the technical field of analog-to-digital conversion. The analog-to-digital converter comprises a capacitor DAC module used for sampling an analog signal; the comparator module is used for comparing the signals output by the capacitor DAC module and outputting a comparison result; the time sequence and control unit module is used for generating a clock signal and a time sequence control signal; the voltage reference module is used for providing reference voltage for the interior of the chip; the successive approximation register module is used for successive approximation of a true value of an analog input signal and converting the true value into a digital parallel signal to be output; the output buffer module is used for buffering the parallel signals and outputting serial data; and the temperature zone regulation and control module is used for keeping the temperature zone regulation and control module relatively stable at different temperatures by regulating bias voltage signals of the comparator module and the voltage reference module. A serial output mode is adopted for data output, and the efficiency and reliability of data transmission are optimized through the sequential control module.

Description

Technical Field

[0001] The present disclosure relates to the technical field of analog-to-digital conversion, and in particular to a high-temperature resistant successive approximation analog-to-digital converter. Background Art

[0002] As the core of high-precision microelectronic systems, high-performance analog-to-digital converters (ADCs) are crucial to the reliability of electronic systems, high-precision equipment, and communication networks. With the expansion of VLSI into extreme environments such as petrochemicals, aerospace, and automotive electronics, there is an urgent need for ADC modules that can work stably under harsh conditions such as high temperatures. As the temperature rises, existing bulk silicon process ADCs face problems such as a surge in leakage current, a drop in threshold voltage, a decrease in mobility, and latch-up effects, resulting in an operating temperature below 175°C. Traditional methods increase the operating temperature of bulk silicon process ADCs by extending signal transmission lines or adding complex cooling systems, but extending signal transmission lines will lead to reduced reliability and increased electromagnetic interference; adding complex cooling systems will increase system complexity, power consumption, and cost. Although silicon carbide (SiC) technology is resistant to high temperatures, it is difficult to commercialize it widely due to its high cost and complex process. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] In order to solve the problem of performance degradation and reduced reliability of traditional SAR ADC under high temperature conditions in the prior art, ensure that it can still maintain efficient and stable conversion performance under extreme temperature conditions, thereby broadening the application field of SAR ADC and improving the reliability and durability of the overall system, the embodiment of the present disclosure provides a high-temperature resistant successive approximation analog-to-digital converter, which effectively suppresses the surge of leakage current under high temperature, stabilizes the threshold voltage, and completely eliminates the adverse effects of the latch effect by using a silicon-on-insulator (SOI) manufacturing process to design the circuit; by controlling an external controllable logic signal, the internal temperature zone control module can be adjusted to achieve calibration within a wide temperature range and obtain good working performance; and the data output adopts a serial output mode, and the efficiency and reliability of data transmission are optimized through a timing control module; and the buffers of the input and output ports effectively reduce the interference of external noise on the ADC signal, further improving the anti-interference ability and signal quality of the ADC.

[0005] (II) Technical solution

[0006] In view of the above problems, an embodiment of the present disclosure provides a high temperature resistant successive approximation analog-to-digital converter.

[0007] According to the first aspect of the present disclosure, a high-temperature resistant successive approximation analog-to-digital converter is provided, comprising: a capacitor DAC module, comprising a sampling and holding circuit and a segmented capacitor array, wherein the sampling and holding circuit is used to sample an analog signal to obtain a sampling signal; a segmented capacitor array, comprising a 6-bit low-segment capacitor array, a 6-bit high-segment capacitor array and a bridge capacitor, wherein the low-segment capacitor array and the high-segment capacitor array are both composed of binary-coded capacitor arrays; a comparator module, used to compare the signal output by the capacitor DAC module and output the comparison result; a timing and control unit module, used to generate a clock signal and a timing control signal; a voltage reference module, connected to the capacitor DAC module, used to provide a reference voltage for the inside of the chip; a successive approximation register module, connected to the timing and control unit module, the capacitor DAC module and the comparator module, used to control the binary search algorithm in the conversion process, gradually approximate the true value of the analog input signal, and convert it into a digital parallel signal output; and an output buffer module, which buffers the parallel signal output by the successive approximation register module and outputs serial data through a serial port.

[0008] In some exemplary embodiments, it also includes: a temperature zone control module, which is connected to the comparator module and the voltage reference module, selects resistors of different resistance values ​​through externally selected input signals, adjusts the bias current output by the temperature zone control module, and realizes current calibration within a wide temperature range. At the same time, the bias voltage signals of the comparator module and the voltage reference module are adjusted to keep them relatively stable at different temperatures.

[0009] In some exemplary embodiments, the timing and control unit module includes: a clock generation module, which is used to select the external clock signal or enable the internal clock signal according to the external clock selection signal, and output the selected clock signal, wherein the selected clock signal serves as a reference for the synchronous operation of various modules of the circuit; a control signal generation module, which works closely with the clock signal to ensure the timing of other functional modules is accurate, thereby achieving coordinated operation of the entire system.

[0010] In some exemplary embodiments, the control signal generation module includes: a state control logic module for generating a key logic control signal; and a clock control logic module for dividing the clock signal selected by the clock generation module and generating a clock flag.

[0011] In some exemplary embodiments, the temperature zone control module includes a decoder, a startup circuit, and a reference circuit; the externally selected input signal received by the temperature zone control module includes: RSEL <1> 、RSEL <0> ;RSEL <1> and RSEL <0> The decoder is connected to select resistors of different resistance values ​​to adjust the bias voltage generated in the reference circuit to suppress the influence caused by temperature drift; and the bias voltage generated by the reference circuit is directly connected to the comparator.

[0012] In some exemplary embodiments, the input signal of the control logic received by the state control logic module includes: a chip enable signal, a chip select signal, and a data conversion control signal.

[0013] In some exemplary embodiments, the input signal of the control logic received by the clock control logic module includes: a chip input clock signal and a clock gating signal.

[0014] In some exemplary embodiments, a high temperature resistant successive approximation analog-to-digital converter is designed using a silicon-on-insulator manufacturing process.

[0015] In some exemplary embodiments, the digital parallel signal obtained during the conversion process of the successive approximation register module is fed back to the capacitor DAC module in real time to serve as a reference for the comparison operation of the comparator module.

[0016] In some exemplary embodiments, the input signal of the output buffer module includes an externally supplied serial clock signal to ensure that the serial data can be output correctly and orderly; and the input signal of the output buffer module also includes an output enable signal of the timing and control unit module, and the output enable signal is used to control whether the serial data can be output.

[0017] In some exemplary embodiments, the analog-to-digital converter logic operation process includes activation preparation: setting the chip enable signal to a high level state, and maintaining the chip select signal at a low level state to activate the chip to prepare to receive instructions; triggering sampling: triggering the analog-to-digital converter to start the sampling process through the falling edge of the reset or data conversion control signal; data conversion: the status signal remains at a low level, indicating that the data is not ready; after the analog-to-digital converter starts data conversion, the status signal switches to a high level state; the status signal changes from a high level state to a low level state, indicating that the data conversion is completed and the current output data is ready, and the serial data can be read through the serial interface; continuous processing, applying the falling edge of the data conversion control signal again, connecting to the next data conversion cycle, to achieve continuous data acquisition and processing flow, wherein, when the data conversion control signal is in a low level state, the data output terminal is in a high impedance state to ensure the accuracy of data transmission and the stability of the circuit; and after triggering sampling and before the data conversion is completed, the data conversion control signal returns to a high level state to avoid re-triggering.

[0018] (III) Beneficial effects

[0019] It can be seen from the above technical solutions that the high temperature resistant successive approximation analog-to-digital converter provided by the embodiments of the present disclosure has at least one of the following beneficial effects:

[0020] (1) By designing the circuit using the silicon-on-insulator (SOI) manufacturing process, the surge in leakage current at high temperatures is effectively suppressed, the threshold voltage is stabilized, and the adverse effects of the latch-up effect are completely eliminated, ensuring that the ADC can operate stably in a wide temperature range of -50°C to 250°C.

[0021] (2) By controlling the external controllable logic signal, the internal temperature zone control module can be adjusted to achieve calibration within a wide temperature range and obtain good working performance.

[0022] (3) Data output adopts serial output mode, and the efficiency and reliability of data transmission are optimized through the timing control module.

[0023] (4) The buffers at the input and output ports effectively reduce the interference of external noise on the ADC signal, further improving the ADC's anti-interference capability and signal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram of the structure of a high temperature resistant successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown;

[0026] Figure 2 The schematic diagram of the operating mechanism principle of the temperature zone control module according to the embodiment of the present disclosure is schematically shown;

[0027] Figure 3 A schematic diagram showing the working principle of the core circuit of the temperature zone control module according to an embodiment of the present disclosure is shown;

[0028] Figure 4 A diagram schematically shows a simulation result of a temperature calibration technology based on a resistance control mechanism in the full operating temperature range according to an embodiment of the present disclosure;

[0029] Figure 5 Schematically shows a timing diagram of an ADC output signal according to an embodiment of the present disclosure;

[0030] Figure 6 Schematically shows a specific output timing diagram of 12-bit serial data according to an embodiment of the present disclosure; and

[0031] Figure 7 The diagram schematically shows the spectrum of the output signal simulated at 200° C. of the ADC according to the embodiment of the present disclosure and the dynamic performance indicators such as the signal-to-noise ratio (SNR) and the effective number of bits (ENOB) obtained by calculation. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0033] Silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) technology relies on SiO 2 The insulating layer isolates the transistor from the substrate, effectively suppresses high-temperature leakage current, stabilizes the threshold voltage, and eliminates the latch-up effect, making it the preferred solution for high-temperature ADC design. Given that the high-temperature resistant successive approximation analog-to-digital converter (SAR ADC) meets the performance requirements of most circuits with its high sampling rate and resolution, designing a high-temperature resistant, high-precision, low-power SAR ADC chip has become a technical challenge, and the introduction of SOI CMOS technology provides an innovative solution to this problem, showing great application potential.

[0034] Figure 1 The schematic diagram shows the structure of a high temperature resistant successive approximation analog-to-digital converter according to an embodiment of the present disclosure.

[0035] like Figure 1As shown, a high temperature resistant successive approximation analog-to-digital converter according to an embodiment of the present disclosure includes: a capacitor DAC module, including a sampling and holding circuit and a segmented capacitor array, wherein the sampling and holding circuit is used to sample an analog signal to obtain a sampling signal; the segmented capacitor array includes a 6-bit low-segment capacitor array, a 6-bit high-segment capacitor array and a bridge capacitor, and the low-segment capacitor array and the high-segment capacitor array are both composed of binary-coded capacitor arrays; a comparator module, used to compare the signal output by the capacitor DAC module and output a comparison result; a timing and control unit module, used to generate a clock signal and a timing control signal; a voltage reference module, connected to the capacitor DAC module, used to provide a reference signal for the chip. A reference voltage is provided, and optionally, the reference voltage is 2.5V; a successive approximation register module is connected to the timing and control unit module, the capacitor DAC module and the comparator module, and is used to control the binary search algorithm in the conversion process, gradually approach the true value of the analog input signal, and convert it into a digital parallel signal output. The digital parallel signal obtained during the conversion process of the successive approximation register module is fed back to the capacitor DAC module in real time as a reference for the comparison operation of the comparator module, thereby forming a closed-loop, self-calibrated conversion mechanism to ensure high precision and stability of the conversion result; an output buffer module buffers the parallel signal output by the successive approximation register module, and outputs serial data through the serial port.

[0036] In some exemplary embodiments, the high temperature resistant successive approximation analog-to-digital converter uses a silicon on insulator (SOI) manufacturing process to design the circuit. The SOI manufacturing process is used to design the circuit, thereby effectively suppressing the surge of leakage current at high temperature, stabilizing the threshold voltage, and completely eliminating the adverse effects of the latch effect.

[0037] In some exemplary embodiments, the timing and control unit module includes: a clock generation module, which is used to select the external clock signal or enable the internal clock signal according to the external clock selection signal (CLKSEL), and output the selected clock signal, wherein the selected clock signal is used as the reference for the synchronous operation of each module of the circuit; a control signal generation module, which closely cooperates with the clock signal to ensure the timing of other functional modules is accurate, so as to achieve the coordinated operation of the whole system. Optionally, the control signal generation module includes: a state control logic module, which is used to generate a key logic control signal (STS); and a clock control logic module, which is used to divide the clock signal selected by the clock generation module and generate a clock flag.

[0038] In some exemplary embodiments, the input signals of the control logic received by the state control logic module include: a chip enable signal (Chip Enable, CE), a chip select signal (Not chip select, NCS) and a data conversion control signal (Read / Not Convert, RNC); and / or the input signals of the control logic received by the clock control logic module include: a chip input clock signal (XCLKIN) and a clock selection signal (CLKSEL).

[0039] In some exemplary embodiments, the high temperature resistant successive approximation analog-to-digital converter also includes: a temperature zone control module, which is connected to the comparator module and the voltage reference module, selects resistors of different resistance values ​​through externally selected input signals, adjusts the bias current output by the temperature zone control module, and realizes current calibration within a wide temperature range, and at the same time adjusts the bias voltage signals of the comparator module and the voltage reference module to keep them relatively stable at different temperatures, thereby effectively avoiding performance degradation or failure problems caused by temperature fluctuations. Thanks to this, the ADC can maintain a normal and stable working state within a wide temperature range.

[0040] In order to help more clearly understand the technical content of the embodiments of the present disclosure, the functions of the above signals are explained in detail below.

[0041] Chip enable signal CE, when input high level will enable the chip and enable the output, low level will disable the chip and put the output in a high impedance state.

[0042] The chip select signal NCS, when input low level will select the chip and enable the output, high level will deselect the chip and put the output into a high impedance state.

[0043] The data conversion control signal RNC starts the conversion of analog signals to digital signals when it changes from high level to low level. When it remains at low level, the output is in high impedance mode.

[0044] The status output signal STS, when outputting a low level, indicates that the conversion is completed and the data is available at the output end, and when outputting a high level, indicates that the conversion is in progress.

[0045] The chip input clock signal XCLKIN is used to provide a clock signal to the chip when an external clock signal is selected.

[0046] The clock selection signal CLKSEL, when the input is high level, the clock generation module selects to access the external clock signal, and when the input is low level, the internal clock signal is enabled.

[0047] In the disclosed embodiment, the output buffer module requires an external serial clock signal (SCLK) to ensure that the serial data (SDOUT) can be output correctly and orderly; in addition, the module also receives an output enable signal (EN) from the timing and control unit module. This enable signal, as a key control condition, directly determines whether SDOUT can be allowed to be output normally.

[0048] Preferably, SCLK needs to provide at least 12 pulse cycle signals in one data output (it works when STS is at a low level). When the XCLKIN frequency is 4MHz and the sampling frequency is 50KSPS, the recommended SCLK frequency is 1.6MHz.

[0049] In order to ensure that all serial 12-bit data can be correctly output, the relationship between the serial clock frequency and the sampling frequency should be as follows:

[0050] f SCLK ≥32f sample (1)

[0051] In the formula, f SCLK is the serial clock frequency, f sample is the sampling frequency, and the formula requires that there are at least 32 serial clock cycles in one sampling. Since the conversion time is much smaller than the output data time, it can ensure that all serial 12-bit data are output within the output data time period with a time margin.

[0052] Figure 2 The schematic diagram shows the operating mechanism principle diagram of the temperature zone control module provided according to the embodiment of the present disclosure.

[0053] like Figure 2 As shown, according to the embodiment of the present disclosure, the temperature zone control module includes a decoder, a start-up circuit and a reference circuit. Optionally, the decoder includes a 2-4 decoder; the externally selected input signal received by the temperature zone control module includes: RSEL <1> 、RSEL <0> .

[0054] The temperature zone control module is controlled by the signal RSEL <1> 、RSEL <0> Signal control, RSEL <1> and RSEL <0> Connect the decoder to select resistors of different resistance values ​​to adjust the bias voltage generated in the reference circuit, stabilize the bias voltage at different temperatures to restrain the influence of temperature drift; and the bias voltage generated by the reference circuit is directly connected to the comparator. RSEL <1> 、RSEL <0> The specific temperature ranges corresponding to different values ​​are shown in Table 1.

[0055] Table 1 Temperature range corresponding to different values ​​of input signal selection

[0056]

[0057] As can be seen from Table 1, by controlling the externally selected input signal, the internal temperature zone control module is adjusted, and further, calibration is achieved in a wide temperature range from -50°C to 250°C, obtaining good working performance.

[0058] Figure 3 The schematic diagram schematically shows the working principle of the core circuit of the temperature zone control module according to the embodiment of the present disclosure.

[0059] like Figure 3 As shown, the core circuit of the temperature zone control module according to the embodiment of the present disclosure is an optional resistor R in the dotted box. By adjusting the resistor R, the output current at different temperatures can be controlled. Figure 3 Detailed description of the temperature calibration process by changing the resistor value.

[0060] M 1 With M 2 The substrate voltage of the tube is V B Equal to V 3 The voltage at point 3 The tube is a diode connection, with V 3 =V TH3 .

[0061] Because M 1 With M 2 The source voltage of the tube is V 1 =V 2 =V OV4,5 , where V OV4,5 M 4 、M 5 The overdrive voltage of the tube. Therefore, V SB1 =V SB2 = V TH3 -V OV4,5 .

[0062] V TH3 With V OV4,5 The change trend with temperature is the same, which can ensure that V SB1 With V SB2 It basically does not change with the change of temperature, thus greatly weakening M 1 With M 2 The body effect of the tube provides a more stable guarantee for the current reference it generates.

[0063] In addition, affected by M 1 The influence of diode connection, V RP -V 1 The voltage is V TH1 . Since V 1 =V 2 , with VRP -V 2 = V TH1 , V RN -V 2 = V OV2 , we can get M 2 The drain current I 2 =(V RP -V RN ) / R=( V TH1 -V OV2 ) / R.

[0064] The calculation results are:

[0065] (2)

[0066] It can be seen that changing the value of the resistor R can adjust the reference current I 2 The value of the bandgap reference current is then calibrated to change with temperature.

[0067] Ensuring the stability of the bandgap reference output current can ensure that the bias current of the voltage comparator remains stable as the temperature changes, thereby ensuring that its bandwidth is large enough. Therefore, the speed of the comparator will not decrease as the temperature rises, ensuring the operating speed of the comparator in a high temperature environment.

[0068] Figure 4 The diagram schematically shows the simulation results of the temperature calibration technology based on the resistance control mechanism in the full operating temperature range according to the embodiment of the present disclosure.

[0069] like Figure 4 As shown, the horizontal axis represents the simulation temperature range, which is finely divided into four temperature intervals from -50°C to 250°C to fully cover a wide range of working environments; the vertical axis corresponds to the bias current value output by the temperature zone control module, which will subsequently be converted into a bias voltage for precise adjustment.

[0070] By using the gate resistor technology, the disclosed embodiment can effectively calibrate the reference voltage under different temperature conditions, thereby significantly enhancing the output stability and reliability of the ADC in extreme or harsh working environments, and demonstrating an innovative temperature compensation strategy.

[0071] Figure 5 The figure schematically shows a timing diagram of an ADC output signal according to an embodiment of the present disclosure.

[0072] When describing the operating logic of a chip, we need to ensure that the interactions and conditional triggers between the various signals have a clear logical order and causal relationship. The following is a reorganization and optimization of the given information to enhance its logic.

[0073] First, clarify the basic operating premise of the chip:

[0074] When CE is high, the chip is in an active state, allowing further operations.

[0075] When NCS is low, the chip is selected to ensure that the operation is performed only on the current chip.

[0076] Next, the role of the data conversion control signal RNC and its relationship with ADC sampling are explained:

[0077] When the RNC signal is triggered (i.e. pulled low), the ADC circuit starts sampling and then outputs the converted data under the conditions of CE high and NCS low. After the conversion is completed, STS goes low, indicating that the output data is now available and can be read.

[0078] Let's explain the behavior control of the output signal:

[0079] The 12-bit serial output signal will enter a high impedance state (high impedance state) under three circumstances: one is when the CE signal is low, that is, when the chip is not activated; the second is when the RNC signal is high and is not currently in the data output stage (that is, during the period of waiting to read data after non-sampling); the third is during the conversion process, when STS is high.

[0080] Therefore, to trigger the next data conversion, just pull the RNC signal low again, provided that CE remains high and NCS remains low. This ensures that the chip can continue to respond to conversion requests and perform a new sampling and conversion process after each RNC falling edge.

[0081] The logic operation flow of the chip follows the following precise and standardized steps to ensure efficient and stable data conversion and output. During chip operation, first ensure that CE is in a high state and NCS is maintained at a low level to activate the chip to receive instructions. Subsequently, the ADC is triggered by the falling edge of reset or RNC to start the sampling process. After this triggering action, RNC needs to return to a high state before the ADC completes the conversion to avoid accidental re-triggering.

[0082] During the conversion, the status signal (STS) remains low, indicating that the data is not ready yet. Once the ADC completes the data conversion, STS will quickly switch to a high state, marking the beginning of the data conversion cycle, which is the core period of ADC data processing. Subsequently, when STS changes from high to low, it clearly indicates that the conversion is complete and the current output data is ready to be read through the 12-bit serial interface SDOUT.

[0083] After completing the above steps, the falling edge of RNC can be applied again to seamlessly connect to the next data conversion cycle, realizing a continuous and efficient data acquisition and processing process. Importantly, when RNC is in a low level state, the data output end will be in a high impedance state, ensuring the accuracy of data transmission and the stability of the circuit.

[0084] Among them, T1 represents the reaction time from RNC pulling low to STS pulling high; T2 represents the time RNC keeps low; T3 represents the ADC conversion time; T4 represents the reaction time from the output data being valid to STS pulling low, after STS pulls low, the serial data output officially starts; T5 represents the reaction time from RNC pulling low to starting the next analog-to-digital conversion to the output high-impedance state.

[0085] Figure 6 The specific output timing diagram of 12-bit serial data according to an embodiment of the present disclosure is schematically shown.

[0086] like Figure 6 As shown, in order to restore the 12-bit serial data output by the ADC to 12-bit parallel data and facilitate subsequent data processing, the timing of the three signals STS, SCLK, and SDOUT must be clarified.

[0087] At the end of the conversion cycle (slightly before the STS signal is pulled low), SDOUT immediately generates valid output data. The data is output MSB first and changes the data position at each falling edge of SCLK until the last data bit.

[0088] After outputting 12 bits of serial data, due to the existence of the SCLK signal and the RNC signal not being pulled low to trigger the next data conversion, SDOUT still has output, but the output is logic zero.

[0089] The output signal does not change from output logic zero to high impedance until the RNC signal is pulled low to trigger the next data conversion.

[0090] Among them, T6 represents the reaction time from when the output data is valid to when STS is pulled low; T7 represents the time from when STS is pulled low to when the first SCLK clock signal rises.

[0091] Figure 7 The diagram schematically shows the spectrum of the output signal simulated at 200° C. of the ADC according to the embodiment of the present disclosure and the dynamic performance indicators such as the signal-to-noise ratio (SNR) and the effective number of bits (ENOB) obtained by calculation.

[0092] like Figure 7 As shown, the signal-to-noise ratio of the output signal obtained by simulating the ADC according to the embodiment of the present disclosure at 200° C. is about 68.2 dB, and the effective number of bits is about 11.0 bits.

[0093] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A high temperature resistant successive approximation analog-to-digital converter, characterized in that: include: A capacitor DAC module, comprising a sampling and holding circuit and a segmented capacitor array, wherein the sampling and holding circuit is used to sample an analog signal to obtain a sampling signal; the segmented capacitor array comprises a 6-bit low-segment capacitor array, a 6-bit high-segment capacitor array and a bridge capacitor, wherein the low-segment capacitor array and the high-segment capacitor array are both composed of binary-coded capacitor arrays; A comparator module, used for comparing the signal output by the capacitor DAC module and outputting a comparison result; A timing and control unit module, used to generate clock signals and timing control signals; A voltage reference module, connected to the capacitor DAC module, for providing a reference voltage inside the chip; a successive approximation register module, connected to the timing and control unit module, the capacitor DAC module and the comparator module, for controlling the binary search algorithm in the conversion process, gradually approximating the true value of the analog input signal, and converting it into a digital parallel signal output; and The output buffer module buffers the parallel signal output by the successive approximation register module and outputs the serial data through the serial port.

2. The high temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that: Also includes: The temperature zone control module is connected to the comparator module and the voltage reference module. Through the externally selected input signal, resistors with different resistance values ​​are selected to adjust the bias current output by the temperature zone control module to achieve current calibration within a wide temperature range. At the same time, the bias voltage signals of the comparator module and the voltage reference module are adjusted to keep them relatively stable at different temperatures.

3. The high temperature resistant successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that: The timing and control unit module includes: A clock generation module, used for selecting to access an external clock signal or enable an internal clock signal according to an external clock selection signal, and outputting the selected clock signal, wherein the selected clock signal serves as a reference for synchronous operation of various modules of the circuit; The control signal generation module works closely with the clock signal to ensure the timing of other functional modules is accurate, thereby achieving coordinated operation of the entire system.

4. The high temperature resistant successive approximation analog-to-digital converter according to claim 3, characterized in that: The control signal generating module comprises: A state control logic module for generating key logic control signals; and The clock control logic module is used to divide the frequency of the clock signal selected by the clock generation module and generate a clock flag.

5. The high temperature resistant successive approximation analog-to-digital converter according to claim 2, characterized in that: The temperature zone control module includes a decoder, a start-up circuit and a reference circuit; The externally selected input signal received by the temperature zone control module includes: RSEL <1> 、RSEL <0> ; The RSEL <1> and the RSEL <0> Connecting the decoder to select resistors of different resistance values ​​to adjust the bias voltage generated in the reference circuit to suppress the influence caused by temperature drift; and The bias voltage generated by the reference circuit is directly connected to the comparator.

6. The high temperature resistant successive approximation analog-to-digital converter according to claim 4, characterized in that: The input signals of the control logic received by the state control logic module include: a chip enable signal, a chip select signal and a data conversion control signal; and / or The input signal of the control logic received by the clock control logic module includes: a chip input clock signal and a clock gating signal.

7. The high temperature resistant successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that: The high temperature resistant successive approximation analog-to-digital converter adopts a silicon on insulator manufacturing process to design a circuit.

8. The high temperature resistant successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that: The digital parallel signal obtained during the conversion process of the successive approximation register module is fed back to the capacitor DAC module in real time as a reference for the comparison operation of the comparator module.

9. The high temperature resistant successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that: The input signal of the output buffer module includes an externally supplied serial clock signal to ensure that the serial data can be output correctly and in order; and The input signal of the output buffer module also includes an output enable signal of the timing and control unit module, and the output enable signal is used to control whether the serial data can be output.

10. The high temperature resistant successive approximation analog-to-digital converter according to claim 1 or 2, characterized in that: The analog-to-digital converter logic operation process includes: Activation preparation: put the chip enable signal in a high level state, and keep the chip select signal in a low level state to activate the chip to prepare to receive instructions; Trigger sampling: Trigger the analog-to-digital converter to start the sampling process through the falling edge of the reset or data conversion control signal; Data conversion: The status signal remains at a low level, indicating that the data is not ready yet; after the analog-to-digital converter starts data conversion, the status signal switches to a high level state; the status signal changes from a high level state to a low level state, indicating that the data conversion is complete and the current output data is ready, and the serial data can be read through the serial interface; Continuous processing, apply the falling edge of the data conversion control signal again, connect to the next data conversion cycle, and realize continuous data collection and processing flow. When the data conversion control signal is in a low level state, the data output terminal is in a high impedance state to ensure the accuracy of data transmission and the stability of the circuit; and After the sampling is triggered and before the data conversion is completed, the data conversion control signal returns to the high state to avoid retriggering.

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