IGBT (Insulated Gate Bipolar Translator) defect positioning method and device based on gate current in turn-off process

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) defect positioning method and device based on gate current in a turn-off process. The method comprises the following steps: acquiring the total number of chips of a target IGBT, first normal gate current and first actual gate current in a gate voltage drop stage, and second normal gate current and second actual gate current in a Miller plateau stage; determining a first normal gate discharge charge quantity and a first actual gate discharge charge quantity in a gate voltage drop stage, and a second normal gate discharge charge quantity and a second actual gate discharge charge quantity in a Miller plateau stage; and completing internal defect positioning of the target IGBT according to the total number of the chips, the first normal gate discharge charge quantity, the first actual gate discharge charge quantity, the second normal gate discharge charge quantity and the second actual gate discharge charge quantity. According to the invention, the internal defects of the insulated gate bipolar transistor can be positioned, and the subsequent maintenance of the insulated gate bipolar transistor is facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of insulated gate bipolar transistors, and in particular to an IGBT defect location method and device based on gate current during a turn-off process. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) devices have the advantages of fast switching speed of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices and low conduction loss of bipolar devices. They have been widely used in new energy converters, flexible DC transmission equipment, dynamic reactive power compensation equipment and other occasions.

[0003] The existing insulated gate bipolar transistor defect detection method is single, for example, analyzing the defect situation through the gate discharge charge, which can partially reflect whether a defect has occurred inside the IGBT, but cannot locate the internal defects of the IGBT. Summary of the invention

[0004] In response to at least one problem in the prior art, the present application proposes an IGBT defect locating method and device based on the gate current during the shutdown process, which can locate internal defects of the insulated gate bipolar transistor and facilitate subsequent maintenance of the insulated gate bipolar transistor.

[0005] In order to solve the above technical problems, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides an IGBT defect location method based on gate current during a turn-off process, comprising:

[0007] Obtaining the total number of target IGBT chips, a first normal gate current in a gate voltage drop phase, a first actual gate current, a second normal gate current in a Miller platform phase, and a second actual gate current, wherein the shutdown process includes: the gate voltage drop phase and the Miller platform phase;

[0008] Determine a first normal gate discharge charge amount, a first actual gate discharge charge amount, a second normal gate discharge charge amount, and a second actual gate discharge charge amount in the Miller platform stage in the gate voltage falling stage according to the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current in the Miller platform stage in the gate voltage falling stage;

[0009] The internal defect positioning of the target IGBT is completed according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge.

[0010] In one embodiment, the internal defect location of the target IGBT is completed according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge, including:

[0011] Detecting whether the first normal gate discharge charge is greater than the first actual gate discharge charge, and if so, locating the internal defect of the target IGBT including a gate-emitter loop defect;

[0012] It is detected whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, the internal defect of the target IGBT is located, including a collector gate loop defect.

[0013] In one embodiment, after locating the internal defect of the target IGBT including the gate emitter loop defect, the method further includes:

[0014] The number of chips of the target IGBT having gate-emitter loop defects is determined according to the first normal gate discharge charge, the first actual gate discharge charge and the total number of chips.

[0015] In one embodiment, after locating the internal defect of the target IGBT including the collector gate loop defect, the method further includes:

[0016] The number of chips of the target IGBT having collector gate loop defects is determined according to the second normal gate discharge charge, the second actual gate discharge charge and the total number of chips.

[0017] In one embodiment, the IGBT defect location method based on the gate current during the shutdown process further includes:

[0018] If the internal defects of the target IGBT include a gate-emitter loop defect and a collector-gate loop defect, it is determined that the defect type of the target IGBT is a gate defect.

[0019] In one embodiment, the IGBT defect location method based on the gate current during the shutdown process further includes:

[0020] If the internal defect of the target IGBT includes a gate-emitter loop defect but does not include a collector-gate loop defect, it is determined that the defect type of the target IGBT is an emitter defect.

[0021] In one embodiment, the IGBT defect location method based on the gate current during the shutdown process further includes:

[0022] If the internal defect of the target IGBT includes a collector-gate loop defect but does not include a gate-emitter loop defect, it is determined that the defect type of the target IGBT is a collector defect.

[0023] In a second aspect, the present application provides an IGBT defect location device based on gate current during a turn-off process, comprising:

[0024] An acquisition module is used to acquire the total number of target IGBT chips, a first normal gate current in a gate voltage drop phase, a first actual gate current, a second normal gate current in a Miller platform phase, and a second actual gate current, wherein the shutdown process includes: the gate voltage drop phase and the Miller platform phase;

[0025] a charge amount determination module, configured to determine a first normal gate discharge charge amount in the gate voltage falling stage, a first actual gate discharge charge amount, a second normal gate discharge charge amount in the Miller platform stage, and a second actual gate discharge charge amount in the gate voltage falling stage according to the first normal gate current in the gate voltage falling stage, the first actual gate current, the second normal gate current in the Miller platform stage, and the second actual gate current;

[0026] The detection module is used to complete the internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge in the gate voltage drop stage, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform stage, and the second actual gate discharge charge.

[0027] In one embodiment, the detection module includes:

[0028] A first detection unit, configured to detect whether the first normal gate discharge charge is greater than the first actual gate discharge charge, and if so, locate the internal defect of the target IGBT including a gate-emitter loop defect;

[0029] The second detection unit is used to detect whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, the internal defect of the target IGBT is located, including a collector gate loop defect.

[0030] In one embodiment, the IGBT defect locating device based on the gate current during the turn-off process further includes:

[0031] The first chip quantity determination module is used to determine the number of chips of the target IGBT having gate-emitter loop defects according to the first normal gate discharge charge, the first actual gate discharge charge and the total number of chips.

[0032] In one embodiment, the IGBT defect locating device based on the gate current during the turn-off process further includes:

[0033] The second chip quantity determination module is used to determine the number of chips of the target IGBT having a collector gate loop defect according to the second normal gate discharge charge, the second actual gate discharge charge and the total number of chips.

[0034] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0035] The gate defect determination module is used to determine that the defect type of the target IGBT is a gate defect if the internal defect of the target IGBT includes a gate-emitter loop defect and a collector-gate loop defect.

[0036] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0037] The emitter defect determination module is used to determine that the defect type of the target IGBT is an emitter defect if the internal defect of the target IGBT includes a gate-emitter loop defect but does not include a collector-gate loop defect.

[0038] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0039] The collector defect determination module is used to determine that the defect type of the target IGBT is a collector defect if the internal defect of the target IGBT includes a collector-gate loop defect but does not include a gate-emitter loop defect.

[0040] In a third aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the IGBT defect location method based on the gate current during the shutdown process is implemented.

[0041] In a fourth aspect, the present application provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the IGBT defect locating method based on the gate current during the turn-off process.

[0042] It can be seen from the above technical solution that the present application provides an IGBT defect location method and device based on the gate current during the shutdown process. The method includes: obtaining the total number of chips of the target IGBT, the first normal gate current in the gate voltage drop phase, the first actual gate current, the second normal gate current in the Miller platform phase, and the second actual gate current, and the shutdown process includes: the gate voltage drop phase and the Miller platform phase; determining the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge according to the first normal gate current in the gate voltage drop phase, the first actual gate current, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge; completing the internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge, so as to realize the positioning of the internal defects of the insulated gate bipolar transistor, and the process is efficient and reliable, which is convenient for the subsequent maintenance of the insulated gate bipolar transistor; the IGBT defect state detection and positioning can be realized based on the gate current waveform of the shutdown delay process, and the gate current i of the IGBT device during the shutdown delay process can be observed. G Waveform analysis can determine whether a device has defects and locate the defect, which is of certain significance for IGBT status detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 It is a first flow chart of the IGBT defect location method based on the gate current during the turn-off process in an embodiment of the present application;

[0045] Figure 2 is a schematic diagram of the commutation circuit structure of the half-bridge circuit model in the embodiment of the present application;

[0046] Figure 3 is a schematic diagram of the internal structure of the IGBT in the embodiment of the present application;

[0047] Figure 4 Schematic diagram of the IGBT turn-off delay process in an embodiment of the present application;

[0048] Figure 5It is a second flow chart of the IGBT defect location method based on the gate current during the shutdown process in the embodiment of the present application;

[0049] Figure 6 1 is a first structural schematic diagram of an IGBT defect location device based on gate current during a turn-off process in an embodiment of the present application;

[0050] Figure 7 is a second structural schematic diagram of an IGBT defect locating device based on gate current during a turn-off process in an embodiment of the present application;

[0051] Figure 8 It is a schematic block diagram of the system structure of the electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] In order to solve the problems existing in the above-mentioned prior art, the embodiment of the present application provides an IGBT defect location method and device based on the gate current of the turn-off delay process during the turn-off delay process. By analyzing the gate current waveform of the turn-off delay process, the turn-off delay process is divided into the gate voltage drop stage and the Miller platform stage, and the response of the gate current waveform of each stage process to the collector, emitter, and gate defects is studied respectively. It is proposed that the gate current characteristics of the two stages of the turn-off delay process can be integrated to carry out defect location at different positions inside the IGBT, which can enhance the depth of understanding of the internal defects of the IGBT and has certain value for the performance detection of the IGBT device; by observing the gate current i of the IGBT device during the turn-off delay process, the gate current i of the IGBT device can be measured. G Waveform analysis can be used to determine whether a device has defects and locate the defect, which can improve the reliability and convenience of IGBT defect location.

[0054] The details are described through the following embodiments.

[0055] In order to locate the internal defects of the insulated gate bipolar transistor and facilitate the subsequent maintenance of the insulated gate bipolar transistor, this embodiment provides an IGBT defect location method based on the gate current of the shutdown process, in which the execution subject is an IGBT defect location device based on the gate current of the shutdown process. The IGBT defect location device based on the gate current of the shutdown process includes but is not limited to a server, such as Figure 1As shown, the method specifically includes the following contents:

[0056] Step 100: Obtain the total number of target IGBT chips, the first normal gate current in the gate voltage drop phase, the first actual gate current, the second normal gate current in the Miller platform phase, and the second actual gate current. The shutdown process includes: the gate voltage drop phase and the Miller platform phase.

[0057] Specifically, the first normal gate current may be the gate current of the target IGBT in a normal state during the gate voltage drop phase; the first actual gate current may be the actual gate current of the target IGBT during the gate voltage drop phase; the second normal gate current may be the gate current in a normal state during the Miller platform phase; the second actual gate current may be the actual gate current during the Miller platform phase. The shutdown process may include: a shutdown delay process, the gate voltage drop phase may be the gate voltage drop phase of the shutdown delay process, and the Miller platform phase may be the Miller platform phase of the shutdown delay process.

[0058] Step 200: Determine a first normal gate discharge charge in the gate voltage falling phase, a first actual gate discharge charge, a second normal gate discharge charge in the Miller platform phase, and a second actual gate discharge charge in the Miller platform phase according to the first normal gate current in the gate voltage falling phase, the first actual gate current, the second normal gate current in the Miller platform phase, and the second actual gate current.

[0059] Specifically, the gate current i G There is the following relationship between the gate discharge charge amount:

[0060]

[0061] Where n is the total number of chips, and Q is the gate discharge charge of a single chip. The gate current of the insulated gate bipolar transistor during the turn-off delay process can be measured to form a gate current waveform of the turn-off delay process. Combined with the relationship between the gate current and the gate discharge charge, the actual gate discharge charge during the gate voltage drop stage and the Miller platform stage of the turn-off delay process can be determined. The gate current waveform of the insulated gate bipolar transistor during the turn-off delay process under normal conditions can also be obtained. Combined with the relationship between the gate current and the gate discharge charge, the normal gate discharge charge during the gate voltage drop stage and the Miller platform stage of the turn-off delay process can be determined. It can be understood that, assuming i G is the first actual gate current, then the actual gate discharge charge of a single chip during the gate voltage drop phase can be Q, and the first actual gate discharge charge Q tA,fault It can be n×Q; assuming i Gis the first normal gate current, then the normal gate discharge charge of a single chip during the gate voltage drop phase can be Q, and the first normal gate discharge charge Q tA It can be n×Q; assuming i G is the second normal gate current, then the normal gate discharge charge of a single chip in the Miller platform stage can be Q, and the second normal gate discharge charge Q G It can be n×Q; assuming i G is the second actual gate current, then the actual gate discharge charge of a single chip in the Miller platform stage can be Q, and the second actual gate discharge charge Q G,fault It can be n×Q.

[0062] Specifically, Figure 2 is the commutation circuit structure of the half-bridge circuit model including IGBT, u GE is the gate voltage, u CE is the collector-emitter voltage, u chip,CE is the chip collector-emitter voltage, turn-off delay process u chip,CE =u CE ,u CG is the collector gate voltage. C is the collector current, L s,1 is the parasitic inductance of the IGBT circuit, u GE is the device gate voltage, the half-bridge circuit model should include the gate current i G Measurement points of key parameters such as Figure 2 The dotted line box 1 in the figure represents the IGBT, the dotted line 2 represents the collector gate loop, and the dotted line 3 represents the gate emitter loop. The reference direction of voltage and current is Figure 2 L s,F and L s,CE They represent the parasitic parameters of the main circuits inside the FWD device and the IGBT device respectively. s,F Including the parasitic inductance of the FWD anode and cathode sides, L s,CE Including L s,C , L s,E2 part.

[0063] Figure 3 is the internal circuit structure of IGBT, and n is the total number of chips. IGBT device packaging defects can be divided into three categories: gate defects, collector defects, and emitter defects; Figure 3 The mark ① indicates a gate defect. Figure 3 The mark ② indicates a collector defect. Figure 3 The mark ③ indicates an emitter defect. Figure 4 t 0 ~t 2 The stage is the turn-off delay process, which includes two stages: ① Gate voltage drop stage (t 0 ~t1 ) ② Gate voltage Miller platform stage (t 1 ~t 2 ), Figure 4 The gate current i G Waveform.

[0064] Step 300: completing internal defect location of the target IGBT according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge.

[0065] Specifically, the first normal gate discharge charge may be the gate discharge charge of the target IGBT in the gate voltage drop stage under normal conditions; the first actual gate discharge charge may be the actual gate discharge charge of the target IGBT in the gate voltage drop stage, and may be the gate discharge charge of the target IGBT after a defect occurs in the gate voltage drop stage. The second normal gate discharge charge may be the gate discharge charge of the target IGBT in the Miller platform stage under normal conditions; the second actual gate discharge charge may be the actual gate discharge charge of the target IGBT in the Miller platform stage, and may be the gate discharge charge of the target IGBT after a defect occurs in the Miller platform stage.

[0066] In order to improve the efficiency and convenience of internal defect localization of insulated gate bipolar transistors, such as Figure 5 As shown, in one embodiment, step 300 includes:

[0067] Step 301: Detect whether the first normal gate discharge charge is greater than the first actual gate discharge charge. If so, locate the internal defect of the target IGBT including the gate-emitter loop defect.

[0068] Specifically, during the gate voltage drop phase, when the gate discharge charge decreases (ΔQ tA =(Q tA,fault —Q tA )<0), indicating that the IGBT has a gate emitter (GE) loop defect. tA,fault It can represent the first actual gate discharge charge, Q tA It can represent the first normal gate discharge charge amount.

[0069] Step 302: Detect whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, locate the internal defect of the target IGBT including the collector gate loop defect.

[0070] Specifically, in the Miller platform phase, when the gate charge changes by ΔQ G=(Q G —Q G,fault )>0, indicating that the collector-gate (CG) loop defect occurs in the IGBT. G,fault It can represent the second actual gate discharge charge, Q G The second normal gate discharge charge amount can be represented.

[0071] In order to achieve quantification of the detection results of the IGBT defects, in one embodiment, after step 301, the following steps are further included:

[0072] Step 303: Determine the number of chips having gate-emitter loop defects in the target IGBT according to the first normal gate discharge charge, the first actual gate discharge charge and the total number of chips.

[0073] Specifically, the number m1 of target IGBT chips with gate-emitter loop defects can be determined according to the following formula:

[0074]

[0075] In order to achieve quantification of the detection results of the IGBT defects, in one embodiment, after step 302, the following steps are further included:

[0076] Step 304: Determine the number of chips of the target IGBT having collector gate loop defects according to the second normal gate discharge charge, the second actual gate discharge charge and the total number of chips.

[0077] Specifically, the number m2 of target IGBT chips with collector-gate loop defects can be determined according to the following formula:

[0078]

[0079] In order to improve the reliability of locating gate defects, in one embodiment, the IGBT defect locating method based on the gate current during the turn-off process further includes:

[0080] Step 305: If the internal defects of the target IGBT include a gate-emitter loop defect and a collector-gate loop defect, then determine that the defect type of the target IGBT is a gate defect.

[0081] Specifically, if the first normal gate discharge charge is greater than the first actual gate discharge charge, and the second normal gate discharge charge is greater than the second actual gate discharge charge, it can be determined that the defect type of the target IGBT is a gate defect.

[0082] In order to improve the reliability of locating emitter defects, in one embodiment, the IGBT defect locating method based on the gate current during the turn-off process further includes:

[0083] Step 306: If the internal defect of the target IGBT includes a gate-emitter loop defect but does not include a collector-gate loop defect, then determine that the defect type of the target IGBT is an emitter defect.

[0084] Specifically, if the first normal gate discharge charge is greater than the first actual gate discharge charge, and the second normal gate discharge charge is less than or equal to the second actual gate discharge charge, it can be determined that the defect type of the target IGBT is an emitter defect.

[0085] In order to improve the reliability of locating collector defects, in one embodiment, the IGBT defect locating method based on the gate current during the turn-off process further includes:

[0086] Step 307: If the internal defect of the target IGBT includes a collector-gate loop defect but does not include a gate-emitter loop defect, then determine that the defect type of the target IGBT is a collector defect.

[0087] Specifically, if the first normal gate discharge charge is less than or equal to the first actual gate discharge charge, and the second normal gate discharge charge is greater than the second actual gate discharge charge, it can be determined that the defect type of the target IGBT is a collector defect.

[0088] In order to improve the reliability of the number of defective chips, in one embodiment, the IGBT defect locating method based on the gate current of the shutdown process may also include: if the defect type is a gate defect, it can be determined whether the number of chips with gate-emitter loop defects and collector-gate loop defects are the same, and then the number of chips with gate defects in the target IGBT is determined to be the number of chips with collector-gate loop defects, otherwise an abnormal warning prompt is output; if the defect type is an emitter defect, the number of chips with emitter defects in the target IGBT is determined to be the number of chips with gate-emitter loop defects; if the defect type is a collector defect, the number of chips with collector defects in the target IGBT is determined to be the number of chips with collector-gate loop defects.

[0089] In order to further illustrate the present solution, the present application provides an application example of an IGBT defect location method based on the gate current during the shutdown process, which is specifically described as follows:

[0090] During the IGBT turn-off transient process, the gate-emitter capacitance (C GE ) and Miller capacitance (C CG ) The current direction is Figure 2 shown.

[0091] 1) For C GE, if the voltage reference direction is G→E, then the process C GE Discharge, gate voltage u GE reduce.

[0092] 2) For C CG , if the voltage reference direction is C→G, then the process C CG Charging, CG and u CE Increase.

[0093] Gate current i G The following relationship exists between Q and voltage (Q is the amount of charge discharged from the gate of a single chip):

[0094]

[0095] Where n is the total number of chips, C GE is the gate-emitter capacitance, u GE is the gate voltage, C CG is the Miller capacitance, u CG is the collector gate voltage.

[0096] If the collector-gate voltage u is taken into account CG ≈ Collector-emitter voltage u CE ,exist:

[0097]

[0098] 1) Gate voltage falling stage (t 0 ~t 1 ),u GE changes, and u CG No change.

[0099] 2) Miller plateau stage (t 1 ~t 2 ),u CG changes, and u GE No change.

[0100] C GE is a constant (not changing with u GE changes with changes), and C CG is a variable (with u CG changes with changes).

[0101] The voltage and capacitance changes at each stage of the shutdown delay process are summarized in Table 1:

[0102] Table 1

[0103]

[0104] Considering the changes in voltage and capacitance at different stages, equation (2) can be organized as:

[0105]

[0106] 1. Gate voltage falling stage (t 0 ~t 1 ):

[0107] The gate voltage u GE The waveform can be used to analyze gate emitter (GE) loop defects, which include gate defects and emitter defects.

[0108] Define the gate-emitter loop time constant τ of a single chip 0 for:

[0109] τ 0 =R G,off C ies (4)

[0110] The overall time constant τ of the gate loop is:

[0111] τ=n×τ 0 =R G,off ×nC ies (5)

[0112] In formula (4), R G,off is the gate turn-on resistance, C ies is the gate input capacitance of a single IGBT chip (C ies =C GE +C CG ).

[0113] During the gate voltage drop phase (t 0 ~t 1 ), due to u CE Maintaining the on-state saturation voltage drop (about 3V), the process C CG It can be approximately considered as a constant C CG,sat .

[0114] t 0 ~t 1 During gate discharge, the following relationship is satisfied:

[0115]

[0116] Among them, U G,on is the gate power supply voltage during the turn-on process, U G,off For the gate supply voltage during the shutdown process, both parameters are fixed and do not change with time.

[0117] Gate voltage u GE The collector current i C The control relationship is:

[0118]

[0119] Among them, μ n is the electron mobility, α pnp is the transistor transport coefficient, w is the gate channel width, l is the gate channel length, c ox is the gate channel capacitance per unit area, U T is the gate threshold voltage.

[0120] The height of the Miller platform is determined by the load current I L The gate voltage Miller platform value is:

[0121]

[0122] Gate voltage u GE From U G,on Reduce to u miller The process (i.e. t 0 ~t 1 Gate discharge charge Q tA It can be equivalent to the first normal gate discharge charge, Q tA for:

[0123]

[0124] If the gate (G) or emitter (E) contact defect occurs in the gate-emitter loop, the gate loop discharge time constant will become smaller. Referring to formula (4), when the gate or emitter contact of m IGBT chips is abnormal, the gate loop time constant changes to:

[0125] τ=(nm)×τ 0 =R G,off ×(nm)C ies (10)

[0126] In the above case, the gate voltage Miller platform value is u miller,fault :

[0127]

[0128] Change of gate Miller platform height Δu miller for:

[0129]

[0130] Gate voltage u GE From U G,on Reduce to u miller,fault The process (i.e. t 0 ~t 1 ) Gate discharge charge Q tA,faultIt can be equivalent to the first actual gate discharge charge, Q tA,fault for:

[0131]

[0132] The following conclusions can be obtained through equations (9) and (12):

[0133] Case 1: When the gate discharge charge decreases (ΔQ tA =(Q tA,fault —Q tA )<0), indicating that a gate-emitter (GE) loop defect occurs in the IGBT.

[0134] If the change in the height of the Miller platform Δu caused by the defect is not considered miller (That is, it is approximately considered that u miller ≈u miller,fault ), the change in the amount of charge discharged through the gate ΔQ tA The number of defective chips m is solved as follows:

[0135]

[0136] 2. Miller platform stage (t 1 ~t 2 ):

[0137] In this stage, the gate current i G The waveform can be used to analyze collector gate (GC) loop defects, which include gate defects and collector defects.

[0138] Gate voltage u GE Miller platform continuous process (t 1 ~t 2 ), collector-emitter voltage u CE From close to 0 to U DC .

[0139] u CG (or u CE ) is larger, C CG The smaller. C CG with u CE The functional relationship between them is:

[0140]

[0141] Where q is the electron charge, N D is the drift region doping concentration, p SC is the hole concentration across the depletion layer, n SC is the concentration of electrons crossing the depletion layer, n is the total number of chips, and ε is the dielectric constant of silicon material.

[0142] Miller platform process gate charge Q G It can be equivalent to the second normal gate discharge charge, Q G for:

[0143]

[0144] When the collector gates of m chips are defective, the gate charge of the Miller platform process can be equivalent to the second actual gate discharge charge mentioned above, Q G，fault for:

[0145]

[0146] The following conclusions can be obtained through formula (17):

[0147] Case 2: When the collector-gate (CG) loop defect occurs in the IGBT, the gate voltage u GE Miller platform process (t 1 ~t 2 The gate charge Q of the process) G,fault The gate charge changes in this process to ΔQ G =(Q G —Q G,fault )>0.

[0148] Combining equations (16) and (17), we can obtain that the gate charge changes to ΔQ G , and the number of defective chips m is obtained:

[0149]

[0150] 3. IGBT defect location method:

[0151] Combining Case 1 and Case 2, the defect location method of IGBT device is obtained as follows:

[0152] 1) Gate defect: Both cases 1 and 2 exist;

[0153] 2) Collector defect: Case 1 does not exist, but case 2 does.

[0154] 3) Emitter defect: Case 1 exists, Case 2 does not exist;

[0155] The IGBT defect types and corresponding conditions are shown in Table 2, where "√" indicates that the corresponding situation exists and "×" indicates that the corresponding situation does not exist.

[0156] Table 2

[0157] Gate defects Collector defect Emitter Defects Case 1 √ × √ Case 2 √ √ ×

[0158] From the software level, in order to realize the location of internal defects of the insulated gate bipolar transistor and facilitate the subsequent maintenance of the insulated gate bipolar transistor, the present application provides an embodiment of an IGBT defect location device based on the gate current during the shutdown process for realizing all or part of the contents of the IGBT defect location method based on the gate current during the shutdown process, see Figure 6 The IGBT defect location device based on the gate current during the shutdown process specifically includes the following contents:

[0159] The acquisition module 01 is used to acquire the total number of chips of the target IGBT, the first normal gate current in the gate voltage falling stage, the first actual gate current, the second normal gate current and the second actual gate current in the Miller platform stage, and the shutdown process includes: the gate voltage falling stage and the Miller platform stage;

[0160] A charge amount determination module 02 is used to determine a first normal gate discharge charge amount in the gate voltage falling stage, a first actual gate discharge charge amount, a second normal gate discharge charge amount in the Miller platform stage, and a second actual gate discharge charge amount in the gate voltage falling stage according to the first normal gate current in the gate voltage falling stage, the first actual gate current, the second normal gate current in the Miller platform stage, and the second actual gate current;

[0161] The detection module 03 is used to complete the internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge in the gate voltage drop stage, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform stage, and the second actual gate discharge charge.

[0162] like Figure 7 As shown, in one embodiment, the detection module 02 includes:

[0163] A first detection unit 021 is used to detect whether the first normal gate discharge charge is greater than the first actual gate discharge charge, and if so, locate the internal defect of the target IGBT including the gate-emitter loop defect;

[0164] The second detection unit 022 is used to detect whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, the internal defect of the target IGBT is located, including a collector gate loop defect.

[0165] In one embodiment, the IGBT defect locating device based on the gate current during the turn-off process further includes:

[0166] The first chip quantity determination module is used to determine the number of chips of the target IGBT having gate-emitter loop defects according to the first normal gate discharge charge, the first actual gate discharge charge and the total number of chips.

[0167] In one embodiment, the IGBT defect locating device based on the gate current during the turn-off process further includes:

[0168] The second chip quantity determination module is used to determine the number of chips of the target IGBT having a collector gate loop defect according to the second normal gate discharge charge, the second actual gate discharge charge and the total number of chips.

[0169] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0170] The gate defect determination module is used to determine that the defect type of the target IGBT is a gate defect if the internal defect of the target IGBT includes a gate-emitter loop defect and a collector-gate loop defect.

[0171] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0172] The emitter defect determination module is used to determine that the defect type of the target IGBT is an emitter defect if the internal defect of the target IGBT includes a gate-emitter loop defect but does not include a collector-gate loop defect.

[0173] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0174] The collector defect determination module is used to determine that the defect type of the target IGBT is a collector defect if the internal defect of the target IGBT includes a collector-gate loop defect but does not include a gate-emitter loop defect.

[0175] The embodiment of the IGBT defect locating device based on the gate current of the shutdown process provided in this specification can be specifically used to execute the processing flow of the embodiment of the IGBT defect locating method based on the gate current of the shutdown process mentioned above. Its functions will not be repeated here, and reference can be made to the detailed description of the embodiment of the IGBT defect locating method based on the gate current of the shutdown process mentioned above.

[0176] Figure 8 A schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention, such as Figure 8 As shown, the electronic device includes: a memory 801, a processor 802, and a computer program stored in the memory 801 and executable on the processor 802. When the processor 802 executes the computer program, the following method is implemented:

[0177] Obtaining the total number of target IGBT chips, a first normal gate current in a gate voltage drop phase, a first actual gate current, a second normal gate current in a Miller platform phase, and a second actual gate current, wherein the shutdown process includes: the gate voltage drop phase and the Miller platform phase;

[0178] Determine a first normal gate discharge charge amount, a first actual gate discharge charge amount, a second normal gate discharge charge amount, and a second actual gate discharge charge amount in the Miller platform stage in the gate voltage falling stage according to the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current in the Miller platform stage in the gate voltage falling stage;

[0179] The internal defect positioning of the target IGBT is completed according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge.

[0180] This embodiment provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following method is implemented:

[0181] Obtaining the total number of target IGBT chips, a first normal gate current in a gate voltage drop phase, a first actual gate current, a second normal gate current in a Miller platform phase, and a second actual gate current, wherein the shutdown process includes: the gate voltage drop phase and the Miller platform phase;

[0182] Determine a first normal gate discharge charge amount, a first actual gate discharge charge amount, a second normal gate discharge charge amount, and a second actual gate discharge charge amount in the Miller platform stage in the gate voltage falling stage according to the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current in the Miller platform stage in the gate voltage falling stage;

[0183] The internal defect positioning of the target IGBT is completed according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge.

[0184] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0185] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0186] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0188] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0189] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for locating IGBT defects based on gate current during the shutdown process, characterized in that: include: Obtaining the total number of target IGBT chips, a first normal gate current in a gate voltage drop phase, a first actual gate current, a second normal gate current in a Miller platform phase, and a second actual gate current, wherein the shutdown process includes: the gate voltage drop phase and the Miller platform phase; Determine a first normal gate discharge charge amount, a first actual gate discharge charge amount, a second normal gate discharge charge amount, and a second actual gate discharge charge amount in the Miller platform stage in the gate voltage falling stage according to the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current in the Miller platform stage in the gate voltage falling stage; The internal defect positioning of the target IGBT is completed according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge.

2. The IGBT defect location method based on the gate current during the turn-off process according to claim 1, characterized in that: The method of completing the internal defect location of the target IGBT according to the total number of chips, the first normal gate discharge charge in the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform phase, and the second actual gate discharge charge comprises: Detecting whether the first normal gate discharge charge is greater than the first actual gate discharge charge, and if so, locating the internal defect of the target IGBT including a gate-emitter loop defect; It is detected whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, the internal defect of the target IGBT is located, including a collector gate loop defect.

3. The IGBT defect location method based on the gate current during the turn-off process according to claim 2, characterized in that: After locating the internal defects of the target IGBT including gate emitter loop defects, the method further includes: The number of chips of the target IGBT having gate-emitter loop defects is determined according to the first normal gate discharge charge, the first actual gate discharge charge and the total number of chips.

4. The IGBT defect location method based on the gate current during the turn-off process according to claim 2, characterized in that: After locating the internal defects of the target IGBT including the collector gate loop defect, the method further includes: The number of chips of the target IGBT having collector gate loop defects is determined according to the second normal gate discharge charge, the second actual gate discharge charge and the total number of chips.

5. The IGBT defect location method based on the gate current during the turn-off process according to claim 2, characterized in that: Also includes: If the internal defects of the target IGBT include a gate-emitter loop defect and a collector-gate loop defect, it is determined that the defect type of the target IGBT is a gate defect.

6. The IGBT defect location method based on the gate current during the turn-off process according to claim 2, characterized in that: Also includes: If the internal defect of the target IGBT includes a gate-emitter loop defect but does not include a collector-gate loop defect, it is determined that the defect type of the target IGBT is an emitter defect.

7. The IGBT defect location method based on the gate current during the turn-off process according to claim 2, characterized in that: Also includes: If the internal defect of the target IGBT includes a collector-gate loop defect but does not include a gate-emitter loop defect, it is determined that the defect type of the target IGBT is a collector defect.

8. An IGBT defect location device based on gate current during shutdown, characterized in that: include: An acquisition module is used to acquire the total number of target IGBT chips, a first normal gate current in a gate voltage drop phase, a first actual gate current, a second normal gate current in a Miller platform phase, and a second actual gate current, wherein the shutdown process includes: the gate voltage drop phase and the Miller platform phase; a charge amount determination module, configured to determine a first normal gate discharge charge amount in the gate voltage falling stage, a first actual gate discharge charge amount, a second normal gate discharge charge amount in the Miller platform stage, and a second actual gate discharge charge amount in the gate voltage falling stage according to the first normal gate current in the gate voltage falling stage, the first actual gate current, the second normal gate current in the Miller platform stage, and the second actual gate current; The detection module is used to complete the internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge in the gate voltage drop stage, the first actual gate discharge charge, the second normal gate discharge charge in the Miller platform stage, and the second actual gate discharge charge.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the IGBT defect location method based on the gate current during the turn-off process as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the instructions are executed by the processor, the IGBT defect location method based on the gate current during the turn-off process described in any one of claims 1 to 7 is implemented.

Images