Approximate multiplier implementation method for neural network and approximate multiplier

Abstract

The invention discloses an approximate multiplier implementation method for a neural network and an approximate multiplier, and the key points of the technical scheme are that the method comprises the steps: inputting a first operand and a second operand, and splitting the first operand into a low-order part and a high-order part; performing first coding on the low-order part to obtain a plurality of groups of first coding numbers, and performing second coding on the high-order part to obtain a plurality of groups of second coding numbers; assembling the plurality of groups of first coding numbers and the plurality of groups of second coding numbers to form an assembly operand; according to the assembly operand and the second operand, generating a partial product matrix and a truncation error compensation value corresponding to the partial product matrix; based on the partial product matrix and the truncation error compensation value, an approximate multiplication result of the first operand and the second operand is generated, approximate high-base coding and truncation compensation are combined for use, and the performance of an approximate multiplier is greatly improved on the premise that the calculation precision and the final network reasoning precision are guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of approximate multiplication calculation, and more particularly to an implementation method of an approximate multiplier for a neural network and an approximate multiplier. Background Art

[0002] The high computational requirements of neural networks have brought serious performance bottlenecks and critical power consumption to embedded systems. The core of neural networks in the reasoning process is MAC (multiply-accumulate) operations. Advanced neural networks integrate thousands of MACs, which consumes a lot of energy. But at the same time, neural networks have strong fault tolerance, so the energy consumed can be reduced through approximate calculations.

[0003] Most of the existing approximate multipliers are based on ASIC design. For example, the Chinese invention patent with authorization announcement number CN111488133B provides a high-performance approximate Booth multiplier and calculation method, which significantly improves the accuracy while reducing the power consumption and area overhead of the approximate Booth multiplier.

[0004] However, compared with FPGA-based computing units, ASIC design is based on the logic gate level, while FPGA design is based on a lookup table 6-LUT and a carry chain. Since the internal logic resources of the FPGA are not taken into consideration during the design, the performance of common ASIC-based multipliers is greatly reduced when applied to FPGA. Therefore, the existing technology has shortcomings. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an implementation method of an approximate multiplier for a neural network and an approximate multiplier. The approximate multiplier is designed through an FPGA architecture and combined with approximate high-radix coding and truncation compensation, so as to greatly improve the performance of the approximate multiplier without affecting the reasoning accuracy.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] The present invention provides a method for implementing an approximate multiplier for a neural network, comprising:

[0008] Input a first operand and a second operand, and split the first operand into a low-order part and a high-order part;

[0009] Performing a first encoding on the low-order part to obtain multiple groups of first coded numbers, and performing a second encoding on the high-order part to obtain multiple groups of second coded numbers;

[0010] Assembling the plurality of groups of first coding numbers and the plurality of groups of second coding numbers to form an assembly operation number;

[0011] Generate a partial product matrix and a truncation error compensation value corresponding to the partial product matrix according to the assembly operand and the second operand;

[0012] An approximate multiplication result of the first operand and the second operand is generated based on the partial product matrix and the truncation error compensation value.

[0013] As a further improvement of the present invention, splitting the first operand into a low-order part and a high-order part includes splitting the first operand into a low-order part and a high-order part according to a preset weight, wherein the low-order part is a part with a lower weight, and the high-order part is a part with a higher weight.

[0014] As a further improvement of the present invention, the high radix approximate Booth code is a radix-8 approximate Booth code, the low radix Booth code is a radix-4 Booth code, and the radix-8 approximate Booth code is to approximate the odd-numbered operations in the radix-8 Booth code to the even-numbered operations, and the approximation error is a positive number.

[0015] As a further improvement of the present invention, generating a partial product matrix according to the assembly operand and the second operand includes:

[0016] The second operand is traversed from the lower bit to the higher bit according to two bits as a group and a step length of one bit, to obtain multiple groups of sub-operands;

[0017] In order from low to high bits, each group of the first coding numbers and each group of the second coding numbers are input into a corresponding lookup table with each group of the sub-operands for logical operation to generate a plurality of partial product bits;

[0018] The plurality of partial product bits are arranged in the order of the lookup table to form the partial product matrix.

[0019] As a further improvement of the present invention, generating the truncation error compensation value corresponding to the partial product matrix includes:

[0020] Truncating the low-order part of the partial product matrix to obtain an approximate partial product matrix and a truncated partial product matrix;

[0021] The truncation error compensation value is generated according to the truncated partial product matrix and the Karnaugh map.

[0022] As a further improvement of the present invention, generating an approximate multiplication result of the first operand and the second operand based on the partial product matrix and the truncation error compensation value includes:

[0023] For two adjacent partial product positions above and below in the partial product matrix, if the carry chain corresponding to the next partial product position receives the corresponding truncation error compensation value, the previous partial product position and the corresponding carry chain output result are selectively input into the carry chain corresponding to the next partial product position, and the truncation error compensation value is input into the carry chain corresponding to the next partial product position to perform an addition logic operation together, so as to obtain a first carry output result of the carry chain corresponding to the next partial product position; otherwise, the previous partial product position and the corresponding carry chain output result are selectively input into the carry chain corresponding to the next partial product position to perform an addition logic operation, so as to obtain a second carry output result of the carry chain corresponding to the next partial product position;

[0024] The last carry output result of each column in the partial product matrix is ​​sequentially combined to obtain an approximate multiplication result of the first operand and the second operand.

[0025] The present invention provides an approximate multiplier, which is applied to the above implementation method. The approximate multiplier is composed of a lookup table and a carry chain arranged according to a pipeline architecture.

[0026] The lookup table is used to generate partial product bits;

[0027] The carry chain is used to implement the addition of the partial product bit and the relatively previous partial product bit or carry output result.

[0028] The present invention provides an FPGA chip, comprising the above-mentioned approximate multiplier.

[0029] The present invention provides an FPGA system, comprising the above-mentioned FPGA chip.

[0030] The present invention designs the lookup table and carry chain in the FPGA, and performs the generation and accumulation of partial products in a pipeline manner. Compared with the multiplier design for ASIC, the number of required lookup tables is greatly reduced, and the number of partial products is reduced by approximate coding, thereby further reducing the delay and the number of lookup tables. At the same time, all low bits with smaller weights in the partial product matrix are truncated, and the error compensation value is generated according to the specific bits of the partial product matrix by using the Karnaugh map simplification method, so as to compensate for the truncation error and ensure the calculation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the method steps of the present invention;

[0032] Figure 2 It is a schematic diagram of the structure of an approximate multiplier of the present invention;

[0033] Figure 3 is the grouping method of the first operand in the present invention;

[0034] Figure 4 is a Karnaugh map used to generate truncation compensation;

[0035] Figure 5 It is a schematic diagram of the 6-LUT structure;

[0036] Figure 6 It is a schematic diagram of the carry chain structure;

[0037] Figure 7 Schematic diagram of the internal logic of six types of LUTs. DETAILED DESCRIPTION

[0038] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations of the technical solution of the present invention.

[0039] The term "and / or" in the following text is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the front and back associated objects are in an "or" relationship. The words "front", "back", "left", "right", "upper" and "lower" used in the following description refer to the directions in the drawings.

[0040] An embodiment of the present application provides an approximate multiplier, which is composed of a lookup table and a carry chain arranged in a pipeline architecture, wherein the lookup table is used to generate a partial product bit, and the carry chain is used to implement the addition of the partial product bit with the relative previous partial product bit or carry output result.

[0041] The approximate multiplier provided in this embodiment is modified based on the approximate multiplier for ASIC (Application-Specific Integrated Circuit) and combined with the 6-LUT (Look-Up-Table) and carry chain resources used in FPGA (Field-Programmable Gate Array), solving the problem of performance degradation when the design based on ASIC is applied to FPGA. It can make full use of the most commonly used 6-LUT in the current FPGA to realize approximate calculation, thereby achieving the purpose of reducing area and power consumption.

[0042] In the prior art, the multiplier design based on FPGA architecture mostly adopts a pipeline architecture, sacrificing part of the delay in exchange for a smaller area, but does not combine the classic approximation means such as approximate high-radix coding and truncation compensation. This embodiment combines the two when performing approximate multiplication operations. On the premise of ensuring the calculation accuracy and the final network inference accuracy, the number of partial product rows can be reduced through approximate high-radix coding, and through truncation error compensation, part of the accuracy is sacrificed in exchange for lower delay, thereby greatly improving the performance of the approximate multiplier.

[0043] The following is a further description of the method steps for implementing approximate multiplication using the above-mentioned approximate multiplier in this application.

[0044] like Figure 1 As shown, the embodiment of the present application provides a method for implementing an approximate multiplier for a neural network, characterized by comprising:

[0045] Input a first operand and a second operand, and split the first operand into a low-order part and a high-order part;

[0046] Performing a first encoding on the low-order part to obtain multiple groups of first coded numbers, and performing a second encoding on the high-order part to obtain multiple groups of second coded numbers;

[0047] Assembling a plurality of groups of first coding numbers and a plurality of groups of second coding numbers to form an assembly operation number;

[0048] generating a partial product matrix and a truncation error compensation value of the corresponding partial product matrix according to the assembly operand and the second operand;

[0049] An approximate multiplication result of a first operand and a second operand is generated based on the partial product matrix and the truncation error compensation value.

[0050] Specifically, splitting the first operand into a low-order part and a high-order part includes splitting the first operand into a low-order part and a high-order part according to a preset weight, wherein the low-order part is a part with a lower weight, and the high-order part is a part with a higher weight.

[0051] The first code is a high-cardinality approximate Booth code, and the second code is a low-cardinality Booth code.

[0052] The method provided in this embodiment is suitable for high-bit multiplication with fault tolerance. The number of partial product rows can be reduced through high-radix approximate Booth coding, thereby improving the performance of the multiplier.

[0053] Specifically, the high radix approximate Booth code is the radix-8 approximate Booth code, the low radix Booth code is the radix-4 Booth code, and the radix-8 approximate Booth code is, approximating the odd-number multiple operations in the radix-8 Booth code to the even-number multiple operations, and the approximation error is a positive number.

[0054] In traditional radix-8 Booth encoding, the generation of each partial product bit requires 4 bits of the multiplier and 3 bits of the multiplicand, which exceeds the input limit of the 6-LUT, resulting in the need for two 6-LUTs to implement the generation of each partial product bit.

[0055] The approximate encoding method provided in this embodiment is proposed based on the characteristics of 6-LUT 6 inputs and 1 output. The radix-8 approximate Booth encoding algorithm can be implemented with only 3 bits of the multiplier and 2 bits of the multiplicand. The number of partial product rows is reduced through high-radix approximate Booth encoding, and the number of input bits required to generate a partial product is limited to the input range of the 6-LUT through an appropriate encoding method. After the approximate high-radix encoding, the generation of each partial product and its accumulation with the calculation result bit of the previous row can still be implemented through a 6-LUT. In this way, the size of the partial product matrix is ​​reduced to the greatest extent, that is, the number of LUTs and carry chains after synthesis is reduced.

[0056] Furthermore, this embodiment provides a step of generating a partial product matrix, including:

[0057] Group two digits into one group, and traverse the second operand from the lower bit to the higher bit with one digit as the step length to obtain multiple groups of sub-operands;

[0058] In order from low to high bits, each group of first coding numbers and each group of second coding numbers are input into a corresponding lookup table with each group of sub-operands for logical operation to generate a plurality of partial product bits;

[0059] Arrange the multiple partial products in the order of the lookup table to form a partial product matrix.

[0060] Furthermore, this embodiment provides a step of generating a truncation error compensation value corresponding to a partial product matrix, including:

[0061] The low-order part of the partial product matrix is ​​truncated to obtain an approximate partial product matrix and a truncated partial product matrix;

[0062] A truncation error compensation value is generated based on the truncated partial product matrix and the Karnaugh map.

[0063] This embodiment generates a truncation error compensation value through Karnaugh map simplification, and inputs it into the carry chain to participate in the subsequent partial accumulation process, which compensates for the error caused by truncation to a certain extent, while further reducing the number of LUTs and offsetting the delay increase caused by the pipeline architecture.

[0064] Furthermore, this embodiment provides a step of generating an approximate multiplication result of a first operand and a second operand based on a partial product matrix and a truncation error compensation value, including:

[0065] For two adjacent partial product positions above and below in the partial product matrix, if the carry chain corresponding to the next partial product position receives the corresponding truncation error compensation value, the previous partial product position and the corresponding carry chain output result are selectively input to the carry chain corresponding to the next partial product position, and the truncation error compensation value is input to the carry chain corresponding to the next partial product position for an addition logic operation to obtain a first carry output result of the carry chain corresponding to the next partial product position; otherwise, the previous partial product position and the corresponding carry chain output result are selectively input to the carry chain corresponding to the next partial product position for an addition logic operation to obtain a second carry output result of the carry chain corresponding to the next partial product position;

[0066] The last carry output result of each column in the partial product matrix is ​​combined in sequence to obtain an approximate multiplication result of the first operand and the second operand.

[0067] For example, Figure 2 As shown in the figure, the above implementation method is explained by taking the 16×16 approximate multiplier structure as an example. In order to reduce the LUT required for the multiplier unit, a pipeline structure is adopted to integrate the generation of the partial product of each row and its addition with the result of the previous row into a one-bit LUT and a one-bit carry chain. The boxes marked with letters represent LUTs, CC represents carry chains, and the bottom row pp represents i Represents each digit of the calculation result.

[0068] For 16-bit signed number multiplication, firstly, the base-8 approximate Booth coding is used for the lower weighted bits in the multiplier, and the base-4 Booth coding is used for the higher weighted bits. The specific multiplier coding grouping method is as follows: Figure 3 As shown, after the lowest bit is padded with 0, the low-order part is grouped by four bits to obtain four groups of base-8 codes (i.e., four groups of first coded numbers), and the high-order part is grouped by three bits to obtain two groups of base-4 codes (i.e., two groups of second coded numbers). It is reflected in the partial product matrix that the first four rows of partial products corresponding to the low bits of the multipliers are obtained by base-8 approximate Booth coding, and the last two rows of partial products corresponding to the high bits of the multipliers are obtained by base-4 Booth coding. The base-8 approximate Booth coding reduces the number of partial product rows from 8 rows to 6 rows.

[0069] The specific approximate coding method and its comparison with the exact coding method are shown in Table 1. The leftmost column is the encoded four-bit multiplier, and the second, third and fourth columns are the exact coding results, approximate coding results and relative error values, respectively. It can be seen that the ×1 and ×3 operations in all exact coding are approximated to ×2, ×4 or zero operations in the table. It is easy to know that the generation of 2A and 4A can be achieved by shifting the multiplicand A left by one or two bits, respectively, and the negative operation is achieved by inverting each bit and then adding one to the lowest bit of the partial product. Therefore, the logic of partial product generation is relatively simple; and it can be observed from Table 1 that the encoded partial product value is only related to the upper three bits of the encoded bit, but not to the lowest bit. At the same time, the value of each bit can only be the corresponding bit of the multiplicand shifted left by one bit, left by two bits (and its inversion) or 0.

[0070] Table 1

[0071]

[0072] Therefore, for the LUT corresponding to the mth bit of the partial product, m = 1, ..., 16, the required input bits are only the multiplicand shifted left by one bit A m-1 and left shift A by two positions m-2 , and the three Bs for each group of multipliers n , B n+1 and B n+2 , where n is the number of groups, n = 0, …, 5, plus the partial product pp generated in the previous row, so that the input required by each LUT is limited to 6 bits, ensuring that each partial product bit generation and its addition with the partial product of the previous row can be implemented by only one LUT, saving LUT resources.

[0073] Furthermore, considering the fault tolerance of the neural network, the 12 columns with lower weights in the partial product matrix ( Figure 2 The solid and dotted box parts in the middle are directly ignored to further reduce the usage of LUT and offset the delay increase caused by the pipeline architecture; in order to partially compensate for the error caused by low-bit truncation, the 8 partial product bits of the 11th and 12th columns (such as Figure 2 The solid line frame part in the middle is divided into two groups, and two compensation bits are generated using the Karnaugh map, which are added to the carry input bits of the partial product carry chain of the second row and the fourth row, respectively. The Karnaugh map is shown in Figure 4 As shown, for the four LUTs in each group, I'1, I1, I'2, and I2 are partial product bits generated by the LUTs in the 11th column of the upper row, the 12th column of the upper row, the 11th column of the lower row, and the 12th column of the lower row, respectively.

[0074] The specific compensation generation method is that for the four values ​​of I'1, I1, I'2, and I2 in a group, when there is a high-order value (12-column position) and a low-order value (11-column position), or the two high-order values ​​are both 1, the compensation value is 1, and in other cases the compensation value is 0; in this way, the compensation value is approximately the value of the 11th and 12th columns after the weight addition is considered. Since the calculation result is smaller due to the truncation of the low-order bits, a positive error is introduced into the Karnaugh map of the compensation bit, which also reduces the complexity of the Karnaugh map implementation logic.

[0075] Then use the 6-LUT and carry chain in the FPGA to perform calculations, where the structure of the 6-LUT is as follows Figure 5 As shown in the figure, it can be configured as 6-input 1-output or 5-input 2-output mode. Its internal specific logic is implemented through a lookup table. I0-I5 in the figure are the six-bit inputs of the LUT. Figure 6 As shown, four bits are generally grouped together, including a carry input Cin, a four-bit selector input O5, a four-bit selection control input O6, four-bit outputs S0, S1, S2, S3 and a carry output Cout; when the carry chain is configured to implement addition logic, such as implementing x+y, O5 needs to input each bit of x (or y), and O6 needs to input the result of the bitwise XOR of x and y.

[0076] like Figure 7 There are six main LUT designs in approximate multipliers, among which LUTA is the most commonly used, with 6-bit input and 1-bit output. The BE in the figure is the encoding logic block, which is based on the three-bit B of the multiplier b. n , B n+1 and B n+2 , control the generation of shift flag s, negation flag c and zero flag z, these three flags and the two bits of the multiplicand A m-1 , A m-2 , a partial product bit t is generated through the selector logic, and then the one-bit result pp generated in the previous row is XORed with the newly generated partial product bit t through the XOR logic to obtain a one-bit output cout, and pp and cout are respectively input into the O5 and O6 terminals of the carry chain to realize the addition of the result pp of the previous row and the partial product bit t generated in this row.

[0077] LUTA2 is located at the highest bit of the partial product in each row, and realizes the addition of the "1" in the previous row in the partial product matrix, the carry output pp of the carry chain in the previous row, and the partial product bit t of this bit. The BE is similar to LUTA and is a coding logic block, but because it is in the high bit of each row, the input only contains the highest bit A of the multiplicand A. 15 , so there is no shift flag s, and the three-digit multiplier B n , B n+1 and B n+2The control coding logic block obtains a partial product bit t, and the base bit of the result obtained by adding the carry output pp of the previous row and "1" is ~pp, and the carry is pp. Therefore, pp is inverted inside the LUT and XORed with the generated partial product bit t. The obtained result cout is input to the O6 end of the carry chain, and ~pp is input to the O5 end of the carry chain to realize the addition of ~pp and t.

[0078] LUTB is used to extend the sign of the most significant bit of each partial product in each row. 15 , three-digit multiplier B n , B n+1 and B n+2 As well as the carry output pp of the previous row, SE is the sign extension bit generation logic, which generates the sign extension bit according to the input three-bit multiplier B n , B n+1 and B n+2 , decide whether to input A 15 The inversion of the highest bit of the partial product is obtained by s. Since the highest bit of the partial product on the right is added to "1", the carry generated is the output pp of the carry chain in the previous row. Therefore, the sign extension bit also needs to be added with pp. The inversion of the highest bit of the partial product S is XORed with the carry output pp of the carry chain in the previous row to obtain the result cout, which is input into the O6 terminal of the carry chain in this row, and pp is input into the O5 terminal of the carry chain to realize the addition of pp and s.

[0079] LUTA1 is located at the lowest bit of the partial product of each row, generates the sign correction bit i and adds it to the result pp of the previous row, and adds the partial product bit t generated in this row. The BE in it is the same as LUTA, which is the encoding logic block used to generate the partial product bit t. The input includes the lowest bit A0 and 0 of the multiplicand, the three bits B of the multiplier n , B n+1 and B n+2 And the result pp of the previous row, the output includes the current bit pout and the carry cout, and no carry chain is needed below it; since the partial product obtained after encoding may be the original partial product or the partial product shifted left by one position, and for the rightmost LUT bit of each row, the partial product is shifted left by one position, then the bit becomes 0, so the input at the multiplicand position is the lowest bit A0 of the multiplier and 0; when the encoding result of the multiplier encoding bit corresponding to this row is a negative number, the corresponding sign correction bit i is 1, otherwise it is zero; in order to realize the addition of the three, the logical formulas pout=pp∧t∧i and cout=i&&(t∧pp)||(t&&pp) are implemented inside the LUT.

[0080] LUTAF is applied in the first row and the phase error compensation part, which implements the function of three bits B according to the multiplier B n , B n+1 and B n+2 , and the two A's of the multiplicandm-1 , A m-2 , get the partial product bit cout and output it directly, which is equivalent to omitting the XOR part of t and pp in LUTA.

[0081] LUTA2F is used to realize the generation of the sign extension bit ~s of the first row and its addition with "1". The bit obtained by adding ~s and 1 is s, and the carry is ~s, but the higher bit needs to be added with "1" through the carry chain, so "1" and ~s can be XORed, that is, s. Therefore, the two-bit results generated by LUTA2F are equal to the result after the highest bit of the multiplicand is encoded, among which Aout is passed to the LUTA of the next row as input, and Bout is passed to the higher bit carry chain as input.

[0082] In summary, this design is carried out at the LUT level. For a LUT, first, a partial product bit is generated through the selector logic according to the two bits of the multiplicand and the three bits of the multiplier. Then, the one-bit result generated in the previous row is XORed with the newly generated partial product bit through the XOR logic. The one-bit result of the previous row and the one-bit XOR result are input into the carry chain, so that encoding and addition are carried out simultaneously. This is done row by row to obtain the final result of the multiplication operation.

[0083] In order to verify the hardware performance of the above-mentioned approximate multiplier, the present invention uses vivado2018.3 for experiments. FPGA adopts xc7k325tfbg to synthesize and implement the designed multiplier to obtain its area (expressed by the number of LUTs), critical path delay, total power consumption and dynamic power consumption, and compares it with the vivado multiplier IP. The comparison results are shown in Table 2. It can be seen from the data that compared with vivadoIP, the present invention increases the delay by 17%, but reduces the area by 67%, reduces the dynamic power consumption by 34%, and greatly improves the overall performance.

[0084] Table 2

[0085]

[0086] In order to verify the software accuracy of the above approximate multiplier, the present invention first uses C++ to test the mean relative error distance (MRED) and normalized mean error distance (NMED) of the present invention for all possible input combinations within the 16-bit range. The specific calculation formula is:

[0087]

[0088] Where ED is the difference between the approximate calculation result and the exact calculation result, S is the exact calculation result, N is the number of inputs, 2 2N is the number of all possible input combinations. The experimental results are shown in Table 3.

[0089] Table 3

[0090]

[0091] Afterwards, the designed multiplier is applied to neural network reasoning for handwritten digit recognition. The present invention selects a small-scale neural network Alexnet and a large-scale network VGG16 for testing, records the probability of correct reasoning, and compares them with the precise 16-bit input signed multiplier respectively. The experimental results are shown in Table 4. It can be seen from the data that the result of network reasoning after applying the present invention is not significantly reduced compared with that of using the precise multiplier.

[0092] Table 4

[0093]

[0094] The implementation method of the approximate multiplier for a neural network provided in this embodiment improves the performance of the approximate multiplier while ensuring the calculation accuracy and the final network reasoning accuracy by combining approximate coding and error compensation.

[0095] Furthermore, an embodiment of the present application provides an FPGA chip, comprising the above-mentioned approximate multiplier.

[0096] Furthermore, an embodiment of the present application provides an FPGA system, including the above-mentioned FPGA chip.

[0097] The embodiments of the present application provide an implementation method and an approximate multiplier for a neural network. Based on ASIC, the 6-LUT and carry chain resources used in FPGA are modified to make the approximate multiplier suitable for the logic resources inside the FPGA, solving the problem of performance degradation when the ASIC-based design is applied to the FPGA. Approximation is achieved through three methods: pipeline architecture, radix-8 approximate Booth encoding, and low-order truncation compensation, saving logic resource consumption. The power consumption, area, and delay of the computing unit in the neural network can be effectively reduced without significantly reducing the accuracy, and the approximate multiplier has good practical application value.

[0098] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0100] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0102] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for implementing an approximate multiplier for a neural network, characterized in that: include: Input a first operand and a second operand, and split the first operand into a low-order part and a high-order part; Performing a first encoding on the low-order part to obtain multiple groups of first coded numbers, and performing a second encoding on the high-order part to obtain multiple groups of second coded numbers; Assembling the plurality of groups of first coding numbers and the plurality of groups of second coding numbers to form an assembly operation number; Generate a partial product matrix and a truncation error compensation value corresponding to the partial product matrix according to the assembly operand and the second operand; An approximate multiplication result of the first operand and the second operand is generated based on the partial product matrix and the truncation error compensation value.

2. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that: The splitting of the first operand into a low-order part and a high-order part includes splitting the first operand into a low-order part and a high-order part according to a preset weight, wherein the low-order part is a part with a lower weight, and the high-order part is a part with a higher weight.

3. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that: The first encoding is a high-cardinality approximate Booth encoding, and the second encoding is a low-cardinality Booth encoding.

4. The method for implementing an approximate multiplier for a neural network according to claim 3, characterized in that: The high radix approximate Booth code is a radix-8 approximate Booth code, the low radix Booth code is a radix-4 Booth code, and the radix-8 approximate Booth code is to approximate an odd-number multiple operation in a radix-8 Booth code to an even-number multiple operation, and the approximation error is a positive number.

5. The method for implementing an approximate multiplier for a neural network according to claim 4, characterized in that: The generating a partial product matrix according to the assembly operand and the second operand comprises: Group two digits into one group, and traverse the second operand from the lower bit to the higher bit with one digit as the step length to obtain multiple groups of sub-operands; In order from low to high bits, each group of the first coding numbers and each group of the second coding numbers are input into a corresponding lookup table with each group of the sub-operands for logical operation to generate a plurality of partial product bits; The plurality of partial product bits are arranged in the order of the lookup table to form the partial product matrix.

6. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that: The generating of the truncation error compensation value corresponding to the partial product matrix comprises: Truncating the low-order part of the partial product matrix to obtain an approximate partial product matrix and a truncated partial product matrix; The truncation error compensation value is generated according to the truncated partial product matrix and the Karnaugh map.

7. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that: The step of generating an approximate multiplication result of the first operand and the second operand based on the partial product matrix and the truncation error compensation value comprises: For two adjacent partial product positions above and below in the partial product matrix, if the carry chain corresponding to the next partial product position receives the corresponding truncation error compensation value, the previous partial product position and the corresponding carry chain output result are selectively input into the carry chain corresponding to the next partial product position, and the truncation error compensation value is input into the carry chain corresponding to the next partial product position to perform an addition logic operation together, so as to obtain a first carry output result of the carry chain corresponding to the next partial product position; otherwise, the previous partial product position and the corresponding carry chain output result are selectively input into the carry chain corresponding to the next partial product position to perform an addition logic operation, so as to obtain a second carry output result of the carry chain corresponding to the next partial product position; The last carry output result of each column in the partial product matrix is ​​sequentially combined to obtain an approximate multiplication result of the first operand and the second operand.

8. An approximate multiplier, applied to the method according to any one of claims 1 to 7, characterized in that: The approximate multiplier is composed of a lookup table and a carry chain arranged in a pipeline architecture. The lookup table is used to generate partial product bits; The carry chain is used to implement the addition of the partial product bit and the relatively previous partial product bit or carry output result.

9. An FPGA chip, characterized in that: Comprising an approximate multiplier as claimed in claim 8.

10. An FPGA system, characterized in that: Comprising an FPGA chip as described in claim 9.

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