Providing recovered data to new memory cell at memory subsystem based on unsuccessful error correction operation

Abstract

The invention relates to providing recovered data to a new memory cell at a memory subsystem based on an unsuccessful error correction operation. It is determined that at least one data of a data set stored at a memory cell of a memory component is associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the data set stored at the memory cell has been completed. In response to determining that the program operation has been completed, the at least one data of the data set stored at the memory cell associated with the unsuccessful error correction operation is recovered. Another memory cell of the memory component is identified in response to recovering the at least one data of the data set stored at the memory cell associated with the unsuccessful error correction operation. The data set including the recovered at least one data is provided to the other memory cell of the memory component.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of an invention patent application with an application date of February 8, 2019, application number "201980018153.X", and invention name "New memory unit providing recovered data to a memory subsystem based on an unsuccessful error correction operation". Technical Field

[0003] Embodiments of the present invention relate generally to memory subsystems, and more particularly to providing recovered data to new memory cells at a memory subsystem based on an unsuccessful error correction operation. Background Art

[0004] The memory subsystem may be a storage system such as a solid state drive (SSD) and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize the memory subsystem to store data at and retrieve data from the memory components. Summary of the invention

[0005] According to one embodiment of the present disclosure, a system includes a memory component and a processing device. The processing device is operatively coupled to the memory component to: perform a first pass of a two-pass programming operation to store a data set at a first portion of the memory component; designate a first subset of the data set as a proxy for estimating an error rate of a second subset of the data set; determine that the second subset of the data set is associated with an unsuccessful error correction operation; and in response to completing a second pass of the two-pass programming operation for the second subset of the data set, recover the second subset of the data set.

[0006] According to another embodiment of the present disclosure, a method includes: performing, by a processing device, a first pass of a two-pass programming operation to store a data set at a first portion of the memory component; designating a first subset of the data set as a proxy for estimating an error rate of a second subset of the data set; determining that the second subset of the data set is associated with an unsuccessful error correction operation; and in response to completing a second pass of the two-pass programming operation for the second subset of the data set, recovering the second subset of the data set.

[0007] According to yet another embodiment of the present disclosure, a non-transitory computer-readable storage medium includes executable instructions. When executed by a processing device, the instructions cause the processing device to: perform a first pass of a two-pass programming operation to store a data set at a first portion of the memory component; designate a first subset of the data set as a proxy for estimating an error rate of a second subset of the data set; determine that the second subset of the data set is associated with an unsuccessful error correction operation; and in response to completing a second pass of the two-pass programming operation for the second subset of the data set, restore the second subset of the data set. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present invention.

[0009] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the invention is illustrated.

[0010] Figure 2 is a flow chart of an example method to provide data to a new data block at a memory subsystem based on an unsuccessful error correction / handling operation according to some embodiments of the present invention.

[0011] Figure 3 is a flow chart of an example method for determining that data read from a data block has an error rate exceeding a threshold and reading additional data from the data block in response to the error rate exceeding the threshold according to some embodiments of the invention.

[0012] Figure 4A Illustrated are examples of initial program verify voltages for levels of memory cells according to some embodiments of the present invention.

[0013] Figure 4B Illustrated is an example of adjusting a program verify voltage to increase or decrease an error rate of data stored at a portion of a memory cell in accordance with some embodiments of the present invention.

[0014] Figure 5A The diagram illustrates an example of providing data from a data block of a memory subsystem according to some embodiments of the present invention.

[0015] Figure 5B The diagram illustrates providing data of a memory subsystem to a buffer after performing an error correction / handling operation according to some embodiments of the invention.

[0016] Figure 5C The diagram illustrates recovering data associated with an unsuccessful error correction / handling operation of a memory subsystem and identifying another block of data according to some embodiments of the invention.

[0017] Figure 5D The diagram illustrates providing data to another data block of the memory subsystem according to some embodiments of the present invention.

[0018] Figure 6 is a block diagram of an example computer system in which embodiments of the invention may operate. DETAILED DESCRIPTION

[0019] Aspects of the present invention are directed to providing recovered data to a new memory cell at a memory subsystem based on an unsuccessful error correction operation. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage system. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0020] The memory subsystem may store data at a data block of a memory component included in the memory subsystem. Each data block may include one or more memory cells to store data. Each of the memory cells may store one or more bits of binary data corresponding to data received from a host system. The memory component may include a quad-level cell (QLC) memory. In a QLC memory, each memory cell may store four data bits. For example, in a QLC memory, a memory cell may store four data bits (e.g., 1111, 0000, 1101, etc.) corresponding to data received from a host system. Each bit of the memory cell is stored at a different portion (hereinafter also referred to as a "page") of the memory cell. The memory cell of the QLC memory may have a total of four pages. A bit may be represented by each of the four pages of the memory cell. In the memory cell of the QLC memory, each combination of four bits may correspond to a different voltage level (hereinafter also referred to as a "level").

[0021] The memory subsystem may receive a request from the host system to perform a programming operation to store data at the QLC memory. The memory subsystem may store data by performing a two-pass programming operation on memory cells of the memory components in the memory subsystem. During a first programming pass of the two-pass programming operation, the memory subsystem programs a number of pages to one or more memory cells. For example, during a first programming pass of the QLC memory, three of four pages are programmed based on data received from the host system. A second programming pass may then be performed on the memory cells to program a last page of data to the memory cells by using information about the three pages programmed in the first programming pass.

[0022] In an example using QLC memory, during the second programming pass, the remaining data pages are received from the host and the three pages programmed during the first programming pass are read from the memory components of the memory subsystem. If the measured error rate of the page with the highest error rate among the three pages is below a threshold, the remaining two pages are not provided for error correction / handling operations. Instead, the remaining two pages can be read internally within the memory components and used for the second programming pass.

[0023] If the measured error rate of the page expected to have the highest error rate among the three pages exceeds a threshold, then the other two pages are read from the memory and error correction / handling operations may be performed on the two pages. The error correction / handling operations produce corrected data that is provided to the memory component for storage during the second programming pass. Thus, memory pages associated with high expected error rates are provided for error correction / handling operations, while memory pages associated with low expected error rates are stored internally on a buffer of the memory component, thereby reducing the amount of data provided for error correction / handling operations.

[0024] Typically, when data (e.g., one or more memory pages) is read from a conventional memory subsystem, the data stored on the memory cells of the conventional memory subsystem may include errors caused by noise or error / disturbance mechanisms that cause the value (e.g., bit) of the stored data to toggle (e.g., from '0' to '1'). The errors may be detected and corrected based on error correction / handling operations. The error correction / handling operations may include one or more read retries using parameters that are different from the initial read operation performed on the memory cell (e.g., a change in voltage thresholds). The error correction / handling operations may also use hard information corresponding to the bit value (e.g., 0 or 1) read from the memory cell and soft information corresponding to the probability that the hard information read from the memory cell is correct to correct the bit value stored at the memory cell.

[0025] Since the remaining data to be programmed during the second programming pass depends in part on the data (e.g., three pages) stored at the memory cells during the first programming pass being correct (e.g., not including errors), the memory subsystem may perform error correction / handling operations on one or more pages of data stored at the memory cells during the first programming pass. For example, the memory subsystem may read only one of the pages of data from the memory component based on an expected error rate and perform error correction / handling operations on the one page.

[0026] However, in some examples, the error correction / handling operation may not be able to correct errors in the data stored at one or more of the three pages of the memory cell, which results in an unsuccessful error correction / handling operation. If the error correction / handling operation fails to correct the data, the memory subsystem may perform a recovery operation on the data. The recovery operation may use a logic operation to recover the data. In some embodiments, the logic operation may be based on a redundant array of independent NAND (RAIN). RAIN utilizes a scheme similar to a redundant array of independent disks (RAID) for NAND memory components. In one example, an unsuccessful error correction / handling operation may indicate that the memory storing the data is affected by noise or an error mechanism that may be caused by a physical defect of the memory cell. Since the data stored at the remaining pages programmed during the second programming pass depends on the data at the first three pages not containing errors, if the remaining portion is programmed at the memory cell during the second programming pass, the data stored at the remaining pages may also contain errors.

[0027] The recovery operation may be reserved for data that cannot be corrected by the error correction / handling operation because the recovery operation is a time intensive operation. To minimize or prevent delays in subsequent programming operations performed by the memory subsystem while the recovery operation is performed, a second programming pass may be performed despite one or more of the pages from the first programming pass not being corrected by the error correction / handling operation. After the page has been programmed to the memory component, the recovery operation is performed on the uncorrected data from the first programming pass once the memory subsystem has performed the subsequent programming operation.

[0028] Aspects of the present invention address the above and other deficiencies by providing recovered data to new memory cells at a memory subsystem based on an unsuccessful error correction / handling operation while minimizing delays in executing incoming read / program requests from a host. For example, a first programming pass may be performed on memory cells at a memory subsystem to provide data to one or more pages of the memory cells.

[0029] During the second programming pass, the memory subsystem may perform a read operation on one or more data pages stored at the memory cell during the first programming pass (e.g., provide the data to an external read of a memory controller or host system). The memory subsystem may perform an error correction / handling operation on the data read from the memory cell. In some embodiments, the memory subsystem may determine an error rate associated with the data during the performance of the error correction / handling operation. In one embodiment, if the error correction / handling operation on the data stored at the memory cell is successful, the corrected data may be stored in a relocation buffer that stores corrected data to be relocated or written to a memory component of the memory subsystem during the second programming pass. Otherwise, if the error correction / handling operation is unable to correct the errors of the data stored at the memory cell, the data may be provided to the relocation buffer of the memory subsystem for storage and marked to indicate that a recovery operation will be performed on the uncorrected data.

[0030] A recovery operation (e.g., RAIN) may be performed to recover data received from a host system and stored at a memory cell during a first programming pass. The recovery operation may be a logical operation (e.g., a XOR operation) performed between other data and parity data associated with the three pages programmed during the first programming pass to produce recovered data. The other data may correspond to redundant data associated with the three pages programmed during the first programming pass stored at another memory component of the memory subsystem. Data associated with a second programming pass may also be stored at a buffer that includes data associated with an unsuccessful error correction / handling operation from the first programming pass, as well as other data from the first programming pass (e.g., data stored at the memory cell that does not include errors), corrected data generated from the error correction / handling operation, and / or data from the second programming pass. One or more data pages in the relocation buffer that failed error correction / handling may be recovered by a RAIN operation.

[0031] The memory subsystem can recover data that is not correctable by error correction / handling operations. For example, the data can be recovered based on parity data associated with a recovery operation performed after a second programming pass of the memory component.

[0032] Since an unsuccessful error correction / handling operation may indicate an erroneous memory cell, the memory subsystem may identify another memory block including a plurality of other memory cells to store the recovered data and the received data from the host system. After identifying the other memory block, the recovered data, the other data, and the received data may be provided to the identified other memory block for storage at pages of the other memory cells.

[0033] Advantages of the present invention include, but are not limited to, improved reliability of data stored at a storage system and improved system performance. By delaying the execution of a recovery operation for one or more pages that failed an error correction / handling operation, computing resources are not dedicated to the recovery operation, thereby preventing delays in incoming read / write requests from a host system, which results in improved system performance. Furthermore, identifying and providing recovered data to another memory block prevents data from being stored on a failed memory cell, which results in improved data retention accuracy and overall performance of the memory subsystem. Additionally, although the present invention describes performing various operations on memory cells of a QLC memory during a two-pass programming operation, aspects of the present invention may be applied to any number (e.g., one or more) of programming operations for any type of memory.

[0034] Figure 1 An example computing environment 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present invention. The memory subsystem 110 may include media, such as memory components 112A-112N. The memory components 112A-112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0035] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components) (whether wired or wireless), including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 can further utilize a high-speed NVM (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for transferring control signals, address signals, data signals, and other signals between the memory subsystem 110 and the host system 120.

[0036] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include non-AND (NAND) type flash memory. Each of memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC), such as three-level cells (TLC) or four-level cells (QLC). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more bits of data (e.g., a block of data) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory may perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, the cross-point non-volatile memory may perform write-in-place operations, where the non-volatile memory cells may be programmed without first erasing the non-volatile memory cells. Furthermore, the memory cells of the memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to the unit of the memory component for storing data.

[0037] The memory system controller 115 (hereinafter referred to as "controller") can communicate with the memory components 112A-112N to perform operations such as reading data, writing data, or erasing data and other such operations at the memory components 112A-112N. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a controller 115, but in another embodiment of the invention, the memory subsystem 110 may not include the controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A-112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical block addresses and physical block addresses associated with the memory components 112A-112N. The controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory components 112A-112N and convert responses associated with the memory components 112A-112N into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components that are not illustrated. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A-112N.

[0040] The memory subsystem 110 includes a memory cell identification component 113 that can be used to identify a new memory cell for data associated with an unsuccessful error correction / handling operation. In some embodiments, the controller 115 includes at least a portion of the characteristic component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the memory cell identification component 113 is part of the host system 110, an application, or an operating system.

[0041] The memory cell identification component 113 may determine that data stored at a memory cell of a memory component is associated with an unsuccessful error correction / handling operation. The memory cell identification component 113 may recover the data associated with the unsuccessful error correction / handling operation. The memory cell identification component 113 may identify another memory cell of the memory subsystem 110 in response to recovering the data associated with the unsuccessful error correction / handling operation. The memory cell identification component 113 may provide the recovered data and any additional data stored at the memory cell to a new memory cell for storage at the new memory cell. Further details on the operation of the memory cell identification component 113 are described below.

[0042] The memory subsystem 110 may also include additional circuitry or components that are not illustrated. In some implementations, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A-112N.

[0043] Figure 2 2 is a flow chart of an example method 200 for providing data to a new data block at a memory subsystem based on an unsuccessful error correction / handling operation according to some embodiments of the present invention. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The memory cell identification component 113 is executed.

[0044] At block 210, the processing device determines that at least one data of a data set stored at a data block of a memory component is associated with an unsuccessful error correction / handling operation. The data block includes one or more memory cells of the memory component for storing one or more bits of user data. In some embodiments, the data set stored at the data block may be stored during a previous programming operation. For example, the data set may be stored at the data block during a first programming pass of a two-pass programming operation. In some embodiments, the data set may include at least one data page associated with an unsuccessful error correction / handling operation and other data, such as data stored at the data block that does not contain errors or corrected data generated from performing an error correction / handling operation, as previously discussed. In one embodiment, the data set may include subsequent data received from a host system, such as subsequent data to be programmed to the data block during a second programming pass of a two-pass programming operation. In an embodiment, the data set may be provided to a buffer of a memory subsystem for storage.

[0045] In an embodiment, the processing device determines that the at least one data is associated with an unsuccessful error correction / handling operation based on the identification information associated with the at least one data being present in a data structure indicating data associated with the unsuccessful error correction / handling operation. For example, if the identification information associated with the at least one data (e.g., address information, page number, etc.) is present in a data structure indicating data associated with the unsuccessful error correction / handling operation stored at the storage system, the processing device may determine that the at least one data is associated with an unsuccessful error correction / handling operation. The data structure may be used to determine which data pages will be restored after performing the second programming pass.

[0046] At block 220, at least one data associated with the unsuccessful error correction / handling operation of the data set stored at the data block is recovered. In an embodiment, the data may be recovered based on parity data associated with the recovery operation performed after the second programming pass. As previously discussed, the data programmed during the two-pass programming may include errors that are not correctable by the error correction / handling operation. The data pages that are not correctable by the error correction / handling operation are identified in the data structure. In some embodiments, if the programmed data page is not identified in the data structure, the two-pass programming is completed without uncorrectable errors and no recovery operation is performed on the data.

[0047] However, if one or more data pages are identified in the data structure, then the one or more data pages contain errors that are not correctable by the error correction / handling operation. In some embodiments, if one or more pages contain uncorrectable errors, the two-pass programming operation can be marked by entering page information of the one or more pages containing uncorrectable errors into the data structure. After the two-pass programming, if the two-pass programming operation is marked, a recovery operation, such as a RAIN recovery, is performed on the one or more pages identified in the data structure as having errors that are not correctable by the error correction / handling operation. The uncorrected data stored in the relocation buffer can be replaced with the corrected data generated from the recovery operation.

[0048] At block 230, another data block of the memory component is identified in response to recovering at least one data page of the data set stored at the data block that is associated with the unsuccessful error correction / handling operation. As previously discussed, the data stored at the data block being associated with the unsuccessful error correction / handling operation may indicate that the data block is erroneous or faulty (e.g., cannot reliably store data). Therefore, another data block is identified for storing the data. In some embodiments, the another data block is located on the same block stripe of a group of data blocks of the memory component as the initial data block. The block stripe may refer to a group of data received from a host system and corresponding parity data generated for the group of data. Therefore, the block stripe may be changed so that a previous data block storing data associated with the unsuccessful error correction / handling operation is replaced with another data block that will store the recovered data.

[0049] At block 240, the data set including the recovered data is provided to another data block identified at block 230. In an embodiment, the data set includes other data stored at the initial data block that is not associated with the unsuccessful error correction / handling operation.

[0050] Figure 3 1 is a flow chart of an example method 300 for determining that data read from a data block has an error rate exceeding a threshold and, in response to the error rate exceeding the threshold, reading other data from the data block according to some embodiments of the present invention. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The memory cell identification component 113 is executed.

[0051] At block 310, the processing device determines that the data read from the data block has an error rate exceeding a threshold. The error rate may be determined by performing an error correction / handling operation on the data read from the data block. An error rate exceeding the threshold may indicate that the data page has been affected by a severe noise / error mechanism. An error rate exceeding the threshold may also indicate that other data pages written to the data block may be affected by a similar noise / error mechanism, which results in an increased error rate for the other data pages. In an embodiment, an error rate exceeding the threshold may correspond to a number of errors in the data read from the data block exceeding the correction capability of the error correction / handling operation. In an embodiment, the data read from the data block may be data stored at a first page of the data block during a previous programming operation (e.g., during a first programming pass of a two-pass programming operation). In an embodiment, the error rate of the data is determined during an error correction / handling operation performed on the data read from the data block. The error rate corresponds to the number of bit errors per unit time that the data stored at the data block contains errors. In some embodiments, the error rate associated with the data may be used as a proxy for other data stored at the data block during the first programming pass. For example, the data programmed during the first programming pass may have similar errors and disturbance mechanisms. Thus, the elevated error rate of the data stored at the data block may also indicate an elevated error rate of other data stored at the data block that was programmed in the first programming pass. Since the data and the other data stored at the data block are programmed during the first programming pass, the error rate of the data may be used to determine whether the other data may contain errors. For example, if the error rate exceeds a threshold (indicating a relatively high error rate associated with the data), the other data stored at the data block may also have a relatively high error rate. Thus, if the memory subsystem determines that the error rate exceeds the threshold, the data read from the data block and the other data stored at the data block are provided for error correction.

[0052] As described above, in order for the error rate of the data read for error correction to be used as a proxy for other data stored at the data block, the error rate associated with the data is greater than the error rate associated with the other data programmed in the first programming pass. For example, if three pages are programmed in the first pass and one page is read for error correction, then in order for the one page to be used as a proxy for other data stored at the memory cells of the data block, the error rate of the one page should be higher than the other two pages. Therefore, if the error rate associated with the data is not greater than the error rate associated with the other data, the error rate can be adjusted. The adjustment of the error rate can be based on the adjustment of the program verification (PV) voltage for the corresponding level of the memory cell. The PV voltage for a specific level corresponds to a target voltage threshold, so that each memory cell at the specific level has a voltage threshold exceeding the PV voltage. For example, if the specific level has a PV voltage of PV1, the memory cells programmed to the specific level can have a voltage threshold greater than PV1. The PV voltage can be adjusted so that a desirable ordering between page error rates can be achieved. An operation to adjust the PV voltage (hereinafter also referred to as a dynamic programming target (DPT) operation) can be performed over time. The input of the DPT operation uses the page error rate and iteratively adjusts the PV voltage associated with a particular page of memory cells in an iterative process to achieve a desired error rate between different pages of memory cells. The DPT operation can adjust the PV voltage associated with the memory cell so that a subsequent error rate associated with the data stored at the memory cell can be expected to be greater than a subsequent error rate associated with other data stored at the memory cell. For example, the DPT operation can reduce the range of PV voltages associated with the data stored at the memory cell and / or increase the range of PV voltages associated with other data stored at the memory cell to ensure that a subsequent error rate associated with the data is greater than a subsequent error rate associated with the other data. Figure 4A and 4B Further details regarding regulating the PV voltage are described.

[0053] At block 320, in response to determining that the data read from the data block has an error rate exceeding a threshold, other data is read from the data block. In one embodiment, the other data may correspond to data stored at one or more pages of the data block. For example, the data read at block 310 may be data stored at the first page of the data block. At block 330, an error correction / handling operation is performed on the other data read from the data block at block 320. In some embodiments, errors may be detected and corrected using an error correction code (ECC) operation or another type of error detection and correction operation. In one embodiment, if the error correction / handling operation performed on the other data is unsuccessful, identification information (e.g., address information, page number, etc.) associated with the other data may be stored in a data structure indicating that the other data is associated with an unsuccessful error correction / handling operation. In an embodiment, a two-pass programming operation may be marked to indicate that at least one data page was not corrected by the error correction / handling operation.

[0054] At block 340, a determination is made as to whether the error correction / handling operation performed on the other data at block 330 was successful. If the other data is associated with an unsuccessful error correction / handling operation, the method 300 proceeds to block 350, where a second programming pass is performed with the other data that is not correctable by the error correction / handling operation and the two-pass programming operation is marked for a subsequent recovery operation. The data and / or the other data may be associated with an unsuccessful error correction / handling operation when the number of errors in the data and / or the other data exceeds the error correction capability of the error correction / handling operation. In some embodiments, the other data is determined to be associated with the unsuccessful error correction / handling operation by querying a data structure of the memory subsystem that identifies the data associated with the unsuccessful error correction / handling operation. For example, if identification information associated with the other data read from the data block is located in a data structure indicating that the other data is associated with the unsuccessful error correction / handling operation, it may be determined that the other data is associated with the unsuccessful error correction / handling operation. The identification information (e.g., address information and / or page number) may be used to locate the other data stored at the memory component of the memory subsystem and provide the other data for a recovery operation. If the error correction / handling operations performed on the data and the other data at block 330 are successful, the method 300 proceeds to block 370 .

[0055] At block 350, data associated with the unsuccessful error correction / handling operation is restored at a later time after the second programming pass has been completed. For example, if the other data is associated with an unsuccessful error correction / handling operation, the other data is restored. In an embodiment, the other data is restored based on parity data associated with the redundant operation implemented during the first programming operation, as previously discussed. At block 360, the data read from the data block, the corrected data, and / or the recovered data are provided to another data block of the memory subsystem. For example, if it is determined that the data read at block 310 does not include any errors and the other data read at block 320 is restored at block 350, the data read at block 310 and the other data restored at block 350 are provided to another data block. In an embodiment, a data block with uncorrectable data may be marked for a folding operation that moves all data written to the data block to a new data block. At box 370, if the error correction / handling operation on the data read at box 310 and the other data read at box 320 is successful, then the corrected data and the corrected other data are written to the same or original data block from which the data and the other data were read during the second programming pass.

[0056] Figure 4A An example of an initial program verify voltage 400 for a level of a memory cell is illustrated in accordance with one embodiment of the present invention. As shown, a memory cell storing two bits of data includes four levels L0, L1, L2, and L3 that can be programmed with three PV voltages (e.g., PV1 for L1, PV2 for L2, and PV3 for L3). In this example, the valley margin (D2) between L1 and L2 determines the expected error rate of data stored at a portion of the memory cell, and the valley margin (D1) between L0 and L1 and the valley margin (D3) between L2 and L3 determine the error rate of data stored at another portion of the memory cell. The valley margin may correspond to a voltage range that is greater than the voltage range for a particular level but less than the PV voltage for the next level. For example, the valley margin D1 is a voltage range that is greater than the maximum voltage of L0 and less than the PV voltage for the next level (e.g., PV1 for L1).

[0057] Figure 4BThe diagram illustrates an example of adjusting a program verification voltage 450 to increase or decrease an error rate of data stored at a portion of a memory cell according to some embodiments of the present invention. As shown, the error rate of data stored at a portion of a memory cell will be reduced such that the error rate of data stored at the portion of the memory cell is less than the error rate of data stored at another portion of the memory cell. For example, PV2 may be shifted to the right (e.g., PV2A), which reduces the valley margin D3 between shifted L2 and L3 while also increasing the valley margin D2 between L1 and L2. The result is that the error rate associated with the data stored at the portion of the memory cell is reduced by increasing the distance D2 associated with the data stored at the first portion of the memory cell. In addition, the expected error rate associated with the data stored at the other portion of the memory cell is increased by reducing the distance D3 associated with the error rate of the data stored at the second portion of the memory cell.

[0058] In another example, PV1 may be shifted to the left (e.g., PV1A), which reduces the valley margin D1 between shifted L1 and L0 and increases the distance D2 valley margin between shifted L1 and L2. This results in the error rate associated with the data stored at the portion of the memory cell being reduced by increasing the distance D2 associated with the data stored at the portion of the memory cell. Additionally, the error rate associated with the data stored at the other portion of the memory cell is increased by reducing the distance D1 associated with the error rate of the data stored at the other portion of the memory cell.

[0059] Figure 5A The diagram illustrates an example of providing data from a data block of a memory subsystem 500 according to an embodiment of the present invention. The memory subsystem 500 includes a controller 510, a buffer 520, and a data block 530. In some embodiments, the controller 510 includes at least a portion of the buffer 520. In one embodiment, the buffer 520 may be located external to the memory 530. Data 532 and data 534 may be stored at different pages of the data block 530. For example, data 532 is stored at a first page of the data block 530 and data 534 is stored at a second page of the data block 530. In this illustration, data 532 is provided to the controller 510, where the controller 510 will perform error correction / handling operations on the data 532 and the data 534. Data 532 may act as a proxy for data 534, where data 534 is provided to the controller 510 based on an error rate associated with the data 532 exceeding a threshold, as previously described in Figure 3 Discussed in.

[0060] Figure 5BThe diagram illustrates that data of the memory subsystem 525 is provided to the buffer after performing an error correction / handling operation according to some embodiments of the present invention. In this diagram, the error correction / handling operation performed on the data 532 is successful, which produces corrected data 532a. In this example, the error rate associated with the data 532 is higher than the threshold, which causes the data 534 to be read externally to the controller 510. However, the error correction / handling operation performed on the data 534 is unsuccessful. Corrected data 532a and data 534 (e.g., uncorrected data) are provided to the buffer 520 for storage. The controller 510 may also provide identification information associated with the data 534 to a data structure indicating that the data 534 is associated with an unsuccessful error correction / handling operation. After the error correction / handling operation, data 536 is received from the host system 540 to program the data 536 to the data block 530. The data 536 is stored at the buffer 520 together with the corrected data 532a and the uncorrected data 534. During the second programming pass, corrected data 532a, uncorrected data 534, and data 536 are programmed to data block 430. In an embodiment, because the second programming pass includes uncorrected data 534, the two-pass programming operation may be marked for a recovery operation.

[0061] Figure 5C The diagram illustrates recovering data associated with an unsuccessful error correction / handling operation and identifying another data block of a memory subsystem 550 according to an embodiment of the present invention. The controller 510 performs a recovery operation on the data 534 (as previously described), which produces recovered data 534a. Instead of the uncorrected data 534, the controller 510 provides the recovered data 534a to the buffer 520 for storage. In addition, in response to performing the recovery operation, the controller 510 identifies another data block 555 of the memory subsystem 550 for storing the corrected data 532a, the recovered data 534a, and the data 536. In an embodiment, the data block 530 may be marked for a folding operation to be performed on the data stored at the block 530.

[0062] Figure 5DThe diagram illustrates providing data to another data block of the memory subsystem 575 according to an embodiment of the present invention. Corrected data 532a, recovered data 534a, and data 536 are provided from the buffer 520 to the data block 555 for storage. In some embodiments, the corrected data 532a is stored at the first page of the data block 555, the recovered data 534a is stored at the second page of the data block 555, and the data 536 is stored at the third page of the data block 555. Although the present example illustrates operations performed by the controller 510 of the memory subsystem, in some embodiments, the operations may be performed by other components of the memory subsystem. For example, the operations may be performed by a host system of the memory subsystem.

[0063] Figure 6 An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120), or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0064] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0065] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0066] The processing device 602 represents one or more general-purpose processing devices (e.g., microprocessors, central processing units, etc.). More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a number of processors that implement a combination of several instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate via a network 620.

[0067] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside completely or at least partially within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0068] In one embodiment, instructions 626 include instructions for implementing a method corresponding to a memory cell identification component (eg, Figure 1 The memory unit identification component 113 of the machine readable storage medium 624 is provided with the functional instructions. Although the machine readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present invention. Therefore, the term "machine readable storage medium" should be taken to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0069] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing technology to most effectively convey the substance of their work to others skilled in the art. An algorithm is conceived here, and in general, to be a self-consistent sequence of operations to achieve a desired result. The operations are those requiring physical manipulations of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0070] It should be remembered, however, that all of these terms and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may refer to the actions and processes of a computer system or similar electronic computing device to manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0071] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0072] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures for various of these systems will appear as set forth in the description hereinafter. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present invention as described herein.

[0073] The present invention may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0074] In the foregoing specification, embodiments of the present invention have been described with reference to specific example embodiments of the invention. It will be apparent that various modifications may be made to the invention without departing from the broader spirit and scope of the embodiments of the invention as set forth in the appended claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory components; and a processing device operatively coupled to the memory component to: performing a first pass of a two-pass programming operation to store a data set at a first portion of the memory component; designating a first subset of the data set as a proxy for estimating an error rate for a second subset of the data set; determining that the second subset of the data set is associated with an unsuccessful error correction operation; as well as Responsive to completing a second pass of the two-pass programming operation for the second subset of the data set, restoring the second subset of the data set.

2. The system of claim 1, wherein the processing device is further configured to: storing the second subset of the data set at a second portion of the memory component; receiving a second data set associated with the data set; and The second data set is stored at the second portion of the memory component.

3. The system of claim 2, wherein the first portion of the memory component comprises a first block and the second portion of the memory component comprises a second block. 4 . The system of claim 1 , wherein the second subset of the data set is determined to be associated with an unsuccessful error correction operation in response to performing a read operation for the second subset of the data set stored at the first portion of the memory component.

5. The system of claim 4, wherein the read operation is performed before the second pass of the two-pass programming operation.

6. The system of claim 1, wherein the second subset of the data set is recovered based on parity data associated with the data set.

7. The system of claim 1 , wherein determining that the second subset of the data set is associated with an unsuccessful error correction operation further comprises: Identification information stored in a data structure associated with the second subset of the data set is examined.

8. A method comprising: performing, by a processing device, a first pass of a two-pass programming operation to store a data set at a first portion of the memory component; designating a first subset of the data set as a proxy for estimating an error rate for a second subset of the data set; determining that the second subset of the data set is associated with an unsuccessful error correction operation; as well as Responsive to completing a second pass of the two-pass programming operation for the second subset of the data set, restoring the second subset of the data set.

9. The method according to claim 8, further comprising: storing the second subset of the data set at a second portion of the memory component; receiving a second data set associated with the data set; and The second data set is stored at the second portion of the memory component.

10. The method of claim 9, wherein the first portion of the memory component comprises a first block and the second portion of the memory component comprises a second block.

11. The method of claim 8, wherein the second subset of the data set is determined to be associated with an unsuccessful error correction operation in response to performing a read operation for the second subset of the data set stored at the first portion of the memory component.

12. The method of claim 11, wherein the read operation is performed before the second pass of the two-pass programming operation.

13. The method of claim 8, wherein the second subset of the data set is recovered based on parity data associated with the data set.

14. The method of claim 8, wherein determining that the second subset of the data set is associated with an unsuccessful error correction operation further comprises: Identification information stored in a data structure associated with the second subset of the data set is examined.

15. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to: performing a first pass of a two-pass programming operation to store a data set at a first portion of the memory component; designating a first subset of the data set as a proxy for estimating an error rate for a second subset of the data set; determining that the second subset of the data set is associated with an unsuccessful error correction operation; as well as Responsive to completing a second pass of the two-pass programming operation for the second subset of the data set, restoring the second subset of the data set.

16. The non-transitory computer-readable storage medium of claim 15, further comprising executable instructions that, when executed by the processing device, cause the processing device to: storing the second subset of the data set at a second portion of the memory component; receiving a second data set associated with the data set; and The second data set is stored at the second portion of the memory component.

17. The non-transitory computer-readable storage medium of claim 15, wherein the second subset of the data set is determined to be associated with an unsuccessful error correction operation in response to performing a read operation for the second subset of the data set stored at the first portion of the memory component.

18. The non-transitory computer-readable storage medium of claim 17, wherein the read operation is performed before the second pass of the two-pass programming operation.

19. The non-transitory computer-readable storage medium of claim 15, wherein the second subset of the data set is recovered based on parity data associated with the data set.

20. The non-transitory computer-readable storage medium of claim 15, wherein determining that the second subset of the data set is associated with an unsuccessful error correction operation further comprises: Identification information stored in a data structure associated with the second subset of the data set is examined.

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