Method and system for realizing packaging of memory chip based on lead bonding

Abstract

The invention relates to the technical field of chip packaging, and discloses a method and system for packaging a storage chip based on lead bonding, and the method comprises the steps: carrying out the front-end processing of the storage chip, and obtaining a target storage chip; evaluating expected application performance corresponding to the target memory chip, calculating a bonding adaptation coefficient between the target memory chip and the lead bonding material, and screening out a corresponding optimal bonding material from the lead bonding material; collecting a chip initial image corresponding to the target storage chip, identifying a lead bonding original point, a lead bonding end point and a middle welding point in the chip welding points, and calculating the welding point circularity corresponding to the middle welding point; determining optimal welding spots from the middle welding spots, planning a lead bonding path corresponding to the target storage chip, and analyzing a physical representation attribute corresponding to each welding spot in the optimal welding spots; and performing bonding packaging processing on the target storage chip to obtain a packaged storage chip. The invention mainly aims to solve the problem that the packaging quality of the storage chip is reduced.

Description

Technical Field

[0001] The invention relates to a packaging method and system for a memory chip based on wire bonding, belonging to the technical field of chip packaging. Background Art

[0002] In today's era of rapid development of the electronic information industry, memory chips, as the core storage components of various electronic devices, have seen explosive growth in market demand. In order to meet the growing market demand and ensure the high performance and high reliability of memory chips, memory chip packaging technology has become one of the key links.

[0003] In the traditional memory chip packaging process, the wafer must first be cut to obtain a single memory chip, and then the chip is placed on a specific lead frame or substrate, followed by wire bonding operations. In the wire bonding process, the operator mainly relies on past experience to determine some basic bonding parameters, such as bonding temperature, bonding pressure, and bonding time, and then uses professional wire bonding equipment to connect the chip pads with the lead frame or the pins on the substrate according to the established parameters. After bonding, plastic sealing is performed to protect the chip and the leads, and then the final packaged product is obtained through rib cutting and molding. However, this traditional packaging method relies on experience to determine the bonding parameters and lacks accurate quantitative analysis and optimization mechanisms, resulting in difficulty in quickly and accurately adjusting the bonding parameters for memory chips of different types and specifications, which in turn leads to reduced packaging quality of memory chips. Therefore, a method for improving the packaging quality of memory chips is needed. Summary of the invention

[0004] The present invention provides a packaging method and system for memory chips based on wire bonding, the main purpose of which is to solve the problem of reduced packaging quality of memory chips.

[0005] To achieve the above object, the present invention provides a packaging method for a memory chip based on wire bonding, comprising:

[0006] Acquire a memory chip to be processed and its corresponding chip specification data, combine the chip specification data and a preset specification threshold, perform front-end processing on the memory chip, and obtain a target memory chip;

[0007] Querying the chip application scenario and wire bonding material corresponding to the target memory chip, evaluating the expected application performance corresponding to the target memory chip according to the chip application scenario, calculating the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and selecting the corresponding most suitable bonding material from the wire bonding materials based on the bonding matching coefficient;

[0008] Collecting an initial chip image corresponding to the target memory chip, marking chip solder joints in the initial chip image, identifying wire bonding origins, wire bonding endpoints, and middle solder joints in the chip solder joints according to preset bonding requirements, and calculating solder joint circularity corresponding to the middle solder joint based on the initial chip image;

[0009] According to the roundness of the solder joint, determine the best solder joint from the middle solder joints, plan the wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the best solder joint, analyze the physical characterization property corresponding to each solder joint in the best solder joint according to the initial image of the chip, and set the bonding process parameters corresponding to the target memory chip based on the physical characterization property;

[0010] In combination with the wire bonding path, the most suitable bonding material and the bonding process parameters, a bonding packaging process is performed on the target memory chip to obtain a packaged memory chip.

[0011] Optionally, the combining the chip specification data and a preset specification threshold to perform front-end processing on the memory chip to obtain a target memory chip includes:

[0012] Identify the specification index corresponding to the specification threshold, and perform data filtering processing on the chip specification data based on the specification index to obtain filtered specification data;

[0013] Performing data calibration processing on the filtering specification data to obtain calibration specification data;

[0014] Performing standardization processing on the calibration specification data to obtain standard specification data;

[0015] Calculate the chip yield rate corresponding to the memory chip by combining the standard specification data and the specification threshold;

[0016] According to the chip yield rate, the memory chip is processed at the front end to obtain a target memory chip.

[0017] Optionally, the combining the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the memory chip includes:

[0018] Read the specification reference value in the standard specification data, and calculate the specification weight corresponding to the specification reference value;

[0019] In combination with the specification reference value, the specification threshold value and the specification weight, the chip yield rate corresponding to the memory chip can be calculated by the following formula:

[0020]

[0021] Among them, A represents the chip yield rate corresponding to the memory chip, B a represents the ath reference value in the specification reference value, a represents the serial number of the specification reference value, Q represents the number of specification reference values, B , a Indicates the specification threshold corresponding to the ath benchmark value in the specification benchmark value, D a Indicates the specification weight corresponding to the ath benchmark value in the specification benchmark value.

[0022] Optionally, the evaluating expected application performance corresponding to the target storage chip according to the chip application scenario includes:

[0023] Scheduling chip load data corresponding to the target storage chip in the chip application scenario;

[0024] Extracting labels from the chip load data to obtain load labels;

[0025] Based on the chip load data, calculating the chip load rate corresponding to the load tag;

[0026] Based on the chip load rate, the actual application performance corresponding to the target storage chip is evaluated.

[0027] Optionally, the calculating the bonding fit coefficient between the target memory chip and the wire bonding material based on the expected application performance includes:

[0028] Decomposing the expected application performance into indicators to obtain performance indicators, and screening out key performance indicators from the performance indicators;

[0029] Analyzing the indicator factors corresponding to the key performance indicators, and querying the material characteristic attributes corresponding to the wire bonding material;

[0030] Calculating a coupling index between the index factor and the material characteristic attribute;

[0031] The bonding fit coefficient between the target memory chip and the wire bonding material is calculated in combination with the coupling index and the material characteristic attribute.

[0032] Optionally, the calculating a coupling index between the indicator factor and the material characteristic attribute includes:

[0033] Performing vector processing on the index factors and the material characteristic attributes respectively to obtain an index factor vector and a characteristic attribute vector;

[0034] According to the indicator factor vector and the characteristic attribute vector, respectively calculating the mean values ​​corresponding to the indicator factors and the material characteristic attributes, to obtain the factor vector mean and the attribute vector mean;

[0035] Combining the index factor vector, the characteristic attribute vector, the factor vector mean and the attribute vector mean, the coupling index between the index factor and the material characteristic attribute can be calculated by the following formula:

[0036]

[0037] Among them, E represents the coupling index between the index factor and the material characteristic property, F b represents the bth vector in the indicator factor vector, represents the mean of the factor vector, b represents the serial number corresponding to the indicator factor vector, n represents the number of vectors corresponding to the indicator factor vector, H d represents the dth vector in the feature attribute vector, represents the mean of the attribute vector, d represents the serial number corresponding to the feature attribute vector, and m represents the number of vectors corresponding to the feature attribute vector.

[0038] Optionally, the calculating, based on the initial chip image, the solder joint circularity corresponding to the middle solder joint includes:

[0039] Marking a solder joint image corresponding to the middle solder joint from the initial chip image;

[0040] Identify the edge pixels of the welding spot in the welding spot image, and calculate the pixel distance between the edge pixels of the welding spot;

[0041] Based on the pixel distance, determining a perimeter of a welding spot corresponding to the middle welding spot;

[0042] Based on the welding point image, counting the number of welding point pixels corresponding to the middle welding point;

[0043] Based on the number of pixels of the welding points, determining the welding point area corresponding to the middle welding point;

[0044] Combining the solder joint perimeter and the solder joint area, the solder joint circularity corresponding to the middle solder joint can be calculated by the following formula:

[0045]

[0046] Among them, γ represents the roundness of the solder joint corresponding to the middle solder joint, Se represents the solder joint area corresponding to the e-th solder joint in the middle solder joints, e represents the serial number corresponding to the middle solder joint, and Ge represents the solder joint circumference corresponding to the e-th solder joint in the middle solder joints.

[0047] Optionally, determining the optimal welding point from the intermediate welding points according to the roundness of the welding point includes:

[0048] Identify a candidate welding point set corresponding to each welding point in the intermediate welding points, and count the number of welding points corresponding to the candidate welding point set;

[0049] Based on the candidate welding point set, calculating the candidate welding stroke corresponding to the intermediate welding point;

[0050] In combination with the number of solder joints and the total distance between solder joints, setting the solder joint priority corresponding to the middle solder joint;

[0051] The optimal welding spot is determined from the intermediate welding spots in combination with the welding spot circularity and the welding spot priority.

[0052] Optionally, analyzing the physical characterization property corresponding to each solder joint in the optimal solder joint according to the initial chip image includes:

[0053] Extracting the image corresponding to the optimal solder joint from the initial chip image to obtain the optimal solder joint image;

[0054] Performing denoising processing on the optimal solder joint image to obtain a denoised solder joint image;

[0055] Performing grayscale processing on the denoised solder joint image to obtain a grayscale solder joint image;

[0056] Based on the grayscale solder joint image, calculating the solder joint glossiness corresponding to the optimal solder joint;

[0057] Constructing a solder joint grayscale co-occurrence matrix corresponding to the grayscale solder joint image, and analyzing a solder joint texture representation corresponding to the optimal solder joint based on the solder joint grayscale co-occurrence matrix;

[0058] The glossiness of the weld point and the texture characterization of the weld point are combined to generate a physical characterization attribute corresponding to each weld point in the optimal weld point.

[0059] A packaging system for memory chips based on wire bonding, characterized in that the system comprises:

[0060] A chip processing module is used to obtain a memory chip to be processed and its corresponding chip specification data, and to perform front-end processing on the memory chip in combination with the chip specification data and a preset specification threshold to obtain a target memory chip;

[0061] A material screening module, used to query the chip application scenario and wire bonding material corresponding to the target memory chip, evaluate the expected application performance corresponding to the target memory chip according to the chip application scenario, calculate the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and screen out the corresponding most suitable bonding material from the wire bonding material based on the bonding matching coefficient;

[0062] A solder joint circularity calculation module is used to collect an initial chip image corresponding to the target memory chip, mark the chip solder joints in the initial chip image, identify the wire bonding origin, wire bonding endpoint and middle solder joint in the chip solder joints according to preset bonding requirements, and calculate the solder joint circularity corresponding to the middle solder joint based on the initial chip image;

[0063] A process parameter setting module, for determining an optimal solder joint from the intermediate solder joints according to the solder joint circularity, planning a wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the optimal solder joint, analyzing the physical characterization attribute corresponding to each solder joint in the optimal solder joint according to the chip initial image, and setting the bonding process parameters corresponding to the target memory chip based on the physical characterization attribute;

[0064] The packaging processing module is used to perform bonding packaging processing on the target memory chip in combination with the wire bonding path, the most suitable bonding material and the bonding process parameters to obtain a packaged memory chip.

[0065] Compared with the problems described in the background technology, the present invention combines the chip specification data and the preset specification threshold to perform front-end processing on the memory chip, and can process the chips that do not meet the requirements in the memory chip, thereby improving the chip yield of the memory chip and providing accuracy for subsequent analysis of the memory chip. The present invention evaluates the expected application performance corresponding to the target memory chip according to the chip application scenario, and can understand the performance requirements that the target memory chip needs to achieve in actual use through the expected application performance, thereby laying an important foundation for the subsequent calculation of the bonding fit coefficient between the target memory chip and the wire bonding material. The present invention can obtain a visual image of the target memory chip by collecting the initial chip image corresponding to the target memory chip, marking The chip solder joints in the chip initial image are then accurately obtained to obtain the coordinate position of each solder joint in the chip initial image. According to the preset bonding requirements, the wire bonding origin, wire bonding endpoint and intermediate solder joint are identified in the chip solder joints, which provides convenience for the subsequent calculation of the solder joint circularity corresponding to the intermediate solder joint. The present invention determines the optimal solder joint from the intermediate solder joint according to the solder joint circularity, and can obtain the most suitable soldering point in the intermediate solder joint, thereby improving the overall quality and reliability after the chip packaging is completed. The present invention combines the wire bonding path, the optimal bonding material and the bonding process parameters to perform the bonding packaging process on the target memory chip, which can improve the bonding packaging quality of the target memory chip and enhance the reliability and stability of the target memory chip. Therefore, the present invention proposes a packaging method and system for memory chips based on wire bonding, so as to improve the packaging quality of memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 A schematic flow chart of a method for packaging a memory chip based on wire bonding provided in one embodiment of the present invention;

[0067] Figure 2 A functional module diagram of a packaging system for a memory chip based on wire bonding provided in one embodiment of the present invention.

[0068] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0069] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0070] The embodiment of the present application provides a packaging method for a memory chip based on wire bonding. The execution subject of the packaging method for a memory chip based on wire bonding includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the packaging method for a memory chip based on wire bonding can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0071] Embodiment 1:

[0072] Reference Figure 1 FIG. 1 is a flow chart of a method for packaging a memory chip based on wire bonding according to an embodiment of the present invention. In this embodiment, the method for packaging a memory chip based on wire bonding includes:

[0073] S1. Obtain a memory chip to be processed and its corresponding chip specification data, combine the chip specification data and a preset specification threshold, perform front-end processing on the memory chip, and obtain a target memory chip.

[0074] The present invention combines the chip specification data and the preset specification threshold to perform front-end processing on the memory chip, and can process the chips that do not meet the requirements in the memory chip, thereby improving the chip yield of the memory chip and providing accuracy for subsequent analysis of the memory chip. It should be explained that the memory chip is a semiconductor device with specific storage functions and circuit structures, and the chip specification data is quantitative characteristic information of the memory chip in terms of physical size, pin layout, storage capacity, operating voltage, read and write speed, etc. The target memory chip is a chip obtained after processing the chips that do not meet the specification threshold in the memory chip.

[0075] In detail, the combining the chip specification data and the preset specification threshold to perform front-end processing on the memory chip to obtain the target memory chip includes:

[0076] Identify the specification index corresponding to the specification threshold, and perform data filtering processing on the chip specification data based on the specification index to obtain filtered specification data;

[0077] Performing data calibration processing on the filtering specification data to obtain calibration specification data;

[0078] Performing standardization processing on the calibration specification data to obtain standard specification data;

[0079] Calculate the chip yield rate corresponding to the memory chip by combining the standard specification data and the specification threshold;

[0080] According to the chip yield rate, the memory chip is processed at the front end to obtain a target memory chip.

[0081] It should be explained that the specification indicator is the specification type corresponding to the specification threshold, the filtered specification data is the data obtained by removing the data irrelevant to the specification indicator in the chip specification data, the calibration specification data is the data obtained after repairing the data corresponding to the acquisition error in the filtered specification data, the standard specification data is the standard specification data unified by the calibration specification data, and the chip yield rate represents the proportion of the number of storage chips that meet the production standard conditions.

[0082] Furthermore, the specification index corresponding to the specification threshold can be identified by OCR recognition technology; the data filtering processing of the chip specification data can be implemented by a filtering function, and the filtering function is compiled by a programming language; the data calibration processing of the filtered specification data can be implemented by the mean value substitution method; the standardization processing of the calibrated specification data can be implemented by the Z-score standardization method; when the chip yield is lower than the set value, the storage chip is processed at the front end to obtain the target storage chip, and the set value can be set to 80%, or it can be set according to the actual application scenario.

[0083] Further, as an optional embodiment of the present invention, the combining the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the memory chip includes:

[0084] Read the specification reference value in the standard specification data, and calculate the specification weight corresponding to the specification reference value;

[0085] In combination with the specification reference value, the specification threshold value and the specification weight, the chip yield rate corresponding to the memory chip can be calculated by the following formula:

[0086]

[0087] Among them, A represents the chip yield rate corresponding to the memory chip, B a represents the ath reference value in the specification reference value, a represents the serial number of the specification reference value, Q represents the number of specification reference values, B , a Indicates the specification threshold corresponding to the ath benchmark value in the specification benchmark value, D a Indicates the specification weight corresponding to the ath benchmark value in the specification benchmark value.

[0088] It should be explained that the specification reference value is a specific numerical value in the standard specification data, and the specification weight indicates the importance corresponding to the specification reference value. Furthermore, the specification reference value in the standard specification data can be read through a data interface, such as HTTP, TCP, etc.; the calculation of the specification weight corresponding to the specification reference value can be achieved through factor analysis.

[0089] S2. Query the chip application scenario and wire bonding material corresponding to the target memory chip, evaluate the expected application performance corresponding to the target memory chip according to the chip application scenario, (scenario condition) calculate the bonding matching coefficient (material performance parameters, material proportion) between the target memory chip and the wire bonding material based on the expected application performance, and select the corresponding most suitable bonding material from the wire bonding material based on the bonding matching coefficient.

[0090] The present invention evaluates the expected application performance corresponding to the target memory chip according to the chip application scenario, and the performance requirements that the target memory chip needs to achieve in actual use can be understood through the expected application performance, thereby laying an important foundation for the subsequent calculation of the bonding matching coefficient between the target memory chip and the wire bonding material. It should be explained that the chip application scenario is the use environment and conditions corresponding to the target memory chip, including but not limited to the specific equipment and system used, and the functions undertaken in these equipment or systems, the performance requirements that need to be met, the operating temperature range, the power supply conditions, the data transmission rate requirements, the storage capacity requirements and other related factors. The expected application performance is a comprehensive description of the various performance indicators and performances achieved by the target memory chip; further, the chip application scenario and the wire bonding material corresponding to the target memory chip can be queried through the official website of the packaged chip; based on the bonding matching coefficient, the corresponding most suitable bonding material is screened out from the wire bonding material, such as selecting the material with the largest bonding matching coefficient as the most suitable bonding material, because the material has the highest degree of adaptation to the target memory chip in terms of the expected application performance.

[0091] Specifically, the evaluating the expected application performance corresponding to the target storage chip according to the chip application scenario includes:

[0092] Scheduling chip load data corresponding to the target storage chip in the chip application scenario;

[0093] Extracting labels from the chip load data to obtain load labels;

[0094] Based on the chip load data, calculating the chip load rate corresponding to the load tag;

[0095] Based on the chip load rate, the actual application performance corresponding to the target storage chip is evaluated.

[0096] It should be explained that the chip load data is the historical usage data corresponding to the target storage chip in the chip application scenario, the load label is the load type corresponding to the chip load number, such as read and write speed and computing speed, etc., and the chip load rate indicates the usage level corresponding to the load label.

[0097] Furthermore, the chip load data corresponding to the target storage chip in the chip application scenario can be scheduled in a chip data repository, and the chip data repository is a library for storing usage data of the target storage chip; the label extraction of the chip load data can be achieved through a label extraction tool; based on the chip load data, the chip load rate corresponding to the load label can be calculated by a data traffic statistics method, and the calculation formula is: chip load rate = (actual data traffic / rated data traffic) × 100%; based on the chip load rate, the actual application performance corresponding to the target storage chip is evaluated, and according to the performance characteristics of the chip and the requirements of the application scenario, the chip load rate is divided into different levels, such as low load (0%-30%), medium load (30%-70%), high load (70%-100%), etc., so as to divide the actual application performance of the target storage chip into low load performance, medium load performance and high load performance, etc.

[0098] The present invention calculates the bonding fit coefficient between the target memory chip and the wire bonding material based on the expected application performance, thereby understanding the degree of fit between the target memory chip and the wire bonding material, thereby laying a foundation for subsequently screening out the corresponding most suitable bonding material from the wire bonding materials. It should be explained that the bonding fit coefficient represents the degree of fit between the target memory chip and the wire bonding material.

[0099] Specifically, the step of calculating the bonding fit coefficient between the target memory chip and the wire bonding material based on the expected application performance includes:

[0100] Decomposing the expected application performance into indicators to obtain performance indicators, and screening out key performance indicators from the performance indicators;

[0101] Analyzing the indicator factors corresponding to the key performance indicators, and querying the material characteristic attributes corresponding to the wire bonding material;

[0102] Calculating a coupling index between the index factor and the material characteristic attribute;

[0103] The bonding fit coefficient between the target memory chip and the wire bonding material is calculated in combination with the coupling index and the material characteristic attribute.

[0104] It should be explained that the performance index is a specific subdivision of the expected application performance, such as storage capacity. The key performance index is the part of the performance index that plays a key role in the overall application. The index factor is the specific condition or factor corresponding to the key performance index that affects its achievement, such as external or internal conditions such as operating temperature and signal frequency that affect the read and write speed. The material characteristic attribute is the inherent property characteristics corresponding to the wire bonding material, such as electrical conductivity, thermal conductivity, mechanical strength and other intrinsic characteristics that determine the performance of the material. The coupling index represents the correlation and mutual influence between the index factor and the material characteristic attribute. Furthermore, the index decomposition of the expected application performance can be achieved through the hierarchical analysis method; the key performance indicators can be screened out from the performance indicators through the principal component analysis method; the analysis of the index factors corresponding to the key performance indicators can be achieved through the cause-and-effect analysis method; the material characteristic attribute query corresponding to the wire bonding material can be achieved through the material performance database query; the coupling index and the quantized value corresponding to the material characteristic attribute are multiplied and summed to obtain the bonding fit coefficient between the target storage chip and the wire bonding material.

[0105] Further, as an optional embodiment of the present invention, the calculating the coupling index between the indicator factor and the material characteristic attribute includes:

[0106] Performing vector processing on the index factors and the material characteristic attributes respectively to obtain an index factor vector and a characteristic attribute vector;

[0107] According to the indicator factor vector and the characteristic attribute vector, respectively calculating the mean values ​​corresponding to the indicator factors and the material characteristic attributes, to obtain the factor vector mean and the attribute vector mean;

[0108] Combining the index factor vector, the characteristic attribute vector, the factor vector mean and the attribute vector mean, the coupling index between the index factor and the material characteristic attribute can be calculated by the following formula:

[0109]

[0110] Among them, E represents the coupling index between the index factor and the material characteristic property, F b represents the bth vector in the indicator factor vector, represents the mean of the factor vector, b represents the serial number corresponding to the indicator factor vector, n represents the number of vectors corresponding to the indicator factor vector, H d represents the dth vector in the feature attribute vector, represents the mean of the attribute vector, d represents the serial number corresponding to the feature attribute vector, and m represents the number of vectors corresponding to the feature attribute vector.

[0111] It should be explained that the indicator factor vector and the characteristic attribute vector are respectively the expression vectors corresponding to the indicator factors and the material characteristic attributes; further, the vectorization processing of the indicator factors and the material characteristic attributes can be achieved through the word vector model method; the mean corresponding to the indicator factors and the material characteristic attributes can be achieved through the average function.

[0112] S3. Collect an initial chip image corresponding to the target memory chip, mark the chip solder joints in the initial chip image, identify the wire bonding origin, wire bonding endpoint and middle solder joints in the chip solder joints according to preset bonding requirements, and calculate the solder joint roundness corresponding to the middle solder joint based on the initial chip image.

[0113] The present invention can obtain a visualized image of the target memory chip by collecting the chip initial image corresponding to the target memory chip, mark the chip solder joints in the chip initial image, and then accurately obtain the coordinate position of each solder joint in the chip initial image, and identify the wire bonding origin, wire bonding endpoint and middle solder joint in the chip solder joint according to the preset bonding requirements, so as to facilitate the subsequent calculation of the solder joint circularity corresponding to the middle solder joint. It should be explained that the chip initial image is a visualized image corresponding to the target memory chip, and the chip solder joint is a point used for welding in the chip initial image. The preset bonding requirements are before performing the bonding operation between the chip and components such as the wire bonding. According to factors such as specific application scenarios, chip performance requirements, process standards, and related technical specifications, a series of conditions and standards that should be achieved for the bonding process and bonding effect are pre-set. The wire bonding origin and the wire bonding endpoint are the starting welding point and the ending welding point in the chip solder joint, and the intermediate solder joint is the solder joint between the wire bonding origin and the wire bonding endpoint. Furthermore, the acquisition of the chip initial image corresponding to the target storage chip can be achieved by industrial camera equipment; the marking of the chip solder joints in the chip initial image can be achieved by X-ray detection equipment; the wire bonding origin and the wire bonding endpoint can be identified in the chip solder joint by manual processing.

[0114] Specifically, the calculating the solder joint circularity corresponding to the middle solder joint based on the chip initial image includes:

[0115] Marking a solder joint image corresponding to the middle solder joint from the initial chip image;

[0116] Identify the edge pixels of the welding spot in the welding spot image, and calculate the pixel distance between the edge pixels of the welding spot;

[0117] Based on the pixel distance, determining a perimeter of a welding spot corresponding to the middle welding spot;

[0118] Based on the welding point image, counting the number of welding point pixels corresponding to the middle welding point;

[0119] Based on the number of pixels of the welding points, determining the welding point area corresponding to the middle welding point;

[0120] Combining the solder joint perimeter and the solder joint area, the solder joint circularity corresponding to the middle solder joint can be calculated by the following formula:

[0121]

[0122] Among them, γ represents the roundness of the solder joint corresponding to the middle solder joint, Se represents the solder joint area corresponding to the e-th solder joint in the middle solder joints, e represents the serial number corresponding to the middle solder joint, and Ge represents the solder joint circumference corresponding to the e-th solder joint in the middle solder joints.

[0123] It should be explained that the solder joint image is the image corresponding to the middle solder joint in the initial image of the chip, the solder joint edge pixel is the pixel about the edge position of the middle solder joint in the solder joint image, and the solder joint pixel number is the number of regional pixels corresponding to the middle solder joint. Further, the solder joint edge pixels in the solder joint image can be identified by an edge detection algorithm, such as the Canny edge detection algorithm; the pixel distance between the solder joint edge pixels can be calculated by the Euclidean distance algorithm; the pixel distances are summed to obtain the solder joint perimeter corresponding to the middle solder joint; the solder joint pixel number of the solder joint image can be counted by image processing software, such as Adobe Photoshop software; the solder joint pixel number is the solder joint area corresponding to the middle solder joint.

[0124] S4. Determine the best solder joint from the middle solder joints according to the roundness of the solder joints, plan the wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the best solder joint, analyze the physical characterization properties corresponding to each solder joint in the best solder joint according to the chip initial image, and set the bonding process parameters corresponding to the target memory chip based on the physical characterization properties.

[0125] The present invention determines the optimal solder joint from the intermediate solder joints according to the roundness of the solder joints, so as to obtain the most suitable solder joint position among the intermediate solder joints, thereby improving the overall quality and reliability after the chip packaging is completed. It should be explained that the optimal solder joint is the optimal solder joint position among the intermediate solder joints.

[0126] In detail, determining the optimal welding point from the intermediate welding points according to the roundness of the welding point includes:

[0127] Identify a candidate welding point set corresponding to each welding point in the intermediate welding points, and count the number of welding points corresponding to the candidate welding point set;

[0128] Based on the candidate welding point set, calculating the candidate welding stroke corresponding to the intermediate welding point;

[0129] In combination with the number of solder joints and the total distance between solder joints, setting the solder joint priority corresponding to the middle solder joint;

[0130] The optimal welding spot is determined from the intermediate welding spots in combination with the welding spot circularity and the welding spot priority.

[0131] It should be explained that the candidate weld point set is a set of candidate weld points corresponding to each weld point in the intermediate weld point, the number of weld points is the total number of candidate weld points corresponding to the candidate weld points in the candidate weld point set, the candidate welding stroke is the sum of the distances from the intermediate weld point to each point in the candidate weld point set, and the weld point priority indicates the priority corresponding to the intermediate weld point.

[0132] Furthermore, the candidate solder point set corresponding to each solder point in the intermediate solder points can be identified by a method based on the circuit connection relationship. By viewing the detailed circuit diagram of the chip, other solder points that have similar functions in electrical connection with each intermediate solder point or are in the same signal path are determined. These solder points can constitute the candidate solder point set. For example, in a digital circuit, if an intermediate solder point is a connection point of a data bus, then other solder points on the same bus can be used as candidate solder points when the intermediate solder point fails. By analyzing the line connection and signal flow in the circuit diagram, this candidate solder point relationship based on circuit function can be clearly identified; the distance between the intermediate solder point and each solder point in the candidate solder point set is calculated, and the distances are summed to obtain the corresponding candidate welding stroke; the solder point priority corresponding to the intermediate solder point is set in combination with the number of solder points and the total distance of solder points, such as the number of solder points of the intermediate solder point 1 is 4 and the total distance of solder points is 10. meters, the corresponding priority score is 14, the number of solder joints of the middle solder joint 2 is 5, and the total distance of solder joints is 12 meters, the corresponding priority score is 17, the number of solder joints of the middle solder joint 3 is 5, and the total distance of solder joints is 14 meters, the corresponding priority score is 19, then the solder joint priorities corresponding to the middle solder joint 1, the middle solder joint 2, and the middle solder joint 3 are low, medium, and high respectively; combined with the solder joint circularity and the solder joint priority, the optimal solder joint is determined from the middle solder joints. If there is a group of middle solder joints, they are first screened according to the solder joint circularity, among which the circularity of solder joint A is 0.9, which is closer to the ideal circle among these solder joints, preliminarily highlighting its shape advantage. At the same time, its solder joint priority is higher. Considering the comprehensive circularity and priority, solder joint A stands out and is determined as the optimal solder joint. It achieves a good balance in terms of shape regularity, functional importance, connection stability, etc., and can provide a better basis for subsequent operations such as wire bonding.

[0133] The present invention plans the wire bonding path corresponding to the target memory chip by combining the wire bonding origin, the wire bonding endpoint and the optimal solder joint, thereby providing an accurate, efficient and reliable connection blueprint and process implementation guidance for subsequent chip packaging; by analyzing the physical characterization attributes corresponding to each solder joint in the optimal solder joint, the characteristic properties such as the physical state, structure and performance corresponding to the optimal solder joint can be understood, thereby improving the accuracy of setting the subsequent bonding process parameters corresponding to the target memory chip. It should be explained that the wire bonding path is a specific connection track corresponding to the target memory chip starting from the wire bonding origin, passing through the optimal solder joint, and finally reaching the wire bonding endpoint. The physical characterization attribute is the physical characteristic property of each solder joint in the optimal solder joint. Further, in combination with the wire bonding origin, the wire bonding endpoint and the optimal solder joint, the wire bonding path corresponding to the target memory chip can be planned by a path planning algorithm, such as a Dijkstra algorithm.

[0134] Specifically, analyzing the physical characterization attributes corresponding to each solder joint in the optimal solder joint according to the initial chip image includes:

[0135] Extracting the image corresponding to the optimal solder joint from the initial chip image to obtain the optimal solder joint image;

[0136] Performing denoising processing on the optimal solder joint image to obtain a denoised solder joint image;

[0137] Performing grayscale processing on the denoised solder joint image to obtain a grayscale solder joint image;

[0138] Based on the grayscale solder joint image, calculating the solder joint glossiness corresponding to the optimal solder joint;

[0139] Constructing a solder joint grayscale co-occurrence matrix corresponding to the grayscale solder joint image, and analyzing a solder joint texture representation corresponding to the optimal solder joint based on the solder joint grayscale co-occurrence matrix;

[0140] The glossiness of the weld point and the texture characterization of the weld point are combined to generate a physical characterization attribute corresponding to each weld point in the optimal weld point.

[0141] It should be explained that the optimal solder joint image is the image corresponding to the optimal solder joint in the initial image of the chip, the denoised solder joint image is the image obtained after removing the noise interference in the optimal solder joint image, the grayscale solder joint image is the image of the denoised solder joint image expressed by only a single color, the solder joint glossiness indicates the smoothness corresponding to the optimal solder joint, the solder joint grayscale co-occurrence matrix is ​​the texture description matrix corresponding to the grayscale solder joint image, and the solder joint texture characterization is the texture characteristic corresponding to the optimal solder joint.

[0142] Furthermore, the image corresponding to the optimal solder joint can be extracted from the initial image of the chip by a segmentation tool to obtain the optimal solder joint image, and the segmentation tool is compiled by a scripting language, such as JS scripting language; the denoising processing of the optimal solder joint image can be implemented by a low-pass filter; the grayscale processing of the denoised solder joint image can be implemented by the average method, the pixel values ​​of the red, green and blue channels of the color image are added respectively, and then divided by 3, the average value obtained is used as the corresponding grayscale value, and the grayscale value replaces the corresponding pixel value to obtain the grayscale solder joint image; the grayscale standard deviation corresponding to the grayscale solder joint image is calculated, and the gloss of the solder joint corresponding to the optimal solder joint is determined according to the grayscale standard deviation, the smaller the grayscale standard deviation, the higher the gloss of the solder joint; the solder joint grayscale co-occurrence matrix corresponding to the grayscale solder joint image can be constructed by a matrix function, such as a zero matrix function; the characteristic parameters corresponding to the solder joint grayscale co-occurrence matrix can be calculated by a corresponding calculation formula, and the solder joint texture characterization corresponding to the optimal solder joint is analyzed according to the characteristic parameters, such as contrast, energy and homogeneity and other characteristic parameters.

[0143] The present invention sets the bonding process parameters corresponding to the target memory chip based on the physical characterization attributes, so as to make the bonding process more suitable for the target memory chip and improve the chip packaging quality and performance. It should be explained that the bonding process parameters are a series of key factors that need to be controlled and adjusted during the wire bonding process of the target memory chip, such as bonding speed and bonding pressure. Furthermore, based on the physical characterization attributes, the bonding process parameters corresponding to the target memory chip are set. If the glossiness of the solder joints in the physical characterization attributes is high and the texture characterization shows uniform and dense, it means that the welding quality is good, and the bonding temperature and pressure can be appropriately reduced to reduce the potential damage to the chip while ensuring the connection reliability. If the glossiness is low and the texture is rough and messy, it may be necessary to increase the bonding power and time to promote the full fusion of the bonding materials to improve the connection effect and stability.

[0144] S5. Combining the wire bonding path, the most suitable bonding material and the bonding process parameters, perform bonding packaging processing on the target memory chip to obtain a packaged memory chip.

[0145] The present invention combines the wire bonding path, the optimal bonding material and the bonding process parameters to perform bonding packaging processing on the target memory chip, thereby improving the bonding packaging quality of the target memory chip and enhancing the reliability and stability of the target memory chip.

[0146] Compared with the problems described in the background technology, the present invention combines the chip specification data and the preset specification threshold to perform front-end processing on the memory chip, and can process the chips that do not meet the requirements in the memory chip, thereby improving the chip yield of the memory chip and providing accuracy for subsequent analysis of the memory chip. The present invention evaluates the expected application performance corresponding to the target memory chip according to the chip application scenario, and can understand the performance requirements that the target memory chip needs to achieve in actual use through the expected application performance, thereby laying an important foundation for the subsequent calculation of the bonding fit coefficient between the target memory chip and the wire bonding material. The present invention can obtain a visual image of the target memory chip by collecting the initial chip image corresponding to the target memory chip, marking The chip solder joints in the chip initial image are then accurately obtained to obtain the coordinate position of each solder joint in the chip initial image. According to the preset bonding requirements, the wire bonding origin, wire bonding endpoint and intermediate solder joint are identified in the chip solder joints, which provides convenience for the subsequent calculation of the solder joint circularity corresponding to the intermediate solder joint. The present invention determines the optimal solder joint from the intermediate solder joint according to the solder joint circularity, and can obtain the most suitable soldering point in the intermediate solder joint, thereby improving the overall quality and reliability after the chip packaging is completed. The present invention combines the wire bonding path, the optimal bonding material and the bonding process parameters to perform the bonding packaging process on the target memory chip, which can improve the bonding packaging quality of the target memory chip and enhance the reliability and stability of the target memory chip. Therefore, the present invention proposes a packaging method for memory chips based on wire bonding to improve the packaging quality of memory chips.

[0147] Embodiment 2:

[0148] like Figure 2 1 is a functional module diagram of a packaging system for a memory chip based on wire bonding provided by an embodiment of the present invention.

[0149] The packaging system 100 for implementing a memory chip based on wire bonding according to the present invention can be installed in an electronic device. According to the functions implemented, the packaging system 100 for implementing a memory chip based on wire bonding can include a chip processing module 101, a material screening module 102, a solder joint circularity calculation module 103, a process parameter setting module 104 and a packaging processing module 105. The module described in the present invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0150] In this embodiment, the functions of each module / unit are as follows:

[0151] The chip processing module 101 is used to obtain the memory chip to be processed and its corresponding chip specification data, and to perform front-end processing on the memory chip in combination with the chip specification data and a preset specification threshold to obtain a target memory chip;

[0152] The material screening module 102 is used to query the chip application scenario and wire bonding material corresponding to the target memory chip, evaluate the expected application performance corresponding to the target memory chip according to the chip application scenario, calculate the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and screen out the corresponding most suitable bonding material from the wire bonding materials based on the bonding matching coefficient;

[0153] The solder joint circularity calculation module 103 is used to collect the chip initial image corresponding to the target memory chip, mark the chip solder joints in the chip initial image, identify the wire bonding origin, wire bonding endpoint and middle solder joint in the chip solder joint according to the preset bonding requirements, and calculate the solder joint circularity corresponding to the middle solder joint based on the chip initial image;

[0154] The process parameter setting module 104 is used to determine the optimal solder joint from the intermediate solder joints according to the solder joint circularity, plan the wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the optimal solder joint, analyze the physical characterization attribute corresponding to each solder joint in the optimal solder joint according to the chip initial image, and set the bonding process parameters corresponding to the target memory chip based on the physical characterization attribute;

[0155] The packaging processing module 105 is used to perform bonding packaging processing on the target memory chip in combination with the wire bonding path, the optimal bonding material and the bonding process parameters to obtain a packaged memory chip.

[0156] In detail, each module described in the packaging system 100 for implementing a memory chip based on wire bonding described in the embodiment of the present application is used in the same manner as described above. Figure 1 The same technical means as the packaging method of memory chip based on wire bonding described in the specification and the like can produce the same technical effect, which will not be repeated here.

[0157] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for packaging a memory chip based on wire bonding, characterized in that: The method comprises: Acquire a memory chip to be processed and its corresponding chip specification data, combine the chip specification data and a preset specification threshold, perform front-end processing on the memory chip, and obtain a target memory chip; Querying the chip application scenario and wire bonding material corresponding to the target memory chip, evaluating the expected application performance corresponding to the target memory chip according to the chip application scenario, calculating the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and selecting the corresponding most suitable bonding material from the wire bonding materials based on the bonding matching coefficient; Collecting an initial chip image corresponding to the target memory chip, marking chip solder joints in the initial chip image, identifying wire bonding origins, wire bonding endpoints, and middle solder joints in the chip solder joints according to preset bonding requirements, and calculating solder joint circularity corresponding to the middle solder joint based on the initial chip image; According to the roundness of the solder joint, determine the best solder joint from the middle solder joints, plan the wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the best solder joint, analyze the physical characterization property corresponding to each solder joint in the best solder joint according to the initial image of the chip, and set the bonding process parameters corresponding to the target memory chip based on the physical characterization property; In combination with the wire bonding path, the most suitable bonding material and the bonding process parameters, a bonding packaging process is performed on the target memory chip to obtain a packaged memory chip.

2. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The combining the chip specification data and the preset specification threshold to perform front-end processing on the memory chip to obtain a target memory chip includes: Identify the specification index corresponding to the specification threshold, and perform data filtering processing on the chip specification data based on the specification index to obtain filtered specification data; Performing data calibration processing on the filtering specification data to obtain calibration specification data; Performing standardization processing on the calibration specification data to obtain standard specification data; Calculate the chip yield rate corresponding to the memory chip by combining the standard specification data and the specification threshold; According to the chip yield rate, the memory chip is processed at the front end to obtain a target memory chip.

3. The method for packaging a memory chip based on wire bonding according to claim 2, characterized in that: The step of combining the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the memory chip includes: Read the specification reference value in the standard specification data, and calculate the specification weight corresponding to the specification reference value; In combination with the specification reference value, the specification threshold value and the specification weight, the chip yield rate corresponding to the memory chip can be calculated by the following formula: Among them, A represents the chip yield rate corresponding to the memory chip, B a represents the ath reference value in the specification reference value, a represents the serial number of the specification reference value, Q represents the number of specification reference values, B , a Indicates the specification threshold corresponding to the ath benchmark value in the specification benchmark value, D a Indicates the specification weight corresponding to the ath benchmark value in the specification benchmark value.

4. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The step of evaluating the expected application performance corresponding to the target storage chip according to the chip application scenario includes: Scheduling chip load data corresponding to the target storage chip in the chip application scenario; Extracting labels from the chip load data to obtain load labels; Based on the chip load data, calculating the chip load rate corresponding to the load tag; Based on the chip load rate, the actual application performance corresponding to the target storage chip is evaluated.

5. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The step of calculating a bonding fit coefficient between the target memory chip and the wire bonding material based on the expected application performance includes: Decomposing the expected application performance into indicators to obtain performance indicators, and screening out key performance indicators from the performance indicators; Analyzing the indicator factors corresponding to the key performance indicators, and querying the material characteristic attributes corresponding to the wire bonding material; Calculating a coupling index between the index factor and the material characteristic attribute; The bonding fit coefficient between the target memory chip and the wire bonding material is calculated in combination with the coupling index and the material characteristic attribute.

6. The method for packaging a memory chip based on wire bonding according to claim 5, characterized in that: The calculating of the coupling index between the index factor and the material characteristic attribute comprises: Performing vector processing on the index factors and the material characteristic attributes respectively to obtain an index factor vector and a characteristic attribute vector; According to the indicator factor vector and the characteristic attribute vector, respectively calculating the mean values ​​corresponding to the indicator factors and the material characteristic attributes, to obtain the factor vector mean and the attribute vector mean; Combining the index factor vector, the characteristic attribute vector, the factor vector mean and the attribute vector mean, the coupling index between the index factor and the material characteristic attribute can be calculated by the following formula: Among them, E represents the coupling index between the index factor and the material characteristic property, F b represents the bth vector in the indicator factor vector, represents the mean of the factor vector, b represents the serial number corresponding to the indicator factor vector, n represents the number of vectors corresponding to the indicator factor vector, H d represents the dth vector in the feature attribute vector, represents the mean of the attribute vector, d represents the serial number corresponding to the feature attribute vector, and m represents the number of vectors corresponding to the feature attribute vector.

7. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The calculating the solder joint circularity corresponding to the middle solder joint based on the chip initial image includes: Marking a solder joint image corresponding to the middle solder joint from the initial chip image; Identify the edge pixels of the welding spot in the welding spot image, and calculate the pixel distance between the edge pixels of the welding spot; Based on the pixel distance, determining a perimeter of a welding spot corresponding to the middle welding spot; Based on the welding point image, counting the number of welding point pixels corresponding to the middle welding point; Based on the number of pixels of the welding points, determining the welding point area corresponding to the middle welding point; Combining the solder joint perimeter and the solder joint area, the solder joint circularity corresponding to the middle solder joint can be calculated by the following formula: Among them, γ represents the roundness of the solder joint corresponding to the middle solder joint, Se represents the solder joint area corresponding to the e-th solder joint in the middle solder joints, e represents the serial number corresponding to the middle solder joint, and Ge represents the solder joint circumference corresponding to the e-th solder joint in the middle solder joints.

8. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: Determining the optimal welding point from the intermediate welding points according to the welding point circularity includes: Identify a candidate welding point set corresponding to each welding point in the intermediate welding points, and count the number of welding points corresponding to the candidate welding point set; Based on the candidate welding point set, calculating the candidate welding stroke corresponding to the intermediate welding point; In combination with the number of solder joints and the total distance between solder joints, setting the solder joint priority corresponding to the middle solder joint; The optimal welding spot is determined from the intermediate welding spots in combination with the welding spot circularity and the welding spot priority.

9. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The step of analyzing the physical characterization property corresponding to each solder joint in the optimal solder joint according to the initial chip image includes: Extracting the image corresponding to the optimal solder joint from the initial chip image to obtain the optimal solder joint image; Performing denoising processing on the optimal solder joint image to obtain a denoised solder joint image; Performing grayscale processing on the denoised solder joint image to obtain a grayscale solder joint image; Based on the grayscale solder joint image, calculating the solder joint glossiness corresponding to the optimal solder joint; Constructing a solder joint grayscale co-occurrence matrix corresponding to the grayscale solder joint image, and analyzing a solder joint texture representation corresponding to the optimal solder joint based on the solder joint grayscale co-occurrence matrix; The glossiness of the weld point and the texture characterization of the weld point are combined to generate a physical characterization attribute corresponding to each weld point in the optimal weld point.

10. A packaging system for memory chips based on wire bonding, characterized in that: The system comprises: A chip processing module is used to obtain a memory chip to be processed and its corresponding chip specification data, and to perform front-end processing on the memory chip in combination with the chip specification data and a preset specification threshold to obtain a target memory chip; A material screening module, used to query the chip application scenario and wire bonding material corresponding to the target memory chip, evaluate the expected application performance corresponding to the target memory chip according to the chip application scenario, calculate the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and screen out the corresponding most suitable bonding material from the wire bonding material based on the bonding matching coefficient; A solder joint circularity calculation module is used to collect an initial chip image corresponding to the target memory chip, mark the chip solder joints in the initial chip image, identify the wire bonding origin, wire bonding endpoint and middle solder joint in the chip solder joints according to preset bonding requirements, and calculate the solder joint circularity corresponding to the middle solder joint based on the initial chip image; A process parameter setting module, for determining an optimal solder joint from the intermediate solder joints according to the solder joint circularity, planning a wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the optimal solder joint, analyzing the physical characterization attribute corresponding to each solder joint in the optimal solder joint according to the chip initial image, and setting the bonding process parameters corresponding to the target memory chip based on the physical characterization attribute; The packaging processing module is used to perform bonding packaging processing on the target memory chip in combination with the wire bonding path, the most suitable bonding material and the bonding process parameters to obtain a packaged memory chip.

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