Zero-temperature duty ratio adjustable oscillating circuit and adjusting method

Abstract

The invention belongs to the field of chips, and provides a zero-temperature duty ratio adjustable oscillating circuit which comprises a first NAND gate, the first input end of the first NAND gate is connected with the output end of a first NOT gate, the output end of the first NAND gate is connected with the grid electrode of a first NMOS tube, the drain electrode of the first NMOS tube is connected with the grid electrode of a second NMOS tube, the drain electrode of the second NMOS tube is connected with the input end of a second NOT gate, and the output end of the second NOT gate is connected with the grid electrode of a second NMOS tube. The output end of the second NOT gate is connected with the input end of the third NOT gate, the output end of the third NOT gate is connected with the first input end of the second NAND gate, the output end of the second NAND gate is connected with the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the input end of the fourth NOT gate, and the first input end of the fourth NOT gate is connected with the first input end of the second NAND gate. The output end of the fourth NOT gate is connected with the input end of the first NOT gate, the drain electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a current source and a grounding capacitor, and the first input ends of the first NAND gate and the second NAND gate are connected with the first input end and the second input end of a logic control chip. A first output end and a second output end of the logic control chip are respectively connected with a second input end of the first NAND gate and a second input end of the second NAND gate, and the logic control chip is provided with a reset end; on the basis that the chip area is not increased, the output frequency does not change along with the temperature and the power supply voltage, meanwhile, a back-locking mechanism is introduced, and the problem that the output frequency is possibly changed due to uncertain states in the circuit is solved.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a zero-temperature duty cycle adjustable oscillating circuit and an adjusting method. Background Art

[0002] At present, there are two main ways to generate the frequency circuit inside the chip:

[0003] Method 1: Use ring oscillation to generate a fixed frequency, such as Figure 1 As shown, the working principle of the circuit is as follows: a ring oscillation is formed through a 5-stage inverter circuit, the current I1 charges the capacitor C to reach the flip threshold of the next stage inverter circuit, or the current I2 discharges the capacitor C to be lower than the flip threshold of the next stage inverter circuit, and the ring oscillation circuit is continuously flipped.

[0004] Method 2: If Figure 2 The figure shows an oscillating circuit of a comparator plus current charging mode. When the comparator output is high, the capacitor C0 is charged by the current Ic. When the voltage reaches Vref1, the comparator output flips to low. At the same time, the positive terminal voltage of the comparator switches to Vref2, and the capacitor C0 is discharged by the current Idc. When the negative terminal voltage of the comparator is lower than Vref2, the comparator output is low. In this way, the cycle repeats to achieve a CLK frequency output.

[0005] The defects of the prior art are as follows:

[0006] Problems with ring oscillation in method 1:

[0007] 1. The frequency changes significantly with VDD;

[0008] 2. The output frequency duty cycle is greatly affected by temperature and process, and it is impossible to effectively output a controlled duty cycle frequency;

[0009] Disadvantages of method 2:

[0010] 1. Method 2 introduces a comparator to solve the problem of frequency changing with power supply voltage, but the speed of the comparator limits the maximum output frequency. If the CLK frequency needs to be higher, the comparator speed also needs to be higher, and at the same time, it introduces relatively large power consumption;

[0011] 2. Method 2 introduces a comparator, so there is a minimum operating voltage limit. The minimum operating voltage of the circuit must ensure the normal operation of the comparator;

[0012] 3. Method 2 introduces two voltage values, Vref1 and Vref2, so another circuit is required to provide the corresponding voltage. Summary of the invention

[0013] In view of the above technical problems, the present invention provides a zero-temperature duty cycle adjustable oscillation circuit and adjustment method, which can achieve the output frequency being independent of temperature and power supply voltage without increasing the chip area. At the same time, a back-lock mechanism is introduced to eliminate the unstable state in the circuit that may cause the output frequency change problem.

[0014] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0015] Based on one aspect of the present invention, a zero-temperature duty cycle adjustable oscillator circuit is disclosed, the circuit comprising a first NAND gate, a first input end of the first NAND gate connected to an output end of the first NAND gate, an output end of the first NAND gate connected to a gate of a first NMOS tube, a drain of the first NMOS tube connected to a gate of a second NMOS tube, a drain of the second NMOS tube connected to an input end of a second NAND gate, an output end of the second NAND gate connected to an input end of a third NMOS tube, an output end of the third NMOS gate connected to a first input end of a second NAND gate, an output end of the second NAND gate connected to a gate of a third NMOS tube, and a drain of the third NMOS tube connected to an input end of a fourth NMOS tube. The gate of the OS tube, the drain of the fourth NMOS tube is connected to the input end of the fourth NOT gate, the output end of the fourth NOT gate is connected to the input end of the first NOT gate, the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are also respectively connected to a current source and a grounding capacitor, the first input ends of the first NAND gate and the second NAND gate are connected to the first input end and the second input end of a logic control chip, the first output end and the second output end of the logic control chip are respectively connected to the second input ends of the first NAND gate and the second NAND gate, and the logic control chip has a reset end.

[0016] Furthermore, the current source adopts a Cascode structure.

[0017] Furthermore, the sources of the second NMOS tube and the fourth NMOS tube are connected to a compensation module.

[0018] Furthermore, the compensation module includes a fifth NMOS tube and a sixth NMOS tube forming a current mirror structure, the source of the second NMOS tube or the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the drain of the sixth NMOS tube is connected to another current source.

[0019] Furthermore, the compensation module is a grounded positive temperature resistor.

[0020] According to another aspect of the present invention, there is provided a method for regulating a zero-temperature duty cycle adjustable oscillator circuit, which is applied to the circuit as described above. The method controls the logic control chip so that the circuit maintains an output state unchanged to achieve backlocking. The first input terminal of the logic control chip is connected to the first input terminal of the first NAND gate, the second input terminal is connected to the first input terminal of the second NAND gate, the first output terminal is connected to the second input terminal of the first NAND gate, and the second output terminal is connected to the second input terminal of the second NAND gate.

[0021] The technical solution disclosed in this disclosure has the following beneficial effects:

[0022] By adopting a negative feedback mechanism, an output frequency with close to zero temperature variation can be achieved; it can work under low power supply voltage; by controlling the current charging the capacitor, the duty cycle can be adjusted at will; and a back lock is introduced to ensure the reliability of the circuit output frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a ring oscillator circuit in the background technology of this specification;

[0024] Figure 2 The schematic diagram of the oscillator circuit with comparator in the background technology of this specification;

[0025] Figure 3 Schematic diagram of a zero-temperature duty cycle adjustable oscillator circuit in an embodiment of this specification;

[0026] Figure 4 A schematic diagram of various ports of a logic control chip in an embodiment of this specification;

[0027] Figure 5 is a truth table of the lockback mechanism in the embodiment of this specification;

[0028] Figure 6 It is a state diagram of the oscillation circuit in the embodiment of this specification;

[0029] Figure 7 A schematic diagram of the output frequency of the oscillator circuit in the embodiment of this specification;

[0030] Figure 8 This is a schematic diagram of a negative feedback compensation mechanism implemented by a positive temperature resistor in an embodiment of this specification;

[0031] Fig. 9 This is a schematic diagram of a negative feedback compensation mechanism implemented by a MOS tube in an embodiment of this specification. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0033] like Figure 3 As shown, an embodiment of the present specification provides a zero-temperature duty cycle adjustable oscillator circuit, the circuit includes a first NAND gate Y1, a first input end of the first NAND gate Y1 is connected to the output end of the first NAND gate F1, and its output end is connected to the gate of the first NMOS tube MN1, the drain of the first NMOS tube MN1 is connected to the gate of the second NMOS tube MN2, the drain of the second NMOS tube MN2 is connected to the input end of the second NAND gate F2, the output end of the second NAND gate F2 is connected to the input end of the third NMOS gate F3, the output end of the third NMOS gate F3 is connected to the first input end of the second NAND gate Y2, the output end of the second NAND gate Y2 is connected to the gate of the third NMOS tube MN3, the drain of the third NMOS tube MN3 is connected to the gate of the fourth NMOS tube MN4, and the fourth The drain of the NMOS tube MN4 is connected to the input end of the fourth NOT gate F4, the output end of the fourth NOT gate F4 is connected to the input end of the first NOT gate F1, the drains of the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, and the fourth NMOS tube MN4 are also respectively connected to a current source (I0, I1, I2) and a grounding capacitor (C1, C2), the first input ends of the first NAND gate Y1 and the second NAND gate Y2 are connected to the first input end Seta and the second input end Setb of a logic control chip, the first output end OUT and the second output end OUTB of the logic control chip are respectively connected to the second input ends of the first NAND gate Y1 and the second NAND gate Y2, and the logic control chip has a reset end Reset.

[0034] The various ports of the logic control chip are as follows Figure 4 As shown, the circuit maintains an output state unchanged by controlling the logic control chip to achieve back locking, wherein the first input terminal of the logic control chip is connected to the first input terminal of the first NAND gate, the second input terminal of the logic control chip is connected to the first input terminal of the second NAND gate, the first output terminal of the logic control chip is connected to the second input terminal of the first NAND gate, and the second output terminal of the logic control chip is connected to the second input terminal of the second NAND gate.

[0035] The present invention is mainly used for generating frequency signals inside the chip. On the basis of not increasing the chip area, the output frequency can be kept constant with temperature and power supply voltage. At the same time, a back-lock mechanism is introduced to eliminate the problem of unstable state in the circuit, which may cause the output frequency to change. The overall architecture is as follows Figure 3 As shown, since the structure does not use a comparator circuit, the current source input can use a Cascode structure. Since the current source has a low VDD voltage requirement, the oscillation circuit can operate at a lower VDD power supply voltage.

[0036] The truth table of the lockback mechanism is as follows Figure 5 As shown, 0 represents a low-level input / output signal, 1 represents a high-level input / output signal, and Seta / Setb is Figure 3 The output signal of the oscillation circuit, that is, the signal of the first input terminal of the first NAND gate and the second NAND gate, is used to generate the signal OUT / OUTB; Reset is the initial reset signal of the reset terminal, OUT is the output signal of the oscillation circuit, that is, the signal of the second input terminal of the first NAND gate, which is used for other module circuits inside the chip. At the same time, OUT / OUTB is fed back to the internal module of the circuit to complete the back-locking function.

[0037] The working process of the circuit is as follows Figure 6 As shown, there are 5 states in total, and the 5 working states form a cycle to generate an OUT frequency signal. Specifically, the states are as follows:

[0038] State 1: When the chip is not working, the Reset signal is 0, OUT = 0, OUTB = 1, and the frequency waveform OUT output to the outside is always low. When the Reset signal is 1, Seta = 1, Setb = 0, Figure 5 As shown in the truth table, OUT=1, OUTB=0.

[0039] State 2: OUTB = 0, which will cause the gate of MN3 to be high, pulling down the voltage at point B of the circuit, resulting in Setb = 1, and Seta = 1. Figure 5 As shown in the truth table, the output OUT=1, OUTB=0 is maintained, and the capacitor C1 is charged by the current source I1 (charging time t1). When the voltage at point A reaches Vx, the voltage at point C of the circuit will be pulled down to near 0.

[0040] State 3: When the voltage at point C of the circuit is low, Seta is low level 0, and Setb is high level 1. Figure 5 As shown in the truth table, OUT=0, OUTB=1.

[0041] State 4: When OUTB=0, the voltage at point A of the circuit is pulled down to 0 by the MN1MOS tube, Seta=1, Setb=1, so the output remains OUT=0, OUT=1, and the capacitor C2 is charged by the current source I2 (charging time t2). When the voltage at point B reaches Vx, the voltage at point D will be pulled down to close to 0.

[0042] State 5: When the voltage at point D is low level 0, Setb is low level 0, at this time Setb is low level 0, Seta is high level 1, and the next state will return to state 1.

[0043] The triggering of the lockback mechanism will be beneficial to the duty cycle adjustment and the elimination of the unstable state, such as Figure 7 As shown, the initial states of the high level (t1) and the low level (t2) of the CLK clock are consistent each time, and the capacitor C is charged by the current I1 or I0. Therefore, for the error of the temporary idle ratio, it is only necessary to correct the current I1 or I0.

[0044] Depend on Figure 7 From the working principle of the circuit, we know that the frequency output formed by state 1 to state 5 is as follows Figure 7 As shown, when the capacitance C of points A and B of the circuit and the flip voltage Vx are consistent, the relationship between the frequency f of the output frequency OUT and the Vx voltage, currents I1 and I0 is shown in the following formula. If the frequency f needs to be kept constant, the time t1 and t2 can be controlled by controlling the current I1 / I2 ratio to achieve the control of the output frequency and its duty cycle.

[0045] C*Vx=I1*t1;

[0046] C*Vx=I2*t2;

[0047]

[0048] In the above formula, currents I1 and I2 are temperature-invariant currents, and the capacitance C value also does not change with temperature. If Vx does not change with temperature, then the frequency f does not change with temperature. Since the characteristics of MOS tubes MN2 and MN4 change with temperature, when the temperature rises, the threshold voltage and electron mobility of the MOS tube will decrease. As can be seen from the following formula, the threshold voltage Vth and the electron mobility μ n It is a negative temperature characteristic.

[0049]

[0050]

[0051] MOS tube threshold voltage Vth and electron mobility μ nThe impact on the Vx node is an opposite relationship. The reduction of the threshold voltage will cause the Vx node voltage to drop, and the reduction of the electron mobility will cause the Vx voltage to rise. However, the impact of Vth is greater than the impact of the electron mobility, so it will cause the voltage of the Vx point to decrease, which in turn affects the frequency to become faster. This embodiment introduces a negative feedback compensation mechanism to reduce the change of Vx with temperature, so that the frequency basically does not change with temperature. There are many forms of negative feedback mechanisms, two of which are as follows: Figure 8 and Fig. 9 shown.

[0052] The source electrodes of the second NMOS tube and the fourth NMOS tube are connected to a compensation module, which is a grounded positive temperature resistor. Figure 8 As shown, it is a negative feedback compensation mechanism realized by resistors. Its principle is shown in the following formula. The current I0 is a zero-temperature current. By introducing a positive temperature resistor whose resistance changes with temperature, when the temperature rises, the resistance of the resistor R1 continues to increase, which will cause the voltage on the resistor R1 to increase, maintaining the voltage of Vx unchanged.

[0053]

[0054] In one embodiment, the compensation module includes a fifth NMOS tube and a sixth NMOS tube forming a current mirror structure, the source of the second NMOS tube or the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the drain of the sixth NMOS tube is connected to another current source. Fig. 9 As shown in the figure, it is a negative feedback compensation mechanism based on MOS tube. A positive temperature resistor is formed by MOS to compensate for the reduction of Vx voltage caused by the reduction of threshold voltage. The I3 current is a zero-temperature current. The Vgs6 voltage of MN6 tube meets the following formula:

[0055]

[0056]

[0057] When the Vx voltage just rises, the MOM tube MN5 is in the linear region, and its Ron conforms to the formula of the linear region. Assuming that the size of MN6 is K times that of MN5, the calculation formula of MN6 is as follows:

[0058]

[0059] When the Vx voltage gradually rises, the voltage at point C will gradually decrease. When the flip threshold of the next level is reached, it will immediately enter the next state. At this time, MN2 is in the saturation region. The current balance equation can be used to obtain the following formula:

[0060]

[0061] In the above formula, μn Substituting into Vx, we can get the relationship between Vx voltage and Ron, and get the following formula:

[0062]

[0063] Assuming I3=k1*I0, the size of MN6 tube is K2 times the size of MN2 tube, and combining the previous formula, we can get the following formula. From the following formula, we can see that when the temperature rises and Vth decreases, the electron mobility Un also decreases, but the algebraic term related to the electron mobility becomes larger. Compensation is performed through MOS tubes, the value of K / (2*K1*K2) is adjusted, and the coefficient ratio positively correlated with temperature in the following formula is increased to compensate for the decrease in Vx caused by the negative temperature characteristics of Vth.

[0064]

[0065] When the Vx voltage does not change with temperature, a frequency that does not change with temperature can be output.

[0066] The technical solution disclosed in this disclosure has the following beneficial effects:

[0067] By adopting a negative feedback mechanism, an output frequency with close to zero temperature variation can be achieved; it can work under low power supply voltage; by controlling the current charging the capacitor, the duty cycle can be adjusted at will; and a back lock is introduced to ensure the reliability of the circuit output frequency.

[0068] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A zero-temperature duty cycle adjustable oscillator circuit, characterized in that: The circuit includes a first NAND gate, wherein the first input end of the first NAND gate is connected to the output end of the first NAND gate, and the output end of the first NAND gate is connected to the gate of the first NMOS tube, the drain of the first NMOS tube is connected to the gate of the second NMOS tube, the drain of the second NMOS tube is connected to the input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the third NAND gate, the output end of the third NAND gate is connected to the first input end of the second NAND gate, the output end of the second NAND gate is connected to the gate of the third NMOS tube, the drain of the third NMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the input end of the fourth NAND gate, the output end of the fourth NAND gate is connected to the input end of the first NAND gate, the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are also respectively connected to a current source and a grounding capacitor, the first input ends of the first NAND gate and the second NAND gate are connected to the first input end and the second input end of a logic control chip, the first output end and the second output end of the logic control chip are respectively connected to the second input ends of the first NAND gate and the second NAND gate, and the logic control chip has a reset end.

2. The zero-temperature duty cycle adjustable oscillator circuit according to claim 1, characterized in that: The current source adopts a Cascode structure.

3. The zero-temperature duty cycle adjustable oscillator circuit according to claim 2, characterized in that: The sources of the second NMOS tube and the fourth NMOS tube are connected to a compensation module.

4. The zero-temperature duty cycle adjustable oscillator circuit according to claim 3, characterized in that: The compensation module includes a fifth NMOS tube and a sixth NMOS tube forming a current mirror structure, the source of the second NMOS tube or the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the drain of the sixth NMOS tube is connected to another current source.

5. The zero-temperature duty cycle adjustable oscillator circuit according to claim 3, characterized in that: The compensation module is a grounded positive temperature resistor.

6. A method for adjusting a zero-temperature duty cycle adjustable oscillator circuit, characterized in that: Applied to the circuits as described in claims 1-5, the method controls the logic control chip so that the circuit maintains an output state unchanged to achieve back locking, wherein the first input terminal of the logic control chip is connected to the first input terminal of the first NAND gate, the second input terminal of the logic control chip is connected to the first input terminal of the second NAND gate, the first output terminal of the logic control chip is connected to the second input terminal of the first NAND gate, and the second output terminal of the logic control chip is connected to the second input terminal of the second NAND gate.

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