Annealing-free ferroelectric film material and device application thereof

Abstract

The invention discloses an annealing-free ferroelectric film material and a device application thereof. The invention provides a lanthanum-doped hafnium zirconium oxide (La: HZO) ferroelectric material using atomic layer deposition. The crystallization temperature and ferroelectric characteristics of the material are regulated and controlled by adjusting the deposition temperature and the oxygen source pulse time; the lanthanum doping proportion is regulated and controlled to control the ferroelectric characteristic and the electric leakage characteristic of the gate dielectric, the ferroelectric material which does not need annealing and is high in remanent polarization intensity and durability is achieved, the requirement for the process temperature needed by the subsequent process is met, and the ferroelectric material can be perfectly compatible with the subsequent process of a modern integrated circuit. Based on the material, a high-performance FeFET and a storage circuit thereof can be realized, and a high-performance FeRAM and a storage circuit thereof can also be realized. Compared with other HfO2 materials needing to be annealed to realize ferroelectricity, the material has lower crystallization temperature, higher remanent polarization under the same thermal budget and smaller electric leakage.

Description

Technical Field

[0001] The invention relates to the fields of semiconductor technology and ferroelectric storage technology, and in particular to a hafnium oxide-based ferroelectric thin film material that does not require annealing and device applications thereof. Background Art

[0002] With the rapid development of computing technology, the development of storage technology has lagged far behind the development of computing technology. Against this background, ferroelectric memory has become a common research and development object of scientific research and industry because of its advantages such as non-volatility, fast writing and erasing speed, and good stability.

[0003] Among many ferroelectric materials, hafnium oxide-based ferroelectric materials can be grown through atomic layer deposition and are perfectly compatible with traditional integrated circuit processes. They also have the advantages of high density, low power consumption, long-term data retention, fast reading and writing, and three-dimensional integration. They are regarded as promising candidate materials in future storage technologies and are expected to play an important role in the future storage field.

[0004] The ferroelectricity of hafnium-based ferroelectric materials comes from the ferroelectric orthorhombic phase (o-phase), but the formation of the o-phase requires a large tensile stress, which is generally obtained by high-temperature annealing after top electrode coverage. This is inconsistent with the low-temperature process below 450°C required by the back-end compatible process, which to some extent restricts the application of hafnium-based ferroelectric materials in integrated circuits. Summary of the invention

[0005] In view of the problem of high temperature annealing required for the current hafnium oxide-based ferroelectric materials, the purpose of the present invention is to provide a method based on achieving low temperature ferroelectric thin film without annealing, thereby providing an excellent method for preparing high-performance ferroelectric memory devices and circuits thereof. Through the hafnium oxide-based ferroelectric material and device preparation method without annealing provided by the present invention, a ferroelectric thin film and device compatible with the back-end process, with a large residual polarization intensity, a large storage window and high durability can be obtained.

[0006] In the first aspect of the present invention, a method for lowering the crystallization temperature by doping HZO (hafnium zirconium oxide) with lanthanum is provided. Lanthanum doping can effectively expand the unit cell volume of the thin film. A larger unit cell volume can effectively reduce the formation energy of the ferroelectric o-phase, and ultimately a ferroelectric film with larger grains and more o-phase ratio is obtained, thereby obtaining better ferroelectric properties, thereby expanding the application scenarios.

[0007] The present invention provides a method for preparing a ferroelectric film without annealing, wherein a La-doped hafnium oxide film or HZO film is prepared by an atomic layer deposition (ALD) method, wherein the atomic layer deposition temperature is controlled within a range of 100° C. to 400° C., the oxygen source pulse time is 0.01 to 100 seconds, and a La atomic layer deposition is inserted once every n Hf atomic layer depositions or n Hf and Zr atomic layer deposition cycles, wherein n is an integer of 1 to 60, and the content of the La element is 0.01 to 30 mol%, i.e., a La:(Hf+Zr+La+O) molar ratio. Preferably, n is an integer of 8 to 20.

[0008] In lanthanum-doped HZO (referred to as La:HZO), the La element can be doped in different positions and orders. For example, one La atomic layer can be deposited after four Hf and Zr atomic layer cycles, or 10 La atomic layer can be deposited after 40 Hf and Zr atomic layer cycles. The Hf(Zr):La ratio is 4:1. However, due to the different thicknesses of a single material, two thin film states, solid solution or superlattice, may be formed, and the ferroelectric properties will be different. Generally speaking, the atoms in the solid solution state are more closely mixed, which helps to reduce the crystallization temperature of the material. In terms of sequence, two La atomic layer depositions can be performed before eight Hf and Zr atomic layer deposition cycles, or one La atomic layer deposition can be performed after four Hf and Zr atomic layer deposition cycles. The Hf(Zr):La ratio is 4:1. However, due to the different interfaces directly contacting the top and bottom electrodes, the crystallization phase of the ferroelectric material is closely related to the surface state. When the metal interface contacts ZrO2 and La2O3, the formation energy of the ferroelectric orthorhombic phase is lower than that of the metal interface contacting HfO2, which is more conducive to the preparation of ferroelectric materials with better performance.

[0009] In lanthanum-doped HZO, the addition of La can increase or decrease the content of Hf and Zr itself, and even exclude Zr. In terms of the amount of substance, Zr:Hf=(0~2):1. For Hf:Zr=1:1, the doping range of La is between 0.01 and 20 mol%. A trace amount of La can effectively reduce the formation energy of the ferroelectric orthorhombic phase (o phase), and the film exhibits excellent ferroelectric properties. When the La content is high, the formation energy of the tetragonal phase (t phase) is lower, and the film is more likely to exhibit antiferroelectric properties. If the La content is further increased, the film will be difficult to crystallize and will exhibit paraelectric properties as a whole. The effect of reducing the Hf content is opposite to that of increasing the La content. If the proportion of Zr is reduced, the La doping range can be higher than 20 mol%.

[0010] In the second aspect of the present invention, a method for reducing the crystallization temperature of a ferroelectric film by optimizing the deposition temperature and oxygen source pulse time of atomic layer deposition (ALD) is provided, thereby realizing the preparation of ferroelectric materials without annealing. The deposition temperature and oxygen source pulse time not only have a significant impact on the oxidation bonding of Hf, Zr, and La elements themselves, but also have a significant impact on the content of residual elements such as C, H, O, and N in the film, and these residual elements have a huge impact on the crystallization phase of the ferroelectric film, which will eventually be reflected in the crystallization temperature and ferroelectric properties of the ferroelectric film, making the ferroelectric film more suitable for application in modern integrated circuits. Specifically, the deposition temperature ranges from 100°C to 400°C. Within a suitable range, the higher the deposition temperature, the higher the reaction activity of the precursor and the oxygen source, and the corresponding precursor residual elements C, H, and N will be less, which is more conducive to the formation of the ferroelectric phase, that is, the higher the deposition temperature, the better the ferroelectric performance; but when the deposition temperature exceeds the thermal decomposition temperature of the precursor, the precursor will decompose into by-products, and this disadvantage will replace the advantage of the reaction activity, bringing more residual elements C, H, N, etc., which is not conducive to the formation of the ferroelectric phase and will cause more leakage current, that is, in this range, the higher the deposition temperature, the worse the ferroelectric performance. The preferred condition of the deposition temperature is 250-300°C. The range of oxygen source pulse time is 0.01 to 100 s. In the appropriate range, the higher the oxygen source pulse time, the more complete the oxidation of the precursor, the fewer oxygen vacancies, and the corresponding residual elements C, H, and N will be less, which is more conducive to the formation of the ferroelectric phase, that is, the longer the oxygen source pulse time, the better the ferroelectric performance. However, when the oxygen source pulse time exceeds the appropriate range, the adsorption steady state of the precursor will be broken, the impurity elements in the film will increase, and the ferroelectric performance will deteriorate. The preferred condition of oxygen source pulse time is 0.2 to 10 s.

[0011] In one possible implementation, the deposition temperature varies with deposition time, film thickness, and position. For example, a lower or higher deposition temperature may be used for the substrate surface to improve interface properties and optimize the crystal orientation of the subsequently grown film.

[0012] In a possible implementation, the oxygen source pulse time varies with deposition time, film thickness, and position. For example, a shorter or longer oxygen source pulse time may be used for the substrate surface to improve interface characteristics while suppressing the appearance of an interface dead layer.

[0013] In a possible implementation, different deposition temperatures and oxygen source pulse times are used for different precursors, such as hafnium and zirconium precursors, respectively, so as to achieve lower residual unfavorable elements. For example, for the precursor tetra(ethylmethylamino)hafnium with stronger reaction activity, the corresponding deposition temperature can be lower and the oxygen source pulse time can be reduced, while for the precursor hafnium tetrachloride with weaker reaction activity, the corresponding deposition temperature can be higher and the oxygen source pulse time can be increased, which can also achieve the purpose of reducing the residual elements in the film and enhancing the ferroelectricity.

[0014] In a possible implementation, the deposition temperature and the oxygen source pulse time may be optimized simultaneously.

[0015] In a third aspect of the present invention, various ferroelectric memory devices are prepared based on the above ferroelectric material that does not require annealing.

[0016] In one possible implementation, the ferroelectric material can be used as a gate dielectric to prepare ferroelectric field effect transistors (FeFETs) based on silicon (Si), germanium (Ge), gallium nitride (GaN), silicon carbide (SiC), two-dimensional materials (2D materials), and oxide semiconductor (OS) channels, including but not limited to transistors with back gate structure, top gate structure, double gate structure, fin structure, and surround gate structure.

[0017] In a possible implementation, the ferroelectric material can be used to prepare a metal-ferroelectric material-metal (MFM) ferroelectric capacitor for use in a ferroelectric random access memory (FeRAM) and a dynamic random access memory (DRAM), and the device structure can be a planar structure or a three-dimensional stacked structure. The structure of the ferroelectric random access memory can be a 1T-1C or nT-nC structure, wherein the transistor (T) can select various channel materials, and the dielectric of the capacitor (C) is derived from the ferroelectric material of the present invention.

[0018] In summary, the present invention proposes to use atomic layer deposited hafnium zirconium oxide (HZO) and lanthanum-doped hafnium zirconium oxide (La:HZO) ferroelectric materials, and to control the crystallization temperature and ferroelectric properties of the material by adjusting the deposition temperature and oxygen source pulse time; and to control the ferroelectric properties and leakage properties of the gate dielectric by adjusting the lanthanum doping ratio, thereby realizing a ferroelectric material that does not require annealing, has high residual polarization strength, and is highly durable, and meets the process temperature required for the back-end process, and is perfectly compatible with the back-end process of modern integrated circuits. Based on this material, high-performance ferroelectric field effect transistors (FeFETs) and their storage circuits can be realized, and high-performance ferroelectric random access memories (FeRAMs) and their storage circuits can also be realized. Compared with other hafnium oxide-based materials that require annealing to achieve ferroelectricity, the present invention has the following main advantages:

[0019] 1) By doping with lanthanum, the ferroelectric phase fraction and unit cell volume can be increased simultaneously, which can take into account both high ferroelectricity and durability;

[0020] 2) By optimizing the deposition temperature and oxygen source pulse time to change the element content of the gate dielectric itself, the nature of the material is optimized and has a lower crystallization temperature, thereby achieving a ferroelectric film with higher ferroelectric performance under the same thermal budget;

[0021] 3) Ferroelectric materials do not require annealing and do not require top electrode coverage to provide compressive stress, making them perfectly compatible with downstream processes;

[0022] 4) No need to consider the electrode interface, which can achieve a wider range of applications such as dual-gate, all-around-gate ferroelectric field-effect transistors and their storage circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of a metal-ferroelectric-metal (MIM) capacitor.

[0024] Figure 2 Flow chart for the preparation of metal-ferroelectric-metal (MIM) capacitors.

[0025] Figure 3 Detailed growth flow chart for ALD deposited lanthanum-doped thin films.

[0026] Figure 4 This is a schematic diagram of the structure of a hafnium zirconium oxide top-gate ferroelectric transistor (FeFET) based on oxide semiconductor and lanthanum doping without the need for annealing.

[0027] Figure 5 The present invention is a preparation flow chart of a hafnium zirconium oxide top-gate ferroelectric transistor (FeFET) based on oxide semiconductor and lanthanum doping without annealing.

[0028] Figure 6 This is a schematic diagram of the structure of a three-dimensional stacked ferroelectric random access memory based on oxide semiconductors and lanthanum-doped hafnium zirconium oxide dielectrics that do not require annealing.

[0029] Figure 7 The figure is a process flow chart for preparing a three-dimensional stacked ferroelectric random access memory based on oxide semiconductors and lanthanum-doped hafnium zirconium oxide dielectrics that do not require annealing.

[0030] In the figure, 1 is the substrate, 2 is the bottom electrode of the capacitor, 3 is the ferroelectric dielectric layer, 31 is the HfO2 layer, 32 is the ZrO2 layer, 33 is the La2O3 layer, 4 is the top electrode of the capacitor, 5 is the channel layer, 6 and 7 are the Ni layer and Au layer of the source and drain electrodes respectively, 8 and 9 are the Pt layer and Au layer of the top gate electrode respectively, 10 is the back gate electrode, 11 is the gate dielectric layer, 12 is the isolation layer, 13 is the interconnect electrode Au layer, and 14 is the photoresist mask layer. DETAILED DESCRIPTION

[0031] The present invention provides a method for preparing a hafnium-based ferroelectric material without annealing, and is applied to ferroelectric capacitors, ferroelectric transistors (FeFETs), ferroelectric memories (FeRAMs), random access memories (DRAMs), etc. The following three embodiments of the present invention are described in detail in conjunction with the accompanying drawings, but those skilled in the art should understand that the following embodiments are only used to illustrate the present invention and should not be considered to limit the scope of the present invention.

[0032] Embodiment 1

[0033] The structure of the lanthanum-doped hafnium zirconium oxide ferroelectric capacitor without annealing is as follows Figure 1 As shown, it includes a substrate 1 and a capacitor bottom electrode 2, a ferroelectric dielectric layer 3 and a capacitor top electrode 4 which are sequentially stacked on the substrate 1. Figure 2 As shown, the specific preparation steps are as follows:

[0034] Step 1, bottom electrode preparation: Use standard process to clean the high-resistance silicon substrate 1, such as Figure 2 As shown in (a), the magnetron sputtering method is then used, with tungsten (W) metal as the target material, argon (Ar) as the sputtering gas, and a vacuum degree of <10 -5 Pa, deposit a 10-100 nm thick W capacitor bottom electrode 2, such as Figure 2 As shown in (b).

[0035] Step 2, preparation of ferroelectric material: Deposit a hafnium zirconium oxide (HZO) or lanthanum-doped hafnium zirconium oxide (La:HZO) ferroelectric dielectric layer 3 by atomic layer deposition method, such as Figure 2 As shown in (c), the thickness is 1 to 100 nm. The hafnium source is tetra(ethylmethylamino)hafnium, the zirconium source is tetra(ethylmethylamino)zirconium, the lanthanum source is tri(N,N'-diisopropylformamidine)lanthanum, the oxygen source is O3, the oxygen source pulse time is 0.1 to 100 s, and the deposition temperature is 100 to 400 °C. The detailed deposition process of the La:HZO ferroelectric dielectric layer is shown in Figure 2. Figure 3 As shown, one cycle of HfO2 layer 31 is grown by atomic layer deposition, followed by one cycle of ZrO2 layer 32. n HfO2 and ZrO2 films together constitute the HZO film. On this basis, a La2O3 layer 33 is inserted after every n HfO2 layers 31 and ZrO2 layers 32 to dope the lanthanum element. After several such cycles, a La:HZO film is formed.

[0036] Step 3, top electrode preparation: The top electrode area is exposed by UV lithography and developed to obtain a defined top electrode area. Then, a magnetron sputtering method is used, with tungsten (W) metal as the target material, argon (Ar) as the sputtering gas, and a vacuum degree of <10 -5Pa, deposit 10-100nm thick W, and finally form the W capacitor top electrode 4 through metal lift-off process, such as Figure 2 As shown in (d).

[0037] Different from the preparation process of conventional ferroelectric capacitors, the above process does not involve any annealing process.

[0038] Embodiment 2

[0039] Based on oxide semiconductor and lanthanum doping, no annealing is required for the top-gate ferroelectric transistor (FeFET) structure of hafnium zirconium oxide. Figure 4 As shown, it includes a substrate 1 and an oxide semiconductor channel layer 5 located on the substrate 1, with source and drain electrodes at both ends of the channel layer 5, and a ferroelectric dielectric layer 3 and a top gate electrode between the source and drain. Figure 5 As shown, the specific preparation steps are as follows:

[0040] Step 1: Substrate cleaning. Select a high-resistance silicon substrate 1 with good electrical insulation and a resistivity of >10 4 Ω·cm. Use standard RCA to clean the substrate 1. First, soak it in RCA-1 (deionized water: ammonia: hydrogen peroxide = 5:1:1) at 70°C for 10 minutes to clean the metal cations, organic matter and other contaminants on the substrate. After cleaning, blow it dry with high-purity nitrogen. Figure 5 As shown in (a).

[0041] Step 2: Prepare an indium gallium zinc oxide (IGZO) thin film layer by magnetron sputtering, using IGZO with a ratio of In:Ga:Zn=1:1:1 as the target material, argon (Ar) and oxygen (O2) as the sputtering gas, and a vacuum degree of <10 -6 Pa, depositing IGZO films with a thickness of 1 to 20 nm.

[0042] Step 3, defining a channel layer 5 on the deposited IGZO film, such as Figure 5 As shown in (b), the process specifically includes the following steps: spin coating photoresist, baking, exposure, development, oxygen plasma cleaning to remove residual photoresist, wet etching, etc.

[0043] Step 4, prepare the Ni layer 6 and Au layer 7 of the source and drain electrodes, such as Figure 5 As shown in (c), the process specifically includes the following steps: coating, baking, exposure, development, physical vapor deposition, and lift-off.

[0044] Step 5, depositing a 10 nm thick lanthanum-doped hafnium zirconium oxide iron dielectric layer 3 as a top gate dielectric layer on the sample obtained in step 4 by atomic layer deposition, as shown in FIG. Figure 5 The specific growth process is shown in the previous Figure 3 Already described.

[0045] Step 6, prepare the Pt layer 8 and Au layer 9 of the top gate electrode, such as Figure 5 As shown in (e), the process steps include coating, baking, exposure, development, physical vapor deposition, and stripping.

[0046] Embodiment 3

[0047] Based on oxide semiconductor and lanthanum doping, a three-dimensional stacked ferroelectric random access memory is prepared without annealing the hafnium zirconium oxide dielectric. The structure is as follows Figure 6 As shown, the preparation steps are as follows Figure 7 As shown, including:

[0048] Step 1: Substrate cleaning. Select a high-resistance silicon substrate 1 with good electrical insulation and a resistivity of >10 4 Ω·cm. Use standard RCA to clean the substrate. First, soak it in RCA-1 (deionized water: ammonia: hydrogen peroxide = 5:1:1) at 70°C for 10 minutes to clean the metal cations, organic matter and other contaminants on the substrate. After cleaning, blow it dry with high-purity nitrogen. Figure 7 As shown in (a).

[0049] Step 2, preparing the back gate electrode 10, such as Figure 7 As shown in (b), the process specifically includes coating, baking, exposure, development, physical vapor deposition, and lift-off.

[0050] Step 3, using atomic layer deposition to deposit a 3-20 nm thick hafnium lanthanum oxide dielectric material as a gate dielectric layer 11 on the sample obtained in step 2, such as Figure 7 As shown in (c).

[0051] Step 4: an indium gallium zinc oxide (IGZO) thin film layer is prepared by magnetron sputtering, with IGZO with In:Ga:Zn=1:1:1 as the target material, argon (Ar) and oxygen (O2) as the sputtering gas, and a vacuum degree of <10 -6 Pa, depositing IGZO films with a thickness of 1 to 20 nm.

[0052] Step 5, defining a channel layer 5 on the deposited IGZO film, such as Figure 7 As shown in (d), the process specifically includes the following steps: spin coating photoresist, baking, exposure, development, oxygen plasma cleaning to remove residual photoresist, wet etching, etc.

[0053] Step 6, preparing the Ni layer 6 and Au layer 7 of the source and drain electrodes, such as Figure 7 As shown in (e), the process specifically includes the following steps: coating, baking, exposure, development, physical vapor deposition, and lift-off.

[0054] Step 7, depositing a 50 nm thick silicon oxide layer as an isolation layer 12 on the sample obtained in step 6 by plasma chemical vapor deposition, the deposition temperature is 100-300°C, such as Figure 7 As shown in (f).

[0055] Step 8, spin-coating a photoresist mask layer 14 on the sample obtained in step 7, and then defining an interconnection through-hole layer by a plasma etching machine, such as Figure 7 As shown in (g), the process specifically includes the following steps: coating, baking, exposure, development, etching, etc.

[0056] Step 9, prepare the interconnect electrode Au layer 13 by physical vapor deposition, such as Figure 7 As shown in (h).

[0057] Step 10, obtaining the interconnect electrode Au layer 13 by a stripping process, such as Figure 7 The specific process is to heat at 50°C in acetone for more than 30 minutes, rinse with IPA and then blow dry with high-purity nitrogen.

[0058] Step 11, chemical mechanical polishing (CMP polishing), such as Figure 7 As shown in (j). Removing the metal outside the groove makes the surface flat

[0059] Step 12, preparation of capacitor bottom electrode 2, such as Figure 7 As shown in (k), the specific steps include spin coating photoresist, baking, exposure, development, magnetron sputtering, stripping and other process steps:

[0060] Step 13, preparation of ferroelectric material: Deposit a hafnium zirconium oxide (HZO) or lanthanum-doped hafnium zirconium oxide (La:HZO) ferroelectric dielectric layer 3 by atomic layer deposition method, such as Figure 7 As shown in (l), the thickness is 1 to 100 nm. The hafnium source is tetra(ethylmethylamino)hafnium, the zirconium source is tetra(ethylmethylamino)zirconium, the lanthanum source is tri(N,N'-diisopropylformamidine)lanthanum, the oxygen source is O3, the oxygen source pulse time is 0.1 to 100 s, the deposition temperature is 200 to 400 °C, and the detailed deposition process is as follows Figure 3 shown.

[0061] Step 14, preparation of the capacitor top electrode 4, such as Figure 7 As shown in (m), the specific steps include spin coating of photoresist, baking, exposure, development, magnetron sputtering, stripping and other process steps.

[0062] The above three embodiments are merely presented as a way of describing the implementation of the present invention. However, those skilled in the art should understand that the above embodiments are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention.

Claims

1. A method for preparing a ferroelectric film without annealing, wherein a La-doped hafnium oxide film or HZO film is prepared by an atomic layer deposition method, the deposition temperature is controlled within the range of 100°C to 400°C, the oxygen source pulse time is 0.01 to 100s, and a La atomic layer deposition is inserted once for every n Hf atomic layer depositions or n Hf and Zr atomic layer deposition cycles, wherein: n is an integer of 1 to 60, and the content of La element is 0.01 mol% to 30 mol%.

2. The method for preparing a ferroelectric thin film according to claim 1, characterized in that: n is an integer from 8 to 20.

3. The method for preparing a ferroelectric thin film according to claim 1, characterized in that: The molar ratio of Zr:Hf elements in the HZO film is (0-2):

1.

4. The method for preparing a ferroelectric thin film according to claim 1, characterized in that: When the molar ratio of Hf:Zr in the film is 1:1, one Hf atomic layer deposition and one Zr atomic layer deposition constitute one Hf, Zr atomic layer deposition cycle, and one La atomic layer deposition is inserted into every n Hf, Zr atomic layer deposition cycles, and the doping ratio of La element is 0.01 to 20 mol%.

5. The method for preparing a ferroelectric thin film according to claim 1, characterized in that: The ferroelectric properties of the films can be tuned by adjusting the deposition temperature and / or the oxygen source pulse time.

6. The method for preparing a ferroelectric thin film according to claim 5, characterized in that: For different precursors, different deposition temperatures, oxygen sources and oxygen source pulse times were used.

7. The method for preparing a ferroelectric thin film according to claim 1, characterized in that: In atomic layer deposition, the hafnium source is tetrakis(ethylmethylamino)hafnium or hafnium tetrachloride, the zirconium source is tetrakis(ethylmethylamino)zirconium, the lanthanum source is tris(N,N'-diisopropylformamidinium)lanthanum, and the oxygen source is O3.

8. The ferroelectric thin film material obtained according to the method for preparing a ferroelectric thin film without annealing according to any one of claims 1 to 7.

9. A ferroelectric memory device, comprising a ferroelectric field effect transistor and / or a ferroelectric capacitor, characterized in that: The gate dielectric in the ferroelectric field effect transistor is the ferroelectric thin film material according to claim 8, and the dielectric in the ferroelectric capacitor is the ferroelectric thin film material according to claim 8.

10. The ferroelectric memory device according to claim 9, characterized in that The ferroelectric field effect transistor is a ferroelectric field effect transistor based on silicon, germanium, gallium nitride, silicon carbide, two-dimensional material or oxide semiconductor channel, and its structure is a back gate structure, a top gate structure, a double gate structure, a fin structure or a surrounding gate structure.

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