FPGA (Field Programmable Gate Array) synchronous triggering module with PTP (Precision Time Protocol) timestamp

Abstract

The invention relates to the technical field of optical motion capture, and discloses an FPGA (Field Programmable Gate Array) synchronous triggering module with a PTP (Precision Time Protocol) timestamp. The module comprises an axi lites interface, a clk interface, a resn interface, a trigger interface and a timestamp interface, the axi lites interface is used for configuring parameters of the FPGA synchronous trigger module and receiving start and stop trigger signals, the clk interface is used for receiving clock signals, the resn interface is used for receiving reset signals, the trigger interface is used for outputting synchronous trigger signals based on preset trigger conditions, and the timestamp interface is used for receiving reset signals based on preset trigger conditions. And the timestamp interface is used for outputting a ptp 64-bit timestamp latched when a synchronous trigger signal is changed from low to high so as to be used for synchronous framing of the collected data. According to the invention, high-precision time synchronization can be provided through ptp, and a trigger signal of any frequency and a corresponding timestamp are generated at the same time.

Description

Technical Field

[0001] The present application relates to the technical field of optical motion capture, and in particular to an FPGA synchronization trigger module with a PTP timestamp. Background Art

[0002] In modern optical motion capture systems, in order to achieve high-precision data collection and multi-device collaboration, it is usually necessary to synchronize multiple hardware devices to ensure that the data collected by each device is consistent in time and without delay. In the prior art, common synchronization methods include dedicated synchronization cables, infrared synchronization, wireless synchronization, and time synchronization based on the network time protocol.

[0003] Among them, dedicated synchronization cables have higher reliability, but they require special synchronization cables and synchronization master devices, which not only increases the hardware cost, but also makes the system layout more complicated. Infrared synchronization and wireless synchronization can operate effectively in certain low-interference environments, but in industrial scenarios, due to the presence of external interference signals, infrared signals are easily blocked, and wireless signals are susceptible to electromagnetic interference, and reliability is difficult to guarantee, which limits their application in scenarios with high reliability requirements. Although network time synchronization based on PTP (Precision Time Protocol) can achieve nanosecond timestamp synchronization and provide a time reference through pps (Pulse Per Second) signals, it cannot generate synchronization trigger signals of any frequency, nor can it latch the corresponding timestamp. This makes this technology unable to meet the needs in application scenarios that require higher time accuracy and flexible triggering capabilities.

[0004] To sum up, in the synchronization application of optical motion capture systems, the existing technologies still have problems such as high cost, insufficient anti-interference ability, limited time synchronization accuracy and trigger signal generation capabilities. There is an urgent need for a technical solution that can provide high-precision time synchronization and support flexible trigger signal generation to meet the needs of industrial-grade application scenarios. Summary of the invention

[0005] In order to provide high-precision time synchronization through PTP and generate trigger signals of any frequency and corresponding timestamps at the same time, the present application provides an FPGA synchronization trigger module with PTP timestamp.

[0006] The present application provides an FPGA synchronization trigger module with a PTP timestamp, which adopts the following technical solution: A FPGA synchronous trigger module with a PTP timestamp comprises an axi lites interface, a clk interface, a res_n interface, a trigger interface and a timestamp interface, wherein the axi lites interface is used to configure parameters of the FPGA synchronous trigger module and receive start and stop trigger signals, the clk interface is used to receive a clock signal, the res_n interface is used to receive a reset signal, the trigger interface is used to output a synchronous trigger signal based on a preset trigger condition, and the timestamp interface is used to output a PTP 64-bit timestamp latched when the synchronous trigger signal changes from low to high, so as to be used for synchronous framing of collected data; wherein the parameters of the FPGA synchronous trigger module include an operating mode of the FPGA synchronous trigger module, a clock frequency and an initial state of a trigger signal.

[0007] Optionally, the FPGA synchronization trigger module is used to perform the following steps: Obtaining a configuration signal based on an axi lites interface; wherein the configuration signal includes parameters for configuring an FPGA synchronization trigger module; Get the clock signal and synchronize the PTP timestamp based on the clock signal and configuration signal; The frequency of the output synchronization trigger signal is set based on the configuration signal; wherein the frequency of the synchronization trigger signal corresponds to the triggering timing of the synchronization acquisition device; Outputting a synchronous trigger signal based on a preset trigger condition, wherein the preset trigger condition includes the arrival of a timestamp, the input of an external event, or the timeout of an internal timer; When outputting the synchronization trigger signal, record the current PTP timestamp; The output sync latches the time stamp of the sync trigger signal.

[0008] Optionally, the synchronous trigger signal is used to trigger a synchronous acquisition device, and the triggering of the synchronous acquisition device includes triggering a sensor to take a photo, turning on and off an infrared light, and collecting gyroscope data.

[0009] Optionally, the FPGA synchronization trigger module includes an internal PTP time tuning unit for receiving a time synchronization signal from a PTP server and adjusting a real-time clock inside the FPGA.

[0010] Optionally, the PTP time tuning unit is used to perform time deviation detection and compensation to automatically adjust the time error caused by temperature change or crystal oscillator aging.

[0011] Optionally, the frequency and pulse width of the synchronous trigger signal output by the trigger interface can be programmably set via an axilites interface.

[0012] Optionally, the module includes a trigger signal buffer unit for storing timestamps of multiple trigger signals in a high-frequency trigger scenario for subsequent data framing and time series analysis.

[0013] In summary, the present application includes at least one of the following beneficial technical effects: The module not only solves the limitations of traditional synchronization methods, but also provides high-precision time synchronization and flexible trigger signal generation capabilities. Through modular design, it can be easily integrated into various systems to meet the needs of different applications. The module's high reliability, precise timestamp recording, and trigger signal synchronization latching functions provide strong technical support for data acquisition, video surveillance, and industrial automation. In addition, the module's programmability ensures its adaptability and scalability in future technological developments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of an FPGA synchronization trigger module with a PTP timestamp in a certain embodiment of the present application. DETAILED DESCRIPTION

[0015] Embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings.

[0016] In the description of this specification, the description with reference to the terms "certain embodiments", "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0017] Reference Figure 1 The embodiment of the present application discloses an FPGA synchronous trigger module with PTP timestamp, including an axilites interface, a clk interface, a res_n interface, a trigger interface and a timestamp interface. The axilites interface is used to configure the parameters of the FPGA synchronous trigger module and receive start and stop trigger signals. The clk interface is used to receive clock signals. The res_n interface is used to receive reset signals. The trigger interface is used to output synchronous trigger signals based on preset trigger conditions. The timestamp interface is used to output the PTP 64-bit timestamp latched when the synchronous trigger signal changes from low to high, so as to be used for synchronous framing of collected data.

[0018] AXI Lites is a simplified AXI (Advanced eXtensible Interface) protocol suitable for low-bandwidth, low-latency control tasks. In this module, the main inputs of the AXI Lites interface include address signals, data signals, control signals, and enable signals.

[0019] The address signal is used to select a specific register or configuration unit. Different addresses correspond to different functions in the module, such as operating mode setting, clock frequency configuration, etc.

[0020] The data signal contains the parameter value used to configure the module. The data type can be binary data of a fixed length (such as 32 bits or 64 bits).

[0021] The control signal includes a read / write control signal, which is used to determine whether the current operation is to read the configuration or to write the configuration.

[0022] The enable signal is used to activate the AXI Lites interface to ensure that the module performs corresponding operations when receiving a legal command.

[0023] In different embodiments, the connection between the AXI Lites interface and other modules is different. The AXI Lites interface is usually connected to the internal control logic unit of the module to configure and control the module. For example, the connection with the internal logic of the FPGA: •The address signal is connected to the module's address decoder to determine the target register for the current operation.

[0024] •Data signals are connected to the module’s register bank for reading and writing parameters.

[0025] •The control signal is connected to the logic control unit and is used to trigger different operations of the module (such as start, stop trigger signal).

[0026] Or the connection with the master device (AXI Master): •AXI Lites interface usually acts as a slave device (Slave Device) connected to a master device (MasterDevice), such as a CPU or an external controller.

[0027] •The master device sends control commands to the interface through the AXI bus to achieve remote control of the FPGA module.

[0028] The process of configuring the parameters of the FPGA synchronous trigger module through the AXI Lites interface is as follows: 1. Select the target register: • Select the register to be configured by sending a specific address signal. For example: • Operation mode register: set to single trigger or periodic trigger.

[0029] •Frequency register: used to set the frequency of the trigger signal.

[0030] •Timestamp register: used to configure the initial timestamp value.

[0031] 2. Write parameter values: •After determining the target register, send the data signal and write the specific parameter value. For example: •Write the frequency value of the trigger signal, such as 1kHz or 10kHz.

[0032] • Set the pulse width of the trigger signal, such as 1 microsecond or 5 microseconds.

[0033] 3. Start the configuration command: •Confirm the completion of the write operation through control signals.

[0034] •If you need to read the current parameter value, you can send a read command to read the current configuration from the target register.

[0035] The start / stop trigger signal is a command signal used to control the generation of trigger signals and is sent to the FPGA synchronous trigger module through the AXI Lites interface. These signals determine whether the module starts or stops outputting trigger signals.

[0036] Start the generation of trigger signal. The module starts to output synchronous trigger signal according to the preset conditions, such as triggering the sensor to start taking pictures, or triggering the infrared light to turn on, or starting the data collection of the gyroscope. Pause the device, for example, when the sensor is stopped after the collection is completed, the output of the current trigger signal is the stop trigger signal, and the module enters the idle state.

[0037] The CLK interface is an input interface for receiving clock signals, which is used to provide the clock reference required for module operation. Clock signal: usually a periodic square wave signal with a stable frequency and duty cycle, which serves as the time reference for the entire module's internal circuit. The CLK interface is usually connected to an external clock source, such as: Crystal oscillator, host device clock output, PTP clock manager. The crystal oscillator is used to provide a stable reference clock and is usually the main clock source of the system. If the module communicates with a master device (such as a CPU or MCU) via the AXI bus, the system clock provided by the master device can be used. In scenarios where high-precision time synchronization is required, it can be connected to the synchronization clock signal provided by the PTP protocol.

[0038] The RTC time inside the tuning module is precisely synchronized through the PTP protocol. PTP (Precision Time Protocol) is a network time synchronization protocol that allows devices in the network to synchronize their clocks by exchanging time information. In this module, the acquisition of the PTP timestamp is implemented through the hardware clock manager, which is able to receive time information from the PTP server and adjust the real-time clock (RTC) inside the module accordingly. In order to ensure the accuracy of the time, the PTP tuning module communicates with the PTP server regularly to calibrate and update the time. This mechanism ensures that the RTC time inside the module can maintain high accuracy even when network conditions change or there is a delay. In addition, the module also has time deviation detection and compensation functions, which can automatically adjust the time deviation to reduce the time error caused by factors such as temperature changes and crystal aging. The precise synchronization of the RTC time inside the PTP tuning module is crucial for application scenarios that require high time accuracy, such as in high-speed data acquisition, video surveillance, industrial automation and other fields. By ensuring that all synchronization trigger events are based on accurate timestamps, the overall performance and reliability of the system can be greatly improved.

[0039] The RES_N interface is a reset signal interface used to initialize or reset the internal logic circuit of the module to ensure that the module starts running from a known state.

[0040] The module can generate precise synchronous trigger signals according to preset trigger conditions. These conditions can be the arrival of timestamps, the input of external events, or the timeout of internal timers. The generation of synchronous trigger signals is realized by the logic circuit inside the FPGA, which ensures fast signal response and extremely low latency. In high-speed data acquisition systems, these synchronous trigger signals are used to synchronize multiple data acquisition channels to ensure data consistency and accuracy. In video surveillance systems, synchronous trigger signals can be used to trigger the shutter of the camera to capture key frames. In the field of industrial automation, synchronous trigger signals are used to coordinate the actions of different mechanical parts to achieve precise timing control. The flexibility and programmability of the module enable it to adapt to a variety of application scenarios and meet diverse triggering requirements. Unlike the pps signal of Linux, the synchronous trigger signal can be configured with frequency and pulse width to adapt to different application scenarios.

[0041] The timestamp function of the synchronously latched synchronous trigger signal allows the module to immediately record the current PTP timestamp when the trigger event occurs. This mechanism is essential for events that require time stamping. For example, in high-speed data acquisition systems, it can ensure that each data point has an accurate timestamp, so that the order and time relationship of events can be accurately reconstructed in subsequent data processing and analysis. In addition, in video surveillance systems, the synchronous latching of timestamps can be used to record the shooting time of key frames for subsequent retrieval and analysis. In the field of industrial automation, the accurate recording of timestamps is also important for fault diagnosis and retrospective analysis of production processes. With this function, the system can accurately track the time of event occurrence and provide a time reference benchmark for various applications.

[0042] Specifically, the FPGA synchronization trigger module is used to perform the following steps: A configuration signal is obtained based on an axi lites interface; wherein the configuration signal includes parameters for configuring an FPGA synchronous trigger module, and the parameters of the FPGA synchronous trigger module include an operating mode of the FPGA synchronous trigger module, a clock frequency, and an initial state of a trigger signal.

[0043] Get the clock signal and synchronize the PTP timestamp based on the clock signal and configuration signal; The frequency of the output synchronization trigger signal is set based on the configuration signal; wherein the frequency of the synchronization trigger signal corresponds to the triggering timing of the synchronization acquisition device; Output a synchronous trigger signal based on a preset trigger condition, wherein the preset trigger condition includes the arrival of a timestamp, the input of an external event, or the timeout of an internal timer; the synchronous trigger signal is used to trigger a synchronous acquisition device, wherein the triggering of the synchronous acquisition device includes triggering a sensor to take a photo, turning on and off an infrared light, and collecting gyroscope data; When outputting the synchronization trigger signal, record the current PTP timestamp; The output sync latches the time stamp of the sync trigger signal.

[0044] During the module initialization phase, the parameters of the FPGA synchronous trigger module need to be configured through the AxiLites interface. This includes setting the module's operating mode, clock frequency, and the initial state of the trigger signal. During the initialization process, the Axilites interface allows the user to precisely control the module to ensure that the module is in the correct configuration state before startup. In addition, the module's internal real-time clock (RTC) time needs to be synchronized with the PTP timestamp. This step is accomplished by tuning the module's internal RTC time through PTP to ensure that the module can provide accurate timestamp information. During the initialization process, the user can set the initial time of the RTC to synchronize with the network time. Finally, module initialization also includes setting the frequency of the output synchronous trigger signal. Users can set the frequency of the trigger signal through the AxiLites interface according to the needs of the actual application scenario, thereby controlling the trigger timing of the synchronous acquisition device. This setting is critical to ensuring the accuracy and synchronization of data acquisition.

[0045] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An FPGA synchronization trigger module with PTP timestamp, characterized in that: It includes an axi lites interface, a clk interface, a res_n interface, a trigger interface and a timestamp interface, wherein the axi lites interface is used to configure the parameters of the FPGA synchronous trigger module and receive the start and stop trigger signals, the clk interface is used to receive the clock signal, the res_n interface is used to receive the reset signal, the trigger interface is used to output the synchronous trigger signal based on the preset trigger condition, and the timestamp interface is used to output the ptp 64-bit timestamp latched when the synchronous trigger signal changes from low to high, so as to be used for synchronous framing of the collected data; wherein the parameters of the FPGA synchronous trigger module include the working mode of the FPGA synchronous trigger module, the clock frequency and the initial state of the trigger signal.

2. The FPGA synchronization trigger module with PTP timestamp according to claim 1, characterized in that: The FPGA synchronization trigger module is used to perform the following steps: Obtaining a configuration signal based on an axi lites interface; wherein the configuration signal includes parameters for configuring an FPGA synchronization trigger module; Get the clock signal and synchronize the PTP timestamp based on the clock signal and configuration signal; The frequency of the output synchronization trigger signal is set based on the configuration signal; wherein the frequency of the synchronization trigger signal corresponds to the triggering timing of the synchronization acquisition device; Outputting a synchronous trigger signal based on a preset trigger condition, wherein the preset trigger condition includes the arrival of a timestamp, the input of an external event, or the timeout of an internal timer; When outputting the synchronization trigger signal, record the current PTP timestamp; The output sync latches the time stamp of the sync trigger signal.

3. The FPGA synchronization trigger module with PTP timestamp according to claim 2, characterized in that: The synchronous trigger signal is used to trigger the synchronous acquisition device, and the triggering of the synchronous acquisition device includes triggering the sensor to take pictures, turn on and off the infrared light, and collect gyroscope data.

4. The FPGA synchronization trigger module with PTP timestamp according to claim 3, characterized in that: The FPGA synchronization trigger module includes an internal PTP time tuning unit for receiving a time synchronization signal from a PTP server and adjusting a real-time clock inside the FPGA.

5. The FPGA synchronization trigger module with PTP timestamp according to claim 4, characterized in that: The PTP time tuning unit is used to perform time deviation detection and compensation to automatically adjust the time error caused by temperature change or crystal oscillator aging.

6. The FPGA synchronization trigger module with PTP timestamp according to claim 5, characterized in that: The frequency and pulse width of the synchronous trigger signal output by the trigger interface can be programmably set through the axi lites interface.

7. The FPGA synchronization trigger module with PTP timestamp according to claim 6, characterized in that: The module includes a trigger signal buffer unit for storing timestamps of multiple trigger signals in a high-frequency trigger scenario for subsequent data framing and time series analysis.

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